JP2851964B2 - Test circuit for semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device (D
More specifically, the present invention relates to a test circuit thereof.

[0002]

2. Description of the Related Art In recent years, a test circuit for shortening a test time such as a parallel test of a plurality of bits has been produced with an increase in storage capacity of a semiconductor memory device. In a conventional test circuit, the same data is written to a plurality of bits to be tested at the same time, and the data is compared at the time of reading, and if there is at least one different data, it is determined to be defective.

However, the above-mentioned conventional test circuit is:
The same data must be written to a plurality of bits to be tested, and the written data must be compared at the time of reading. For this reason, there is a disadvantage that even if all the data are erroneous, it is determined that the data is good.

Therefore, the applicant of the present invention does not need to compare written data, and can judge whether each data is correct or not, and can judge that all data are erroneous even if all data are erroneous. Test circuit, Japanese Patent Application Hei 1
-304983.

FIG. 4 shows a test circuit of the semiconductor memory device.
As shown in FIG. 1, upon receiving the data selection signal ST, the data input signal D and the complementary data input signal / D which are input at any one of the high and low levels of the opposite phases based on the data selection signal ST are generated. a first switch SW ₁ to one signal selected and the output of out, height or level of the expected value output signal line holding is temporarily given S
And a fail signal line bar S which is given a phase opposite to that of the output signal line and steadily holds the same, and a first switch SW provided between the output signal line S and the fail signal line bar S. When the data input signal D matches the expected value given to the second switch SW ₂ which is turned on or off by the signal from the _first input signal S, the data input signal D and the complementary data input signal D signals towards which the second off the switch SW ₂ of the first switch SW ₁
On the other hand, when the expected value and the data input signal D do not match, the second switch SW _{2 of} the two signals is output.
It is characterized in that it comprises a data signal selection circuit 2 for outputting a data selection signal ST to output a signal of the direction to be turned to the first switch SW _1. W ₁ ,... Are word lines and M is a memory dial.

It is desirable that a plurality of the first and second switches are provided, and data on a plurality of data lines are determined simultaneously.

When the data input signal D matches the expected value, the first switch SW based on the data selection signal ST
The second switch SW ₂ is turned off by _one. Therefore, the expected value is output from the output signal line S as it is.
When the data input signal D is a mismatch in the expected value and the negative phase, the first switch SW ₁ second switch SW ₂ is turned on based on the data selection signal ST, and the fail signal line bar S and output signal lines S Is made conductive. As a result, the level of the output signal line S changes to the level of the fail signal line S that constantly holds the level opposite to that of the output signal line S. Therefore, after this change, a level having a phase opposite to the expected value is output from the output signal line S. As described above, the test is performed with the pair of data input signals D and D from one bit. Therefore, it is not necessary to compare data input signals from a plurality of bits. Also, by providing a plurality of first and second switches, data input signals from a plurality of bits are individually determined, and even if all data are erroneous, it can be recognized as a failure. That is, by arranging the first switch SW ₁ and the second switch SW ₂ by the number of the data input terminal D, and the test in advance the path signal to precharge the output signal line S, the data selection signal ST data By giving the signal to the selection signal terminal, a pass signal is output when all data is correct, and a fail signal bar S is output when there is at least one error in the data, so that a plurality of data can be determined simultaneously. it can.

Hereinafter, the above-described conventional test circuit will be described in detail with reference to the illustrated example.

FIG. 5 shows a test circuit of a semiconductor memory device as a specific example of the conventional test circuit. FIG. 6 shows input waveforms of control signals φ ₁ , φ ₂ and φ ₃ inputted to the test circuit. Is shown.

In FIG. 5, 1 is an expected value generation circuit, 2 is a data signal selection circuit, 3 to 8 are inverters, and 9 is a P-type M
OS transistors, 10 to 14 are N-type MOS transistors, 15 and 16 are NAND (Negative AND) gates, and the transistors 12 to 14 use a first switch SW.
_1, the second switch SW ₂ is composed of a transistor 11. Further, the transistors 9 and 10 constitute a switch SW ₃ for temporarily holding the expected value to the output signal line S.

This test circuit checks whether the expected value output from the expected value generating circuit 1 and the level of the data line D are the same as follows. Here, the expected value is a binary value of VCC or GND. Data lines D and / D always receive data having phases opposite to each other. The one data is obtained by inputting a signal output from one bit terminal to an inverter (not shown), and the other data is obtained directly from the bit terminal.

First, as shown in FIG. 6, the signal φ ₁ falls (t ₁ ), and the N-type
S transistors 13 and 14 are turned off. Next, the signal φ ₂ falls (t ₂ ), the transistor 12 is turned on through the inverter 8, and the node connected to the gate of the N-type MOS transistor 11 is discharged. As a result, the N-type MOS transistor 11 is turned off. Further, the signal φ ₃ falls (t ₃ ), and the P-type MOS transistor 9
Then, the N-type MOS transistor 10 is turned on to give an expected value to the output signal line S.

In order to compare the expected value with the level of the data line D, first, the signals φ ₂ and φ ₃ rise (t ₄ ), and the transistors 9, 10 and 12 are turned off. Next, φ ₁ rises (t ₅ ), and the data signal selection circuit 2 is enabled, that is, put into an operable state in response to the expected value.

When the expected value is VCC, the transistor 13 is turned on through the data signal selection circuit 2, and the output of the data line D is input to the gate of the N-type transistor 11. Here, if the expected value and the level of the data line D match, the level of the data line D is GND, so that the N-type transistor 11 remains off and the output signal line S The value is output as is. Conversely, if the expected value and the level of the data line D do not match, the data line D is at VCC, so that the N-type transistor 11 is turned on, and the output signal line S goes to the level of the fail signal line S. As a result, data having a phase opposite to the expected value is output to the output signal line S.

On the other hand, when the expected value is GND, the transistor 14 is turned on through the data signal selection circuit 2, and the level of the data line D is output to the gate of the N-type transistor 11. Here, if the expected value matches the output of the data line D, the output of the data line D is GND, so that the N-type transistor 11 remains off and the output signal line S has the expected value. Is output as is. Conversely, if the expected value and the level of the data line D do not match, the N-type transistor 11 is turned on because the data line D is at VCC, and the output signal line S is rewritten to the level of the fail signal line S. As a result, data having a phase opposite to the expected value is output to the output signal line S.

As described above, if the expected value matches the output of the data line, the transistor 11 is turned off and the expected value is output to the output signal line S. If the expected value and the output of the data line do not match, the transistor 11 is turned on. As a result, the level of the fail signal line S, that is, data having a phase opposite to the expected value is output to the output signal line S.

In this circuit, the data selection signal ST from the data signal selection circuit 2, the output signal line S, and the fail signal line bar S can be shared by a plurality of data line pairs.
This is applied to, for example, a semiconductor memory device (DRAM, SRAM, R
OM), the data output to the plurality of data lines D and bar D can be determined at a time, so that the device test time can be reduced. Further, it is possible to detect that even if the data of all the bits is incorrect, it is an error. Further, it is not necessary to use a complicated circuit configuration such as EXOR.

[0018]

In the above-described conventional test circuit, data can be changed for each word line, but data cannot be changed for each data line pair. Therefore, the interference between the data line pairs could not be determined by the line test.

The present invention has been made in view of the above points, and provides a test circuit capable of changing data for each data line pair, thereby enabling interference between data line pairs to be determined by a line test. Things.

[0020]

As shown in FIG. 1, a test circuit for a semiconductor memory device according to the present invention is provided for each data line pair (D _i , bar D _i ) and includes a data selection signal ST.
In response to this, based on the data selection signal ST, a plurality of data input signals and complementary data input signals, which are input at any one of high and low levels opposite to each other, are selected and output. First switches SW ₁₁ , SW ₁₂ , S
W ₁₃ ,..., An output signal line S which is given a high or low expected value and temporarily holds the signal, and a signal having a level opposite to the expected value given to the output signal line S , A fail signal line bar S that constantly holds and receives
Provided between the output signal line S and the fail signal line bar S, the first switch _{SW 11, SW 12, SW 13} , ...
, Which are turned on or off by a signal from the second switch SW ₂₁ , SW ₂₂ , SW ₂₃ ,..., The expected value given to the output signal line S and the (2n−1) th (or 2n)
, Where n is a natural number), the signal for turning off the second switch (SW ₂₁ , SW ₂₂ ,...) Is selected from the data input signal and the complementary data input signal. (2n-1) -th (or 2n-th) of the first switch SW _11, SW _13, ... (or SW _12,
SW ₁₄ ,...).
When the (n-1) -th (or 2n-th) data input signal does not match, of the two signals, the signal for turning on the second switch (SW ₂₁ , SW ₂₂ ,. -1) th (or 2n-th) of the first switch SW _11, SW _13, ... (or SW _12, SW _14,
..), And when the expected value does not match the 2n-th (or (2n-1) -th) data input signal, the signal for turning off the second switch is selected from the two signals. 2n th (or (2n-1) th) of the first switch SW _12, SW _14, ... (or SW _11,
SW ₁₃ ,...).
When the second (or (2n-1) th) data input signal matches, the signal for turning on the second switch of the two signals is changed to the 2nth (or (2n-
1) th) of the first switch SW _12, SW _14, ...
(Or SW ₁₁ , SW ₁₃ ,...) To output a data selection signal ST.

[0021]

[Action] memory cell M ₁₁ in data 1, data 0 to the memory cell M _12, the data 1 into the memory cell M _13, the memory cell M ₁₄
For example, data is written for each data line pair, such as data 0. The expected value is 1. After that, a line test is executed in exactly the same manner as in the related art. At this time, if the data writing is correctly performed, the 0 level is applied to the gates of all the second switches _SW2i ,
The output signal line S holds one level. On the other hand, when the data in any one of the memory cells is inverted due to the interference between the pair of data lines, one level is applied to the gate of the second switch corresponding to that memory cell, and the switch is turned on. Thus, the output signal line S changes to 0 level.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.

FIG. 1 shows a test circuit of a semiconductor memory device according to an embodiment of the present invention, and FIG. 2 shows input waveforms of control signals φ ₁ , φ ₂ and φ ₃ inputted to the test circuit. I have.

In FIG. 1, 1 is an expected value generation circuit, 2 is a data signal selection circuit, 3 to 8 are inverters, and 9 is a P-type M
OS transistor, 10, 11 ₁ , 11 ₂ ,..., 12, 1
_{3 1, 13 2, ...,} 14 1, 14 2, ... N -type MOS transistor, 15 and 16 is a NAND (NAND) gates, transistors _{12,13 i, 14 i (i =} 1,2,
..) Constitute the first switch SW _1i and the transistor 11 _i constitutes the second switch SW _2i . Further, the transistors 9 and 10 constitute a switch SW ₃ for temporarily holding the expected value to the output signal line S. Further, W ₁ ,
W ₂ ,... Are word lines, _Di , bar _Di are each data line pair, M
_ij (i = 1, 2,..., j = 1, 2,...) are respective memory cells.

The difference from the conventional test circuit shown in FIG. 5 lies in how transistors 13 _i and 14 _i are provided, and the other configuration is the same. That is, in the conventional test circuit, all of the transistors 13 are connected to the data line D.
_i, and all the transistors 14 are connected to the data line D _i
On the other hand, in the test circuit of the present invention, each transistor is
, Data lines D _i , data lines D _i ,... Are alternately inserted.

Next, the operation will be described.

An example of a test of the memory cells M ₁₁ , M ₁₂ ,... Connected to the word line W ₁ will be described. First, the data 1 into the memory cell M _11, the data 0 to the memory cell M _12, the data 1 into the memory cell M _13, by changing the data for each of the data line pair and so data 0 in the memory cell M ₁₄ performs writing. The expected value is 1.

First, as shown in FIG. 2, the signal φ ₁ falls (t ₁ ), and the N-type M
The OS transistors 13 _i and 14 _i are turned off. next,
When the signal φ ₂ falls (t ₂ ), the transistor 12 is turned on through the inverter 8 and the N-type MOS transistor 11 is turned on.
Discharge the node connected to the gate of _i . As a result, the N-type MOS transistor 11i is turned off.
Further, the signal φ ₃ falls (t ₃ ), the P-type MOS transistor 9 and the N-type MOS transistor 10 are turned on, and the expected value 1 is given to the output signal line S.

[0029] To make a comparison between the level of the expected value and the data line D _i, first raises the signals phi ₂ and φ ₃ (t _4),
The transistors 9, 10 and 12 are turned off. Next, φ ₁
Rise (t ₅ ) to bring the data signal selection circuit 2 into an enabled state, that is, a state in which it can operate in response to an expected value. Since the expected value is 1, the data signal selection circuit 2 outputs the data selection signal ST that turns on the transistor 13 _i and turns off the transistor 14 _i .

If the data writing is correctly performed,
The level of the data line bar D _2n-1 (n = 1, 2,...) Is 0,
Further, since the level of the data line D _2n also becomes 0, the 0 level is applied to the gates of all the second switches SW _2i ,
Since the second switches SW _2i are all turned off, the output signal line S holds the expected value level 1.

On the other hand, it is assumed that the data in any one of the memory cells has been inverted due to the interference between the data line pairs. For example, when the data of the memory cell M ₁₃ is assumed to have been inverted to 0, the level of the data line bar D ₃ becomes 1, the second switch SW ₂₃ is turned on, the level of the output signal line S is changed to 0 level I do. The same applies to the case where data inversion has occurred in other memory cells.

Therefore, data line pair interference can be determined by a line test.

In the case of a test of a memory cell connected to the word line W ₂ , write data is similarly set to 1, 0,
When 1, 0, ..., the expected value is set to 0. Alternatively, when the expected values are the same, the write data is set to 0.
(M ₂₁ ), 1 (M ₂₂ ), 0 (M ₂₃ ), 1 (M ₂₄ ),...

The N-type MOS transistors 11 _i , 1
P-type MOS or CMOS can be used instead of 2, 13 _i and 14 _i , and the first switch SW _1i may be replaced with a logic circuit as shown in FIG. 3, for example.

[0035]

As described above in detail, according to the present invention, data can be changed for each data line pair, thereby making it possible to determine interference between data line pairs by a line test. A circuit can be provided.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a test circuit according to one embodiment of the present invention.

FIG. 2 is a signal waveform diagram of a control signal for operating the test circuit.

FIG. 3 is a diagram showing an example in which a part of the test circuit is modified.

FIG. 4 is a block diagram showing a conventional test circuit.

FIG. 5 is a circuit diagram showing a conventional test circuit.

FIG. 6 is a signal waveform diagram of a control signal for operating the conventional test circuit.

[Explanation of symbols]

_{Reference Signs List} 1 Expected value generation circuit 2 Data signal selection circuit SW _1i First switch SW _2i Second switch D _i , D _i Data line pair S Output signal line S F Fail signal line ST Data selection signal

Claims (1)

(57) [Claims] A data input signal is provided for each data line pair and receives a data selection signal and, based on the data selection signal, a data input signal and a complementary data input that are input at any one of high and low levels opposite to each other in phase. A plurality of first switches for selecting and outputting one of the signals, an output signal line to which an expected value of any one of high and low levels is given and temporarily held, A fail signal line that is provided with a signal having a level opposite to that of the expected value and steadily holds the signal, and is provided between the output signal line and the fail signal line, and a signal from the first switch. A plurality of second switches that are turned on or off when the expected value given to the output signal line matches the (2n-1) th (or 2nth, where n is a natural number) data input signal , Data entry And the complementary data input signal, the signal for turning off the second switch is output to the (2n-1) th (or 2nth) first switch, while the expected value and the (2n) -1)
When the data input signal does not match the (n) th data input signal, the signal for turning on the second switch of the two signals is changed to the (2n-1) th (or 2nth) signal.
And when the expected value does not match the 2n-th (or (2n-1) -th) data input signal, the second switch of the two signals is turned off. Signal to the 2nth (or (2n
-1) th) while the first switch outputs the signal.
The expected value and the 2nth (or (2n-1) th)
When the data input signal of
A data signal selection circuit for outputting a data selection signal for outputting a signal for turning on the second switch to the 2n-th (or (2n-1) -th) first switch. A test circuit for a semiconductor memory device.