JP3557774B2 - Semiconductor storage device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device.
[0002]
[Prior art]
When a test is performed on a memory core built in a conventional logic IC chip, data input / output is performed via a control signal terminal for controlling each operation of the memory core taken out and a data input / output terminal. Be done.
[0003]
FIG. 7 is a block diagram showing a configuration of such a memory core.
7, 10 is a row address buffer, 20 is a row predecoder, 30 is a row decoder, 40a is a column address buffer, 50a is a column predecoder, 60a is a column selector, 70 is an input / output buffer, 100 is a memory array, D_INAnd D_OUTIndicates a data input terminal and a data output terminal, respectively.
[0004]
As shown, the row address ROWADR is input to the row address buffer 10, input to the row predecoder 20 via the row address buffer 10, and then input to the row decoder 30. A predetermined word line is selected and set to an active state by row predecoder 20 and row decoder 30 in accordance with the input row address ROWADR.
[0005]
On the other hand, the column address CLMADR is input to the column address buffer 40a, input to the column predecoder 50a via the column address buffer 40a, and further input to the column selector 60a. A predetermined bit line is selected by the column predecoder 50a and the column selector 60a according to the input column address CLMADR, and set to an active state.
[0006]
As described above, the memory cells arranged at the intersections of these signal lines are selected by the selected word line and the selected bit line set to the active state, and data input / output is performed via the input / output buffer 70a. Be done.
For example, at the time of data input, that is, at the time of memory writing, the data input terminal D_INIs written to the selected memory cell via the input / output buffer 70a and the selected bit line.
On the other hand, at the time of data output, that is, at the time of memory reading, storage data is read from the selected memory cell, and the data output terminal D is output via the selected bit line and the input / output buffer 70a._OUTIs output to
[0007]
[Problems to be solved by the invention]
By the way, in the above-mentioned conventional memory core, the number of signal terminals and data input / output terminals of the memory core is determined depending on the application. As the capacity of the memory core increases, the test time increases.
Data input / output for each applicationPowerIf the number of terminals is changed, there is a problem that a test pattern must be created separately, and the memory core itself must be newly developed for each application.
[0008]
The present invention has been made in view of such circumstances, and has as its object the number of data input / output terminals can be easily changed by an external signal, multiple bits can be tested simultaneously regardless of the application, and the test time and test pattern can be adjusted. It is an object of the present invention to provide a semiconductor memory device that can reduce the number of development steps and reduce application dependency.
[0009]
[Means for Solving the Problems]
In order to achieve the above object, the present invention providesA memory array in which a plurality of memory cells are arranged, and selecting a memory cell addressed by a selected word line and a selected bit line set to an active state according to a row address and a column address; Through the aboveA semiconductor memory device for writing or reading data to or from a memory array,An address buffer circuit having a plurality of address buffer circuits for outputting the inputted plurality of column address data as an in-phase signal and an inverted signal, respectively, and receiving the lowest one of the plurality of address buffer circuits; When the bit width control signal is inputted at the first level, two signals, ie, an in-phase signal and an inverted signal of the inputted least significant column address data, are outputted, and the bit width control signal is outputted at the second level. And a column address buffer that outputs two signals of a predetermined same level irrespective of the input level of the least significant column address data, and output from the plurality of address buffer circuits of the column address buffer circuit. Set a predetermined column line among a plurality of column lines to an active state based on a plurality of signals. A column predecoder and a column selector having a plurality of switch circuits each connected to a different one of the column lines and making the bit line and the data bus conductive when the column line is in an active state; The input / output circuit receives the bit width control signal and the two output signals of the lowermost address buffer circuit of the column address buffer, and when the bit width control signal is at the first level, provides one data bus. An output buffer for outputting read data of two data buses when the bit width control signal is at the second level, and a lowermost address buffer of the bit width control signal and the column address buffer In response to the two output signals of the circuit, when the bit width control signal is at the first level, two data signals are output. The input data of the data input terminal is output to two data buses as write data, and when the bit width control signal is at the second level, the input data of one data input terminal is output to one data bus as write data. With an input buffer.
[0010]
Further, the semiconductor device of the present invention is incorporated in an ASIC memory.
[0011]
According to the present invention, an input terminal for an external bit width control signal is provided in the semiconductor memory device, and the number of input / output bits of the data input / output circuit is set by the bit width control signal input to the input terminal. .
For example, among a plurality of input / output terminals in the input / output circuit, a predetermined number of input / output terminals are selected according to the bit width control signal, and data input / output is performed through the selected input / output terminals. Done.
As a result, the number of data input / output terminals can be easily changed by an external signal, and application dependency can be reduced.
[0012]
In addition, by incorporating the above-described memory core into the ASIC memory, multiple bits can be tested simultaneously regardless of the application, and the test time and the number of test pattern development steps can be reduced.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a block diagram showing one embodiment of a semiconductor memory device according to the present invention.
In FIG. 1, 10 is a row address buffer, 20 is a row predecoder, 30 is a row decoder, 40 is a column address buffer, 50 is a column predecoder, 60 is a column selector, 70 is an input / output buffer, 100 is a memory array,_INAnd D_OUTIndicates a data input terminal and a data output terminal, respectively.
Further, ROWADR indicates a row address, CLMADR indicates a column address, and BWC indicates a bit width control signal.
[0014]
As shown, the row address ROWADR is input to the row address buffer 10, the column address CLMADR is input to the column address buffer 40, and the bit width control signal BWC is input to the column address buffer 40 and the input / output buffer 70, respectively.
[0015]
The row address ROWADR input to the row address buffer 10 is input to the row predecoder 20 via the row address buffer 10 and further input to the row decoder 30. A predetermined word line is selected by the row predecoder 20 and the row decoder 30 in accordance with the input row address ROWADR, and set to an active state.
[0016]
The column address CLMADR input to the column address buffer 40 is input to the column predecoder 50 via the column address buffer 40, and further input to the column selector 60. A predetermined bit line is selected by the column predecoder 50 and the column selector 60 according to the input column address CLMADR, and set to an active state.
[0017]
Then, the memory cell arranged at the intersection of the selected word line and the selected bit line set in the active state is selected, and data is input / output.
For example, when writing, the input terminal D_INIs read by the input / output buffer 70 and written to the selected memory cell via the selected bit line. At the time of reading, the data stored in the selected memory cell is read out to the selected bit line, and output via the input / output buffer 70 to the output terminal D._OUTIs output to
[0018]
Here, the bit width control signal BWC is input to each of the column address buffer 40 and the input / output buffer 70, and the number of input / output data bits is set according to the bit width control signal BWC.
Hereinafter, the configuration and operation of each part of the column address buffer 40, the column predecoder 50, the column selector 60, the input / output buffer 70, and the memory array 100 constituting the memory core will be described.
[0019]
FIG. 2 is a circuit diagram showing a configuration of the column address buffer 40.
In FIG. 2, Y₀, Y₁, ..., Y_N-1, Y_NIs an input terminal of a column address CLMADR, φ is a bit width control signal BWC input terminal, AY₀Is the input terminal Y₀AY, the in-phase signal of the address data input to₀B is input terminal Y₀AY, the inverted signal of the address data input to AY₁Is the input terminal Y₁AY, the in-phase signal of the address data input to₁B is input terminal Y₁AY, the inverted signal of the address data input to AY_N-1Is the input terminal Y_N-1AY, the in-phase signal of the address data input to_N-1B is input terminal Y_N-1AY, the inverted signal of the address data input to AY_NIs the input terminal Y_NAY, the in-phase signal of the address data input to_NB is input terminal Y_N, The output terminals of the inversion signal of the address data input to are shown.
[0020]
As shown, the column address input terminal Y₀, Y₁, ..., Y_N-1The column address data input to the input terminals A and Y are output via a buffer circuit to the output terminal AY of the in-phase signal.₀, AY₁, ..., AY_N-1And an inverted signal output terminal AY via an inverter.₀B, AY₁B, ..., AY_N-1B.
For example, as shown in FIG.₀The column address data input to the buffer circuit BUF₀Through an in-phase signal output terminal AY₀To the inverter INV₀Signal output terminal AY via₀B.
[0021]
The buffer circuit of the lowest address of the column address buffer 40 has a different structure from other buffer circuits. The operation of this buffer circuit is controlled by the bit width control signal BWC input to the input terminal φ.
Input terminal Y of lowest address_NIs the OR circuit OC_B1One input terminal and the inverter INV_NOf the inverter INV_NOutput terminal is OR circuit OC_B2Connected to one of the input terminals. Further, the input terminal φ of the bit width control signal BWC is connected to the OR circuit OC._B1And OR circuit OC_B2Is connected to the other input terminal.
[0022]
Low level on input terminal φ(First level)When the bit width control signal BWC is input, the input terminal Y_N Signal output terminal AY of the in-phase signal of the lowest address input to_N And the inverted signal is output to an inverted signal output terminal AY_N B.
On the other hand, input terminal φ is high level(2nd level)When the bit width control signal BWC is input, the OR circuit OC_B1And OR circuit OC_B2Output a high-level signal, that is, the in-phase signal output terminal AY of the lowest address data._N And inverted signal output terminal AY_N
A high level signal is output to B.
[0023]
FIG. 3 is a circuit diagram showing a configuration of the column predecoder 50.
In FIG. 3, AC₀, AC₁, ..., AC_2N, AC_{2N + 1}Is the AND circuit, CL₀, CL₁, ..., CL_2N, CL_{2N + 1}Indicates a column line.
As shown, the column predecoder 50 includes a plurality of AND circuits AC.₀, AC₁, ..., AC_2N, AC_{2N + 1}And these AND circuits AC₀, AC₁, ..., AC_2N, AC_{2N + 1}The in-phase signal and the inverted signal of the address data from the column address buffer 40 are input in different combinations to the input terminals.
Note that these AND circuits AC₀, AC₁, ..., AC_2N, AC_{2N + 1}Is supplied with a column predecoder enable signal YDE, and the operation of the column predecoder 50 is controlled by the enable signal YDE.
[0024]
For example, when the enable signal YDE is at a high level, the AND circuit AC₀, AC₁, ..., AC_2N, AC_{2N + 1}Corresponds to the in-phase signal of the address data input to each input terminal or the inverted signal thereof, and the column line CL₀, CL₁, ..., CL_2N, CL_{2N + 1}Are set to the active state.
For example, the lowest address data input terminal Y_NWhen a low-level signal is input to the even-numbered column line, the even-numbered column line is set to the active state, and the lowest address data input terminal Y_NWhen a high-level signal is input to the first column, the odd-numbered column lines are set to the active state.
[0025]
FIG. 4 is a circuit diagram showing a configuration of the memory array 100 and the column selector 60.
In FIG. 4, WL₀, WL₁, ..., WL_NIs the word line, CL₀, CL₁, ..., CL_2N, CL_{2N + 1}Is the column line, BL₀, / BL₀, BL₁, / BL₁, ..., BL_{2N + 1}, / BL_{2N + 1}Is the bit line, MC₀₀, MC₀₁, ..., MC_{2N + 1, N}Is a memory cell, BUS₀, / BUS₀, BUS₁, / BUS₁Is the data bus, SW_0A, SW_0B, SW_1A, SW_1B, ..., SW_{2N + 1A}, SW_{2N + 1B}Indicates a switching circuit.
[0026]
In memory array 100, memory cell MC₀₀, MC₀₁,, MC_{2N + 1, N}Are arranged in a matrix, and a memory array of 2N + 2 rows and N + 1 columns is configured. Each memory cell arranged in each column is connected to a word line WL.₀, WL₁, ..., WL_{N + 1}, And the memory cells arranged in each row are paired with bit lines BL₀, / BL₀, BL₁, / BL₁, ..., BL_{2N + 1}, / BL_{2N + 1}It is connected to the. Bit line BL₀, / BL₀, BL₁, / BL₁, ..., BL_{2N + 1}, / BL_{2N + 1}Is a pair of switching circuits SW_0A, SW_0B, SW_1A, SW_1B, ..., SW_{2N + 1A}, SW_{2N + 1B}Via the data bus BUS₀, / BUS₀, BUS₁, / BUS₁It is connected to the.
[0027]
Switching circuit SW_0A, SW_0B, SW_1A, SW_1B, ..., SW_{2N + 1A}, SW_{2N + 1B}Is formed of, for example, nMOS transistors, and the gate electrodes of these nMOS transistors are connected to column lines CL, respectively.₀, CL₁, ..., CL_2N, CL_{2N + 1}It is connected to the.
For example, according to the input column address CLMADR, a predetermined column line CL_iAre set to the high level state, that is, the active state, the paired switching circuits SW_iA, SW_iBAre set to the conductive state, and the odd-numbered bit lines BL_i, / BL_iIs the data bus BUS₀, / BUS₀And the even-numbered bit lines BL_i, / BL_iIs the data bus BUS₁, / BUS₁Connected to each other.
[0028]
Word line WL₀, WL₁, ..., WL_{N + 1}Are respectively connected to the row decoder 30, and the row decoder 30 outputs a predetermined word line WL according to the input row address ROWADR._jIs set to the active state, the selected word line WL_jAnd the selected bit line BL_i, / BL_iMemory cell MC located at the intersection of_jiIs selected and the corresponding memory cell MC_ijIs written or read.
[0029]
For example, when data is read, the selected memory cell MC_ijIs stored in the bit line BL_iAnd the inverted data of the stored data is_iAnd the switching circuit SW_iA, SW_iBVia the data bus BUS_i, / BUS_iIs output to
On the other hand, when data is written, the data bus BUS_i, / BUS_iIs applied to the switching circuit SW, respectively._iA, SW_iBThrough the bit line BL_i, / BL_i, And further selected memory cell MC_ijIs written to.
[0030]
FIG. 5 is a circuit diagram showing a configuration of the input / output buffer 70.
5, 207 are AND circuits, 208, 209 are OR circuits, 210, 211,..., 215 are inverters, 216, 217, 218, 219 are output buffers, D_OUT0, D_OUT1Is the data output terminal, D_IN0, D_IN1Is the data input terminal, DBUS₀, / DBUS₀, DBUS₁, / DBUS₁Indicates input terminals to the data bus.
FIG. 5A is a circuit diagram of a data output buffer, and FIG. 5B is a circuit diagram of a data input buffer.
[0031]
As shown in FIG. 5A, the data output buffer includes AND circuits 201, 202, and 203, an OR circuit 208, and an inverter 210.
The input terminals of the AND circuit 201 are connected to the data bus BUS, respectively.₀ , Column addressInversion signal output terminal AY _N BAnd the input terminals of the AND circuit 202 are connected to the data bus BUS, respectively.₁ , Column addressIn-phase signal output terminal AY _N And the output terminal of the inverter 210.
An input terminal of inverter 210 is connected to input terminal φ of bit width control signal BWC, and an input terminal of AND circuit 203 is connected to data bus BUS.₁ And the input terminal φ of the bit width control signal BWC.
The input terminal of the OR circuit 208 is connected to the output terminals of the AND circuits 201 and 202, respectively, and the output terminal of the OR circuit 208 is connected to the data output terminal D._OUT0And the output terminal of the AND circuit 203 is connected to the data output terminal D._OUT1It is connected to the.
[0032]
In the data output buffer having such a configuration, the number of data output bits is controlled according to the bit width control signal BWC.
For example, when the high-level bit width control signal BWC is applied to the input terminal φ, the data bus BUS₁Is applied to the data output terminal D via the AND circuit 203._OUT1Is output to At this time, since a low-level signal is output to the output terminal of the inverter 210, a low-level signal is output to the output terminal of the AND circuit 202.
[0033]
As shown in FIG. 2, when the bit width control signal BWC is set to a high level, the inverted signal output terminal AY of the column address data is output._NSince a high-level signal is output to B, the output terminal BUS of the data bus₀Is input to the input terminal of the OR circuit 208 via the AND circuit 201, and further, the data output terminal D is output via the OR circuit 208._OUT0Is output to
[0034]
On the other hand, when the low-level bit width control signal BWC is applied to the input terminal φ, the AND circuit 203 outputs a low-level signal, that is, the data output terminal D_OUT1To output a low-level signal.
Further, since a high-level signal is output to the output terminal of the inverter 210, the data output terminal D_OUT0Output signal from the column address input terminal Y_NIs determined by the least significant data of the column data applied to.
[0035]
For example, when the least significant data of the column data is at the high level, the column address terminal AY_NTo the column address terminal AY_NSince a low level signal is applied to B, the data bus BUS₁Is applied to the output terminal of the data output terminal D via the AND circuit 202 and the OR circuit 208._OUT0Is output to
When the least significant data of the column data is low level, the column address terminal AY_NB, a high level signal is applied to the column address terminal AY._NIs applied to the data bus BUS.₀Applied to the output terminal of the data output terminal D via the AND circuit 201 and the OR circuit 208._OUT0Is output to
[0036]
As shown in FIG. 5B, the data input buffer includes AND circuits 204, 205,..., 207, an OR circuit 209, inverters 211, 212,..., 215 and output buffers 216, 217, 218, 219. I have.
[0037]
The input terminal of inverter 211 is connected to input terminal φ of bit width control signal BWC, the output terminal of inverter 211 is connected to one input terminal of AND circuit 207, and the other input terminal of AND circuit 207 is data input terminal D._IN1It is connected to the.
One input terminal of the AND circuit 206 is a data input terminal D_IN0And the other input terminal is connected to the input terminal φ of the bit width control signal BWC.
[0038]
One input terminal of the AND circuit 204 is a column address terminal AY_NB and the other input terminal is connected to the input enable signal input terminal WE.
The output terminal of the AND circuit 204 is connected to the input terminal of the inverter 212, and further connected to the positive enable signal terminals of the output buffers 216, 217. The input terminal of the output buffer 216 is the data input terminal D_IN0And the output terminal is the input terminal DBUS of the data bus.₀It is connected to the. The input terminal of the inverter 213 is the data input terminal D_IN0, And the output terminal is connected to the input terminal of the output buffer 217. The output terminal of the output buffer 217 is the input terminal of the data bus / DBUS₀It is connected to the.
The output terminal of the inverter 212 is connected to the negative enable signal input terminals of the output buffers 216 and 217.
[0039]
One input terminal of the AND circuit 205 is a column address terminal AY_NAnd the other input terminal is connected to the input enable signal input terminal WE.
The output terminal of the AND circuit 205 is connected to the input terminal of the inverter 214, and further connected to the positive enable signal terminals of the output buffers 218 and 219. The input terminal of the output buffer 218 is connected to the output terminal of the OR circuit 209, and the output terminal is the input terminal DBUS of the data bus.₁It is connected to the. The input terminal of the inverter 215 is connected to the output terminal of the OR circuit 209, and the output terminal is connected to the input terminal of the output buffer 219. The output terminal of the output buffer 219 is the input terminal of the data bus / DBUS₁It is connected to the.
The output terminal of the inverter 214 is connected to the negative enable signal input terminals of the output buffers 218 and 219.
[0040]
In the configuration of the data input buffer described above, the bit width of the input data is controlled by the bit width control signal BWC input to the input terminal φ.
When the high-level bit width control signal BWC is input to the input terminal φ, the data input terminal D_IN0 Is input to the input terminal of the OR circuit 209 via the AND circuit 206, and further input to the output buffer 218 and the inverter 215 via the OR circuit 209. As shown in FIG. 2, when a high-level bit width control signal BWC is input to the input terminal φ, the column addressTerminalAY_N Is set to a high level, when a low-level signal is applied to the enable signal input terminal WE, a low-level signal is output to the output terminal of the AND circuit 205, and both the output buffers 218 and 219 are non-conductive. State is set, no data is output to the data bus, and the rising edge of the enable signal input terminal WEInThen, the signal at the output terminal of the AND circuit 205 is switched from low level to high level, and both the output buffers 218 and 219 are switched to the conductive state.
[0041]
Therefore, the data input terminal D_IN0Is input to the input terminal of the output buffer 218 via the AND circuit 206 and the OR circuit 209, further inverted via the inverter 215, and input to the input terminal of the output buffer 219. Then, at the rising edge of the enable signal input terminal WE, both the output buffers 218 and 219 are switched to the conductive state, and the data input to the input terminals of these output buffers are respectively input to the data bus input terminal DBUS.₁, / DBUS₁Is output to
[0042]
At the same time, the data input terminal D_IN0Is output to the input terminal of the output buffer 216, further inverted via the inverter 213, and output to the input terminal of the output buffer 217. At the rising edge of the enable signal input terminal WE, the level of the signal output to the output terminal of the AND circuit 204 switches from low level to high level, and both the output buffers 216 and 217 are switched from non-conductive to conductive. , The data input to the input terminals of these output buffers are respectively applied to data bus input terminals DBUS.₀, / DBUS₀Is output to
[0043]
On the other hand, when a low-level signal is applied to the bit width control signal BWC input terminal φ, a high-level signal is output to the output terminal of the inverter 211._IN1Is input to the input terminal of the output buffer 218 via the AND circuit 207 and the OR circuit 209, further inverted via the inverter 215, and input to the input terminal of the output buffer 219.
[0044]
At the same time, the data input terminal D_IN0Is input to the input terminal of the output buffer 216, further inverted via the inverter 213, and input to the input terminal of the output buffer 217.
[0045]
Column address input terminal Y_NWhen high-level column address data is input to the column address terminal AY_NHigh level, column address terminal AY_NSince a low level signal is output to B, when the signal at the enable signal input terminal WE is switched from low level to high level, the signal output to the output terminal of the AND circuit 205 is switched from low level to high level. The output buffers 218 and 219 are switched to the conductive state, and the data input terminal D_IN1Is input to the data bus input terminal DBUS via the AND circuit 207 and the OR circuit 209 and further via the output buffer 218.₁And the signal at the output terminal of the OR circuit 209 is inverted via the inverter 215, and the data bus input terminal / DBUS is output via the output buffer 219.₁Is output to
[0046]
Further, at the rising edge of enable signal input terminal WE, output buffers 216 and 217 are switched to the conductive state, so that data input terminal D_IN0Is input to the data bus input terminal DBUS via the output buffer 216.₀To the data input terminal D_IN0Is inverted through an inverter 213, and the data bus input terminal / DBUS is output through an output buffer 217.₀Is output to
[0047]
As described above, when the bit width control signal BWC is set to the high level, the data input terminal D is at the rising edge of the enable signal input terminal WE._IN0Are input to the data bus input terminal DBUS, respectively.₀, / DBUS₀, DBUS₁, / DBUS₁Is output to
On the other hand, when the bit width control signal BWC is set to the low level, the least significant data Y of the column address at the rising edge of the enable signal input terminal WE._NAccording to the data input terminal D_IN0Are input to the data bus input terminal DBUS, respectively.₀, / DBUS₀To the data input terminal D_IN1Are input to the data bus input terminal DBUS, respectively.₁, / DBUS₁Is output to
[0048]
FIG. 6 is a timing chart when data is output from the input / output buffer 70 described above.
As shown in FIG. 6, when the chip enable signal / CE is set to the active state (low level), the column predecoder enable signal YDE is set to high level. When a low level signal is input to the input terminal φ of the bit width control signal BWC, the column line CL is synchronized with the column predecoder enable signal YDE._2NIs also set to the high level, and the column line CL_{2N +1} Is held at the low level, and the column line CL_2NData bus BUS in synchronization with the potential change of₀ Is the data output terminal D_OUT0To the data output terminal D_OUT1Is kept in its original state.
[0049]
On the other hand, the input terminal φ of the bit width control signal BWC isYesWhen a level signal is input, the column line CL is synchronized with the column predecoder enable signal YDE._2N, CL_{2N +1} Are both set to the high level. Then, in synchronization with the potential change of these column lines, the data output terminal D_OUT0, D_OUT1Data bus BUS₀ , BUS₁ Is output. That is, the width of the output data changes according to the bit width control signal BWC.
That is, the bit width control signal BWC isLowWhen set to the level, the output data becomes 1 bit and the output data_OUT0Is output to The bit width control signal BWC isYesWhen set to the level, the output data becomes 2 bits and the output data_OUT0, D_OUT1Respectively.
[0050]
As described above, according to the present embodiment, the semiconductor memory device is provided with the input terminal φ of the bit width control signal BWC, and the signal input to the input terminal φ is supplied to the column address buffer 40 and the input / output buffer 70, respectively. When a low-level signal is input to the input terminal φ, the number of bits of the input / output terminal of the semiconductor memory device is increased by one bit from the normal, and the width of data input / output is controlled by the bit width control signal BWC Therefore, the data input / output bit width can be easily changed according to the level of the control signal input to the external input pin, enabling multi-bit simultaneous testing regardless of the application, reducing test time and reducing the number of test pattern development steps. Can be shortened.
[0051]
By incorporating the semiconductor memory device of the present invention into the ASIC memory, the test time and test pattern development man-hour for the ASIC memory can be reduced.
[0052]
【The invention's effect】
As described above, according to the semiconductor memory device of the present invention, a multi-bit simultaneous test can be performed regardless of the application, and there is an advantage that the test time and the number of test pattern development steps can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram showing one embodiment of a semiconductor memory device according to the present invention.
FIG. 2 is a circuit diagram showing a configuration of a column address buffer.
FIG. 3 is a circuit diagram showing a configuration of a column predecoder.
FIG. 4 is a circuit diagram showing a configuration of a memory array and a column selector.
FIG. 5 is a circuit diagram showing a configuration of an input / output buffer.
FIG. 6 is a timing chart of data output in the input / output buffer.
FIG. 7 is a block diagram showing a configuration of a conventional semiconductor memory device.
[Explanation of symbols]
10 row address buffer, 20 row predecoder, 30 row decoder, 40 column address buffer, 50 column predecoder, 60 column selector, 70 input / output buffer, 100 memory array, D_IN, D_IN0, D_IN1... Data input terminal, D_OUT, D_OUT0, D_OUT1... Data output terminal, Y₀, Y₁, ..., Y_N-1, Y_N... column address input terminal, φ ... bit width control signal input terminal, AC₀, AC₁, ..., AC_2N, AC_{2N + 1}... AND circuits, 201, 202, ..., 207 AND circuits, 208, 209 OR circuits, 210, 211, ..., 215 ... inverters, 216, 217, 218, 219 ... output buffers, WL₀, WL₁, ..., WL_N... word line, BL₀, / BL₀, BL₁, / BL₁, ..., BL_{2N + 1}, / BL_{2N + 1}... bit line, CL₀, CL₁, ..., CL_2N, CL_{2N + 1}… Column line, MC₀₀, MC₀₁, ..., MC_{2N + 1, N}... Memory cell, SW_0A, SW_0B, SW_1A, SW_1B, ..., SW_{2N + 1A}, SW_{2N + 1B}... Switching circuit, BUS₀, / BUS₀, BUS₁, / BUS₁... Data bus, DBUS₀, / DBUS₀, DBUS₁, / DBUS₁… Data bus input terminal

Claims (2)

A memory array in which a plurality of memory cells are arranged, and selecting a memory cell addressed by a selected word line and a selected bit line set to an active state according to a row address and a column address; A semiconductor memory device for writing or reading data to or from the memory array via
An address buffer circuit having a plurality of address buffer circuits for outputting the inputted plurality of column address data as an in-phase signal and an inverted signal, respectively, and receiving the lowest one of the plurality of address buffer circuits; When the bit width control signal is inputted at the first level, two signals, ie, an in-phase signal and an inverted signal of the inputted least significant column address data, are outputted, and the bit width control signal is outputted at the second level. A column address buffer that outputs two signals of a predetermined same level regardless of the input level of the lowest column address data when
A column predecoder that sets a predetermined column line among a plurality of column lines to an active state based on a plurality of signals output from the plurality of address buffer circuits of the column address buffer circuit;
A column selector having a plurality of switch circuits each connected to a different one of the column lines, and making the bit line and the data bus conductive when the column line is in an active state;
The input / output circuit is
Upon receiving the bit width control signal and the two output signals of the lowermost address buffer circuit of the column address buffer, when the bit width control signal is at the first level, the read data of one data bus is output. An output buffer for outputting read data of two data buses when the bit width control signal is at a second level;
Receiving the bit width control signal and the two output signals of the lowermost address buffer circuit of the column address buffer, and when the bit width control signal is at the first level, writes the input data of two data input terminals. An input buffer that outputs data to two data buses as data, and outputs input data of one data input terminal to one data bus as write data when the bit width control signal is at the second level. /> Semiconductor storage device. 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is incorporated in an ASIC memory.

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