KR100454251B1 - Semiconductor memory device for reducing testing time - Google Patents

Abstract

SUMMARY OF THE INVENTION The present invention provides a semiconductor memory device that maintains repair efficiency and reduces test time in a cell test of a memory device and is not limited by cell data patterns for testing. An apparatus for testing a memory including a unit block, the apparatus comprising: an address unit configured to receive a plurality of address signals in a normal mode and to enable one word line in the block; And a test circuit for enabling two or more non-contiguous word lines in the block by the plurality of address signals in a test mode.

Description

Semiconductor memory device with reduced memory test time {SEMICONDUCTOR MEMORY DEVICE FOR REDUCING TESTING TIME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to testing techniques for semiconductor memory devices, and more particularly, to semiconductor memory devices that can test memory cells more efficiently during testing for bad screens.

A test for bad screening is a test in which a cell in memory is tested with a specific cell data pattern at the wafer level, causing the failing cell to fail so that the failed memory is precluded, thus yielding the yield in subsequent processes. In addition to increasing the cost, the test and assembly costs can be reduced.

1 is a block diagram of a conventional memory device.

Referring to FIG. 1, a memory device is divided into an upper block 110 and a lower block 120 in one bank 100, and 17 bit line sense amplifiers 111, 113, 121, 123, 124, 126, and the like are located. In the meantime, 16 cell blocks (112, 114, 122, 125, etc.) are located at the top and eight at the bottom. Typically, 512 word lines are placed in one cell block (for example, block 0). Thus, 8K (8 * 1024) word lines are placed in one bank 100.

On the other hand, when testing a manufactured memory device, word lines are sequentially enabled from block 0 112 of the bank 100 to store data "0" or "1" in the unit cell to store the data in each unit cell. You will be tested for abnormalities. At this time, the total test time is consumed by the time corresponding to the product of 8K times in one operation of the word line, and the current consumption in the test consumes the current corresponding to the product of 8K times in the current consumption of one word line.

Therefore, in order to further reduce current consumption and shorten the test time, the block addresses of the upper block unit 110 and the lower block unit 120 are shared (for example, block 0 and block 8), and the word lines in the block in which the addresses are shared. We use a method of cell testing by enabling each of them, which is shown in FIG.

Referring to the cell test method of the memory device illustrated in FIG. 2, the block addresses of the upper block 210 and the lower block 220 constituting one bank 200 are shared (for example, block 0 and block 8). At the same time, the word line in the block with the shared address is enabled and the data is stored in the cell. For example, word lines 205 and word lines 217 are simultaneously enabled by sharing the addresses of block 0 212 and block 8 222, and the same data pattern is stored and tested through each word line. In this test, one bank 200 can be tested, which can reduce the time required to operate 8K word lines to 4K times.

However, if the word line 217 is repaired and repaired as the repair word line 206, the normal word line 205 and the repair word line 206 coexist at block 0 212, and the two simultaneously You will not be able to run tests that enable the word line.

Therefore, in order to reduce the test time by the above-described method, when performing the repair process, the word line in the upper block portion 210 is repaired in the upper block portion, and the word line in the lower block portion 220 is lowered in the corresponding lower portion. Repairing must be performed in the block unit 220 so that the normal word line and the repair word line can be simultaneously operated in the same block. In this case, however, the repair process for repairs is limited to cut test time in half, resulting in less than half the repair efficiency.

In addition, the bit line sense amplifier operates at the upper block 210 and the lower block 220 at the time of the test, and additionally consumes twice the current.

Therefore, in order to shorten the test time while maintaining repair efficiency, a method of enabling two word lines having consecutive addresses at the same time and storing data in a cell is performed. 3 is shown.

As shown in Fig. 3, a test for a bad screen is performed while simultaneously enabling two word lines having consecutive addresses (for example, 305 and 306), thereby improving the repair efficiency of one bank. You can do it 4K while keeping it as. At this time, an operation of enabling two word lines at the same time is called a multi-word line operation.

4 is a diagram illustrating a partial configuration of a cell data pattern used in the test method of FIG. 3 and a memory cell to which the same is applied.

Referring to FIG. 4, in order to enable two word lines sequentially, the word lines W / L0 and W / L1 are enabled in the first control signal mulit0 to test data through the bit lines BL0 and / BL0. To determine whether the cell is abnormal or not, enable word lines W / L2 and W / L3 in the second control signal mul1, and store test data in the corresponding cell through bit lines BL1 and / BL1. Determine if there is an abnormality in In this case, a cell data pattern to be used is shown in '410', and a part of test data is stored in a cell according to the data pattern in '400'. Meanwhile, in a conventional memory structure, two consecutive word lines share a contact connecting a bit line and a cell to minimize an area.

5 illustrates a circuit for generating a test enable signal for use in the test method of FIGS. 3 to 4.

Referring to FIG. 5, word lines are enabled one by one in the normal operation by receiving the address signals A <0>, A <1 and the control signal CTRL, and in a multi-word line operation, that is, a bad screen. It is a logic circuit that operates two word lines sequentially during the test. During normal operation, the control signal CTRL is kept at a low level and one of the signals WL0 to WL3 is enabled according to the state of the address signals A <0> and A <1>.

In the multi-word line operation, when the control signal CTRL maintains a high level, when A <1> is a low level, the NAND gates ND2 and ND3 operate to enable W / L0 and W / L1 simultaneously. When A <1> is at a high level, the NAND gates ND4 and ND5 operate to enable W / L2 and W / L3 simultaneously.

However, the method of testing a memory cell using the above-described method also has the following problems.

When performing the bad screen test, a test data pattern different in up, down, left, and right sides and a test pattern (410 in FIG. 4) different from the diagonal direction are required for the reference cell (for example, 411 in FIG. 4).

However, in a structure in which a contact connecting a bit line and a cell is configured to share two consecutive word lines, a test for enabling two word lines at a time is restricted by a cell data pattern.

That is, there is no problem in the test using the test pattern (410 of FIG. 4) having a different diagonal direction, but the multiword line operation enables two word lines at the same time when testing with the test data patterns having different top, bottom, left and right sides. Cannot be performed, and only a test for enabling one word line again can be performed. Therefore, when testing with test data patterns with different top, bottom, left and right, it takes 8K test time to test one bank.

Therefore, when testing for a bad screen, there is a need for a test apparatus capable of reducing test time by enabling multiword lines without being restricted by cell data patterns.

An object of the present invention is to provide a semiconductor memory device that maintains repair efficiency and reduces test time in a cell test of a memory device and is not limited by cell data patterns for testing.

1 is a block diagram of a conventional memory element.

Figure 2 is a block diagram showing a cell test method of a memory device according to the prior art, the repair efficiency is reduced.

3 is a cell test block diagram of a memory device according to the prior art which can use only a limited test data pattern.

FIG. 4 is a diagram illustrating a cell data pattern used in the test method of FIG. 3 and a part of a memory cell to which the same is applied. FIG.

5 is an output circuit of a test enable signal used in the test method of FIG.

Figure 6 is a cell test block diagram of a memory device according to a preferred embodiment of the present invention.

FIG. 7 is a partial configuration diagram of a cell data pattern used in the test method of FIG. 6 and a memory cell to which the data is applied.

8 is a circuit for generating a test enable signal for use in the test method of FIG.

According to an aspect of the present invention, there is provided a semiconductor memory device including a unit cell block including a plurality of word lines, the unit cell block including a plurality of word lines; An address circuit unit for receiving a plurality of address signals in a normal mode and enabling one word line in the unit cell block; And a test circuit unit outputting a plurality of test signals for enabling at least two non-contiguous word lines in the unit cell block by the plurality of address signals in a test mode, wherein the address circuit unit includes a test mode switch signal. An address decoder receiving the plurality of address signals and enabling one of the plurality of outputs when the test mode switch signal is disabled; And a plurality of first NAND gates each having the plurality of outputs as one input and one of the plurality of test signals output from the test circuit unit as the other input.

According to the present invention, in a test in which a test data pattern is stored in a cell of a memory device to check for defects, the word lines adjacent to each other between word lines and bit lines in order to minimize area while maintaining test time and repair efficiency. To solve the limitations of shared test data patterns, instead of enabling two consecutive word lines sequentially during a test, the non-contact word lines, that is, non-neighbor word lines, are simultaneously enabled. A semiconductor memory device for performing a test.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. do.

6 is a cell test block diagram of a memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 6, the cell test of the memory device according to the present exemplary embodiment performs a cell test by simultaneously enabling word lines (eg, 505 and 506) using a combination of a control signal and an external address. In this case, the word lines 505 and 506 are non-neighboring word lines. Since the test is performed by enabling two word lines at a time, the test time of one bank (for example, 500) is 4K word line enable times. There is no reduction in repair efficiency. In addition, since the word line is enabled only within one unit block, only 501 and 503 corresponding to block 0 (502) are driven, thereby minimizing current consumption.

FIG. 7 is a block diagram illustrating a cell data pattern used in the test method of FIG. 6 and a memory cell employing the same. FIG. 8 illustrates an embodiment of a semiconductor memory device including a test circuit used in the test method of FIG. It is a figure which shows.

Referring to FIG. 8, the semiconductor memory device according to the present exemplary embodiment receives an address signal A <0>, A <1> in the normal mode, and selects and enables one word line in the unit block. The circuit unit 710 and the test circuit unit 730 enable two or more non-contiguous word lines in the unit block by the address signal A <1> in the test mode.

In addition, the address circuit unit 710 receives one of a plurality of outputs a, b, c, and d when the test mode switch signal CTRL is low. The NAND gate which selects and enables the address decoder 711 and the plurality of outputs a, b, c and d as one input and the output multi0 or multi1 of the test circuit 720 as the other input, respectively. ND5, ND6, ND7, ND8 and buffers (b1, b2, b3, b4) for buffering the output of the NAND gates (ND5, ND6, ND7, ND8) and outputting the word line enable signals wl0 to wl3. Equipped.

The test circuit 730 buffers the output of the NAND gate ND9 and the NAND gate ND9 that receive the test mode switching signal CTRL on one side and the address signal A <1> on the other side. The buffer B5 outputs to the other input of the gates ND6 and ND7, the test mode switching signal CTRL is input to one side, and the inverted address signal / A <1> is input to the other side. The NAND gate ND10 and a buffer b6 buffering an output of the NAND gate ND10 and outputting the multiplied outputs to the other inputs of the NAND gates ND6 and ND7.

6 to 8 will be described in detail the operation according to the present invention.

First, during normal operation, that is, when the memory is normally operated, the test mode switching signal CTRL is inputted low, and at this time, the address signals A <0> and A <1 are inputted and the word lines wl0 and wl3 are received. ) Is enabled.

On the other hand, when the test mode switching signal CTRL is input high in the test mode, the outputs of the NAND gates ND1 to ND4 are fixed high, and when the address signal A <1> is low level, the NAND gate ( When the ND9 is operated to output the first test signal mulit0 low, the word lines wl0 and wl3 are enabled, and when the address signal A <1> is at a high level, the NAND gate ND10 operates to generate a word. Lines wl1 and wl2 are enabled. Therefore, in the test mode, two non-neighboring word lines can be enabled at the same time by using a part of the address signal A <1>.

Referring to FIG. 7, the word lines wl0 and wl3 are enabled by the first test signal muilt0 in one block, and the test data patterns are stored in corresponding cells through the bit lines BL0 and / BL0. By checking the abnormality of the cell, the word lines wl1 and wl2 are enabled by the second test signal muilt1, and the test data patterns are stored in the corresponding cells through the bit lines BL1 and / BL1. Check for abnormalities.

In this case, the test data pattern may be implemented in the form of 610 and 620. When a test is performed using the test data pattern '610', a test having a diagonally different data value may be performed (for example, 611). When testing using '620', it is possible to perform a test having different data values before, after, and after. '600' of FIG. 7 illustrates a portion of a cell when a test is performed using the cell data pattern of 620.

Therefore, as described above, the test is performed by enabling two word lines at the same time during the test, and the test time can be shortened. There are no test data pattern constraints such as different implementations, so you can test more efficiently.

In addition, when the test is performed by enabling more than two word lines at the same time in the same block according to the remedy unit of the word lines, the test can be performed more efficiently.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

According to the present invention, the test time can be reduced, thereby reducing the production cost, and in particular, the product can be developed more effectively during initial product development.

Claims (3)

delete In testing a semiconductor memory device including a unit cell block including a plurality of word lines, A unit cell block having a plurality of word lines; An address circuit unit for receiving a plurality of address signals in a normal mode and enabling one word line in the unit cell block; And A test circuit unit configured to output a plurality of test signals for enabling at least two non-contiguous word lines in the unit cell block by the plurality of address signals in a test mode, The address circuit unit, An address decoder that receives a test mode switch signal and receives the plurality of address signals when the test mode switch signal is disabled to enable one of a plurality of outputs; And And a plurality of first NAND gates each having the plurality of outputs as one input and one of the plurality of test signals output from the test circuit unit as the other input. The method of claim 2, The test circuit unit A plurality of second NAND gates for receiving a test mode switching signal on one side and a selected signal among the address signals on the other side and outputting a test signal to be input to two or more NAND gates of the plurality of first NAND gates; A semiconductor memory device, characterized in that.