KR20040006386A - Semiconductor memory device - Google Patents

Abstract

PURPOSE: A semiconductor memory device is provided to increase row redundancy efficiency using row redundancy existing in a bank which can not be repaired because of block fail. CONSTITUTION: According to the semiconductor memory device including a plurality of banks(11,12,13,14), each bank includes a plurality of redundancy word lines(RWLk0-RWLk3) to repair. A peripheral circuit area corresponding to each bank includes a redundancy control unit comprising a row fuse(23,26) to perform a repair operation by selecting a redundancy word line, and it includes a multiplexer(25,28,29) selecting a redundancy word line enable signal being outputted from a redundancy control unit(24,27) to use a redundancy word line of a bank which dose not perform a repair operation according to a bonding option signal.

Description

Semiconductor memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device that increases the efficiency of row redundancy by using an unused row fuse of a failed block.

1 is a block diagram illustrating a semiconductor memory device according to the prior art. Here, the case where it consists of four banks and each bank consists of four blocks is demonstrated to an example.

The semiconductor memory device is composed of four banks 1 to 4, and each bank includes four blocks 5 to 8.

Each bank also includes two row redundancy, redundancy word lines RWL0 and RWL1.

If less than two word line failures occur in one block, the redundancy word lines RWL0 and RWL1 are replaced by the defective word lines. In addition, the same operation is performed in three different blocks in the same bank. That is, only two word lines can be repaired in one bank.

In addition, there is a redundancy control unit 10 including a row fuse 9 for performing a repair operation in the peripheral circuit region, and an address AXi <0: m> for comparing row addresses and an address BAi for bank coding are provided. It is inputted to output redundancy word line enable signals RWLENi0 and RWLENi1 for driving the redundancy word lines RWL0 and RWL1.

For example, if a block fail or the like exists in two banks 3 and 4 and the rescue is impossible, only the remaining banks 1 and 2 are commercialized.

In this case, unused redundancy exists in the two non-recoverable banks 3 and 4, but since the remaining commercial banks 1 and 2 have only two redundancies, two or more word line failures can be saved. There is no problem.

An object of the present invention for solving the above problems is to increase the low redundancy efficiency by using the redundancy existing in the bank that can not be repaired due to block failure.

1 is a block diagram illustrating a semiconductor memory device according to the prior art.

2 is a block diagram illustrating a semiconductor memory device according to the present invention.

3 is a detailed circuit diagram of the multiplexer 29 shown in FIG.

4 shows a detailed circuit of the multiplexer 25 of the bank 11 shown in FIG.

5 shows a detailed circuit of the multiplexer 28 of the bank 13 shown in FIG.

The semiconductor memory device of the present invention for achieving the above object,

Including a plurality of banks,

Each bank including a plurality of redundancy word lines for repair,

In the peripheral circuit area corresponding to each bank,

Redundancy control means including a row fuse for selecting the redundancy word line and performing a repair operation; And

And a multiplexer for selecting a redundancy word line enable signal output from the redundancy control means to use the redundancy word line of the bank that cannot perform the repair operation according to the bonding option signal.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram illustrating a semiconductor memory device according to the present invention. Here, the case where it consists of four banks and each bank consists of four blocks is demonstrated to an example.

The semiconductor memory device is composed of four banks 11 to 14, and each bank includes four blocks 15 to 18.

Each bank also includes four row redundancy, or redundancy word lines. That is, two redundancy word lines are used to replace a word line failure, and the remaining redundancy word lines are caused by a block failure and more than two word line failures occur by using a low fuse of a non-repairable bank. Used to replace.

Although the structures of the bank 11 and the bank 13 are shown in detail here, the other banks 12 and 14 are configured in the same manner. That is, the bank 11 includes four blocks 15 to 18 and four redundancy word lines RWLi0 to RWLi3, and the bank 13 includes four blocks 19 to 22 and four redundancy word lines RWLk0. -Includes RWLk3.

Here, the banks 11 to 14 are formed in two bundles according to the IO (input / output) structure. In the present invention, the banks 11 to 14 should be operated in a bundle of two banks (11, 12) and (13, 14). . This is because various IO structures (for example, X4, X8, X16, etc.) can be satisfied.

The semiconductor memory device may further include a redundancy control unit including a row fuse for selecting a redundancy word line in a peripheral circuit area corresponding to each bank to perform a repair operation, and a redundancy word line output from the redundancy control unit according to a bonding option signal. The apparatus further includes a multiplexer for selecting the enable signal.

That is, the bank 11 includes a redundancy control unit 24 including a row fuse 23 for performing a repair operation by selecting the redundancy word lines RWLi0 and RWLi1 in a corresponding peripheral circuit area, and the bonding option signals BONDij and BONDkl. Accordingly, the multiplexer 25 selects the redundancy word line enable signals RWLENi0 and RWLENi1 output from the redundancy control unit 24.

In addition, the bank 13 includes a redundancy control unit 27 including a row fuse 26 for performing a repair operation by selecting the redundancy word lines RWLk0 and RWLk1 in a corresponding peripheral circuit area, and the bonding option signals BONDij and BONDkl. Accordingly, the multiplexer 28 selects the redundancy word line enable signals RWLENk0 and RWLENk1 output from the redundancy control unit 27.

The semiconductor memory device includes a multiplexer 29 for selectively transferring the bank addresses BAi and BAk to the multiplexers 25 and 28 of each bank according to the bonding option signals BONDij and BONDkl.

Here, the bonding option signal BONDij is a signal generated by the bonding of the banks 11 and 12, and the bonding option signal BONDkl is a signal generated by the bonding of the banks 13 and 14. That is, when a non-repairable defect occurs in the bank 11 or the bank 12 as a result of testing the semiconductor memory device, the bonding option signal BONDij is at a low level, and the other bonding option signal BONDkl is at a high level.

On the contrary, when a non-repairable defect occurs in the bank 13 or the bank 14, the bonding option signal BONDij goes high and the other bonding option signal BONDkl goes low.

3 is a detailed circuit diagram of the multiplexer 29 shown in FIG. Here, the case where the non-repairable defect exists in the bank 13 or the bank 14 is demonstrated as an example.

The multiplexer 29 includes a selection output section 30 for selectively outputting the addresses BAi and BAk of the banks 11 and 13 in accordance with the bonding option signal BONDij, and an address of the banks 11 and 13 in accordance with the bonding option signal BONDkl. Selective output 31 for selectively outputting BAk and BAi, and selective output for selectively outputting addresses AXi <0: m> and AXk <0: m> of banks 11 and 13 in accordance with the bonding option signals BONDij. And a selection output section 33 for selectively outputting addresses AXk <0: m> and AXi <0: m> of the banks 11 and 13 in accordance with the bonding option signal BONDkl.

Here, the selection output unit 30 includes an inverter INV1 for inverting the bonding option signal BONDij, a NAND gate ND1 for selectively outputting the address BAi of the bank 11 according to the bonding option signal BONDij, and an inverted bonding option signal / BONDij. NAND gate ND2 for selectively outputting the address BAk of the bank 13, and NAND gate ND3 for negative logic multiplication of the output signals of the NAND gates ND1 and ND2.

The selection output section 31 includes an inverter INV2 for inverting the bonding option signal BONDkl, a NAND gate ND4 for selectively outputting the address BAk of the bank 13 in accordance with the bonding option signal BONDkl, and the inverted bonding option signal / BONDkl. And a NAND gate ND5 for selectively outputting the address BAi of the bank 11, and a NAND gate ND6 for negative logic multiplication of the output signals of the NAND gates ND4 and ND5.

The selection output section 32 includes an inverter INV3 for inverting the bonding option signal BONDij, a NAND gate ND7 for selectively outputting the address AXi <0: m> of the bank 11 according to the bonding option signal BONDij, and an inverted bonding option. And a NAND gate ND8 for selectively outputting the address AXk <0: m> of the bank 13 in accordance with the signal / BONDij, and a NAND gate ND9 for negative logic multiplication of the output signals of the NAND gates ND7 and ND8.

The selection output section 33 includes an inverter INV4 for inverting the bonding option signal BONDkl, a NAND gate ND10 for selectively outputting the address AXk <0: m> of the bank 13 in accordance with the bonding option signal BONDkl, and an inverted bonding option. And a NAND gate ND11 for selectively outputting the address AXi <0: m> of the bank 11 in accordance with the signal / BONDkl, and a NAND gate ND12 for negative logic multiplication of the output signals of the NAND gates ND10 and ND11.

In this case, since there is a defect that cannot be repaired in the bank 13 or the bank 14, the bonding option signal BONDij is at a high level, and the other bonding option signal BONDkl is at a low level.

Therefore, in the selection output section 30, the address BAi of the bank 11 is output as it is, regardless of the address BAk of the bank 13, and in the selection output section 31, the bank (regardless of the address BAk of the bank 13) is output. The address BAi of 11) is output as it is.

Similarly, in the selective output unit 32, the address AXi <0: m> of the bank 11 is output as it is, regardless of the address AXk <0: m> of the bank 13, and the selective output unit 33 outputs the bank. Regardless of the address AXk <0: m> of (13), the address AXi <0: m> of the bank 11 is output as it is.

In other words, the coding information of the bank 11 enters the redundancy control unit 27 of the bank 13 to operate like the redundancy control unit of the bank 11.

4 shows a detailed circuit of the multiplexer 25 of the bank 11 shown in FIG.

The multiplexer 25 is controlled by the inverter INV5 for inverting the bonding option signal BONDij, the transmission gate TG1 and the redundancy word line in which are controlled by the bonding option signal BONDij and the inverted signal / BONDij to transmit the redundancy word line enable signal RWLENi0. A selection transmitter 34 including a transfer gate TG2 for transmitting the enable signal RWLENi0 as the redundancy word line enable signal RWLENk2 of the bank 13, an inverter INV6 for inverting the bonding option signal BONDij, a bonding option signal BONDij and an inversion The transmission gate TG3 for controlling the redundant word line enable signal RWLENi1 and the redundancy word line enable signal RWLENi1 controlled by the signal / BONDij as the redundancy word line enable signal RWLENk3 of the bank 13. It includes a selection transmission unit 35 including.

Therefore, when all banks can be repaired, the bonding option signals BONDij and BONDkl are all enabled at a high level, and the redundancy word line enable signals RWLENi0 and RWLENi1 are output as they are to drive the redundancy word lines RWLi0 and RWLi1.

However, when the bank 11 or the bank 12 becomes impossible to repair due to a block failure or the like, the bonding option signals BONDij become low level and the redundancy word line enable signals RWLENi0 and RWLENi1 enable the redundancy word line enable of the bank 13. Outputted as signals RWLENk2 and RWLENk3, bank 13 reserves two additional redundancy word lines.

FIG. 5 shows a detailed circuit of the multiplexer 28 of the bank 13 shown in FIG.

The multiplexer 28 includes inverter INV7 for inverting the bonding option signal BONDkl, and transmission gate TG5 and redundancy word line in which are controlled by the bonding option signal BONDkl and the inverted signal / BONDkl to transmit the redundancy word line enable signal RWLENk0 as it is. A selection transmitter 36 including a transfer gate TG6 for transmitting the enable signal RWLENk0 as the redundancy word line enable signal RWLENi2 of the bank 11, an inverter INV8 for inverting the bonding option signal BONDkl, a bonding option signal BONDkl, and inversion The transmission gate TG7, which is controlled by the signal / BONDkl, which transmits the redundancy word line enable signal RWLENk1, and the transmission gate TG8, which transmits the redundancy word line enable signal RWLENk1 as the redundancy word line enable signal RWLENi3 of the bank 11. It includes a selection transmission unit 37 including.

Therefore, when all banks are repairable, when the bonding option signals BONDij and BONDkl are all enabled at the high level, the redundancy word line enable signals RWLENk0 and RWLENk1 are output as they are to drive the redundancy word lines RWLk0 and RWLk1.

However, when the bank 13 or the bank 14 cannot be repaired due to block failure or the like, the bonding option signals BONDkl become low level, and the redundancy word line enable signals RWLENk0 and RWLENk1 become redundant word line enable of the bank 13. Outputted as signals RWLENi2 and RWLENi3, bank 11 reserves two additional redundancy word lines.

As described above, when there is a bank that cannot be repaired due to a block failure or the like, the redundancy word line of the bank can be additionally used.

As a result, three or four word line failures can be generated to commercialize a chip that cannot be used because it cannot be repaired, thereby increasing the yield on the wafer.

As described above, in the semiconductor memory device according to the present invention, since redundancy word lines of unused banks due to block failure or the like can be controlled and controlled by bonding options, the yield in manufacturing a semiconductor memory device is improved. It can be effected.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (4)

In a semiconductor memory device including a plurality of banks, Each bank including a plurality of redundancy word lines for repair, In the peripheral circuit area corresponding to each bank, Redundancy control means including a row fuse for selecting a redundancy word line to perform a repair operation; And a multiplexer for selecting a redundancy word line enable signal output from the redundancy control means in order to use the redundancy word line of the bank that cannot perform the repair operation according to the bonding option signal. The method of claim 1, And an address multiplexer for selectively transferring a corresponding bank address to the multiplexer of each bank according to the bonding option. The method of claim 2, The address multiplexer, A plurality of first selection output means for selectively outputting a bank address in accordance with the bonding option; And And a plurality of second selection output means for selectively outputting a row address of a bank according to the bonding option. The method of claim 1, The multiplexer, First transmission means for outputting a redundancy word line enable signal of the corresponding bank as it is according to the bonding option; And And second transmission means for outputting a redundancy word line enable signal of the corresponding bank as a redundancy word line enable signal of a bank that cannot perform the repair operation according to the bonding option. .