JP2000268561A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor storage device which is reduced in circuit scale, wiring scale, and occupation area for column address transmission to respective banks operating independently of one another and is reduced in chip area. SOLUTION: A main column decoder 13 which has a larger circuit scale than local column decoders 15-x provides a common signal line for the respective banks. A main column selection line MCSL is unidirectional and extends in parallel to the output line LCSL of the local column decoders 15-x. A column address which is inputted in common to all the banks is inputted to only the main column decoder 13, a column selection line inputted to all the banks in common, i.e. MCSL is employed, and the local column decoders 15-x which are simplified in circuit constitution are arranged for the respective banks, so that the banks can be controlled independently of one other. Consequently, the circuit scale is reducible.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a structure in which a memory chip is divided into a plurality of banks, and capable of independently controlling the operation of each bank.

[0002]

2. Description of the Related Art It is well known that a memory is internally divided into a plurality of banks and operated independently for the purpose of increasing the operation speed of a memory and improving the data transfer capability. For example, in a synchronous DRAM, interleave control can be performed for each bank, and apparently the precharge time is hidden, thereby increasing the bus transfer efficiency. The larger the number of data to be output in one cycle, the more banks are required.

When operations between banks are independent, bit lines may be sensed in a certain bank, and a local line may be connected to a bit line by activating a column selection line in another bank. Column select lines cannot be shared between different banks.

[0004]

For the above reasons, a column decoder must be provided for each bank so that the column selection line can be controlled independently for each bank.
In this case, all addresses need to be input to the column decoders arranged in each bank, and there is a problem that the circuit / wiring scale increases and the chip area increases.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to solve the problem in a plurality of memory cell array banks operating independently, a circuit scale, a wiring scale, and an occupancy for transmitting an address to each of the banks. An object of the present invention is to provide a semiconductor memory device whose area can be reduced and which contributes to reduction in the layout of a memory cell array and whose chip area can be significantly reduced.

[0006]

SUMMARY OF THE INVENTION A semiconductor memory device according to the present invention has a plurality of banks divided for independently operating a memory cell array, and a plurality of bit lines for each block provided in each of the banks. , A first data decoding circuit for decoding an address signal, and at least an address signal which has passed through the first decoding circuit, and a plurality of output lines are provided. A second decoding circuit provided for each of the plurality of banks, each functioning as a signal line for controlling connection between each of the plurality of bit lines and the common data line.

According to the present invention, with respect to a plurality of banks which operate independently, one of a plurality of bit lines is selected by an output line of a second decode circuit and connected to a common data line.

[0008]

FIG. 1 is a circuit diagram showing a configuration of a main part of a semiconductor memory device according to a first embodiment of the present invention.
The memory cell array is divided into a plurality of banks to operate independently. Here, four banks BNKx (x = 0 to 3) are shown. Bank BNK
x has a general configuration including a memory cell array and a sense amplifier.
And that the bit line connected to it is included,
Other general components are omitted.

The column address is shared and each bank BN
Two types of predecoders are provided: a column predecoder 11 for generating a signal commonly used for Kx, and a column predecoder 12 which is not shared and is used as an input for each bank BNKx.

The column predecoder 11 decodes the upper 3 bits of the 5-bit column address and generates signals Y234P <0> to <7> to the main column decoder 13. The main column decoder 13 generates signals MCSL <0> to <7> commonly input to each bank BNKx.

The column predecoder 12 decodes the lower 2 bits of the 5-bit column address and generates signals Y01P <0> to <3> to the local column address decoder 14-x (x = 0 to 3). . The local column address decoder 14-x outputs a column bank selection signal CB
The signals LCAx <0> to <3> corresponding to each bank are created by SL <x> and the signals Y01P <0> to <3> (where x = 0 to 3).

The local column decoder 15-x (x =
0-3) are provided for each bank BNKx, and the corresponding local column address decoders 14-x
LCAx <0>-<3> (x = 0-3) from the main column decoder 1 common to each bank
Signals MCSL <0> to <7> from 3 are input.

The local column decoder 15-x includes:
A plurality of output lines LCSL (local column selection lines) for controlling a column address in the bank BNKx are provided. Each of the plurality of bit lines BL connected to each of the memory cells MC in the bank BNKx is connected to the common data line N2 via the switching element T1. The signal line for controlling the conduction of the switching element T1 is the output line LCSL of the local column decoder 15-x. This controls the connection between each of the plurality of bit lines BL in the bank BNKx and the common data line N2.

The common data line N2 of the bit lines in the bank BNKx is connected to a switching element (transistor) T2.
Is connected to a data output line (RD line) N3 common to the banks.

Although not shown, the bit lines BL are shown one by one, omitting a bit line pair. Therefore, each switching element T1 also has one pair configuration,
The common data line N2 also omits one pair. Therefore,
The RD line N3 is also shown with one pair omitted.

The memory cells MC in the bank BNKx are
Only the configuration in which the memory cell MC is connected to the bit line BL is shown, and the circuit of the bit line control system such as the sense amplifier is omitted. Also, the row decode system is omitted.

For example, when a plurality of memory cell array blocks in which the inside of the bank BNKx is divided by sense amplifiers are formed, a common data line N2 (pair) of a bit line pair is provided for each memory cell array block. Thereby, bank B
RD lines (pair) for NKx memory cell array blocks
Is provided.

According to the configuration of the present invention, the number of RD lines does not change regardless of the number of banks, since the RD lines are shared by the banks BNKx. What is necessary is just to arrange as many as the number of output bits.

Providing a local column decoder 15-x individually for each bank BNKx is advantageous for high-speed operation. For example, RDRAM (Rambus DRAM)
In order to operate at high speed, interleave is used as a method of accessing a bank. This is a method in which a plurality of banks are selected and data of only one of the banks is extracted. Therefore, data of a plurality of banks can be output to the corresponding RD lines at the same time. Here, since the RD line N3 is shared by each bank, each bank BNK is used to control the output for each bank.
x is provided with an independent local column decoder 15-x.

The main column decoder 13, which has a larger circuit size than the local column decoder 15-x,
The units of the NKx and the local column decoder 15-x are arranged on one side where they are arranged. The main column decoder 13
Although a common signal line is provided for each bank, the above arrangement causes its main column select line MCSL to extend in a single direction and in parallel with the output line LCSL of the local column decoder 15-x.

In the layout form of the main column decoder 13, when a plurality of memory cell array blocks are divided by the sense amplifier in the bank BNKx, each memory cell array block can have a shared sense amplifier configuration.

The specific configuration of the decoding circuit will be described below. FIG. 2 is a circuit diagram showing a configuration of the column predecoder 12. This circuit receives column addresses CA <0> and CA <1> and generates a basic signal Y01P to the local column address decoder 14-x. This circuit configuration is prepared in the same number as the number of the local column address decoders 14-x (here, since x = 0 to 3, four are provided).

The signals CADDi and CADDDj are input to two input terminals of the NAND gate NAND21. The signals TMBIDCC and TMBIMODE are input to two input terminals of the NAND gate NAND22, respectively. The output signals of the NAND gates NAND21 and NAND22 are input to two input terminals of the NAND gate NAND23. The output of NAND gate NAND23 is supplied to output signal Y via inverters IV21 and IV22.
01P.

FIG. 3 shows the input signals CADDi and CADDDj and the output signal Y0 in each of the four circuits of FIG.
This is a truth value notation indicating the relationship of 1P. Signal TMBIDC
Since C and TMBIMODE are limited to use in the test mode, they are "L" (low level) in normal operation. Therefore, the output Y01P depends on the column addresses CA <0> and CA <1>, and follows the truth value notation in the figure.

That is, the signals CADDi, CADDDj
Is the column address CA <0> and its complementary signal bCA <
0>, the column address CA <1> and its complementary signal bCA
Four types of combinations are made using <1>, and the output signal Y
01P each local column address decoder 14
−x for each signal Y01P <0> to <3
> Is generated.

FIG. 4 is a circuit diagram showing a configuration of the column predecoder 11. This circuit has a column address CA <
2> -CA <4> and generates a basic signal Y234P to the main column decoder 13. This circuit configuration is prepared for the number of signals supplied to the main column decoder 13 (here, since Y234P <0> to <7>, 8
Pieces).

The NAND gate NAND41 has three input terminals, signals CADDi, CADDDj and CAD, respectively.
Dk is input. Inverter IV41 receives signal TMB
IDCC is inverted and output. NAND gate NAND42
The output signals of the NAND gate NAND41 and the inverter IV41 are respectively input to two input terminals. N
The output of AND gate NAND42 is connected to inverter IV4.
2, and an output signal Y234P via IV43.

FIG. 5 is a truth notation showing the relationship between the input signals CADDi, CADDj, CADDk and the output signal Y234P in each of the eight circuits of FIG. Since the signal TMBIDCC is limited to use in the test mode, it is “L” (low level) in normal operation. Therefore, the output Y234P is at the column address CA
Depends on <2> to CA <4>, and follows the truth notation in the figure.

That is, the signals CADDi, CADDDj,
CADDk uses the column address CA <2> and its complementary signal bCA <2>, the column address CA <3> and its complementary signal bCA <3>, and the column address CA <4> and its complementary signal bCA <4>. Eight types of combinations are created, and respective signals Y234P <0> to <7> used in the main column decoder 13 are generated as output signals Y234P.

FIG. 6 is a circuit diagram showing a configuration of the local column address decoder 14-x. This circuit configuration is prepared four by one for each local column address decoder. Therefore, a total of 16 local column address decoders 14-0 to 14-3 are prepared.

The NAND gate NAND61 has three input terminals: a synchronization signal FCSLE, a CBSL signal for controlling column bank selection, and Y0 from the column predecoder 12.
A 1P signal is provided. The output of the NAND 61 outputs a signal LCA corresponding to each bank via the inverters IV 61, 62 and 63 in series.

That is, the local column address decoder 14-0 generates the FCSLE signal and the CBSL <0> signal in common from the four circuit configurations shown in FIG. 6 in which Y01P <0> to Y01P <3> are input. The transmitted four signals LCA0 <0k> to LCA <3> are transmitted to the local column decoder 15-0.

Further, the local column address decoder 14-1 generates the FCSLE signal and the CBSL <1> signal in common from the four circuit configurations shown in FIG. 6 in which Y01P <0> to Y01P <3> are input. The four signals LCA1 <0> to LCA <3>
The signal is transmitted to the column decoder 15-1.

The local column address decoder 14-2 generates the FCSLE signal and the CBSL <2> signal in common from the four circuit configurations shown in FIG. 6 which input Y01P <0> to Y01P <3> in common. The four signals LCA2 <0> to LCA <3>
The signal is transmitted to the column decoder 15-2.

Further, the local column address decoder 14-3 generates the FCSLE signal and the CBSL <3> signal in common from the four circuit configurations shown in FIG. 6 in which Y01P <0> to Y01P <3> are input. The four signals LCA3 <0> to LCA <3>
The signal is transmitted to the column decoder 15-3.

With such a configuration, the LCA signal is driven in synchronization with the FCSLE signal, and functions as a part of the address signal controlled by the local column decoder 15-x for each bank.

FIG. 7 is a circuit diagram showing a configuration of main column decoder 13. Eight circuit configurations are prepared. NA
The ND gate NAND 71 is supplied with a synchronization signal CDRV and a Y234P signal from the column pre-decoder 11 to which the upper three bits of the column address are input at two input terminals. The output of the NAND 71 is the inverter IV 71, 72,
73 in series, an MCSL signal (MC
SL <0> to <7>).

That is, the main column decoder 13 uses the CD
RV signals are made common and Y234P <0> to Y234P <7
> Eight signals MCSL <0> to MCSL <7> respectively generated from the eight circuit configurations of FIG.
Is commonly transmitted to the local column decoder 15-x in synchronization with the CDRV signal.

FIG. 8 shows a local column decoder 15-.
FIG. 3 is a circuit diagram illustrating a configuration of x. Eight circuit configurations (F8) are prepared for each local column decoder. Therefore, the local column decoders 15-0 to 15-1
A total of 32 pieces are prepared for 5-3.

Each of the NAND gates NAND81 to 84 has one input terminal to which the LCAx <0> to <3> from the local column address decoder 14-x is input, and the other input terminal to the main column decoder 13 respectively.
, A common MCSL signal is input.

The output of the NAND 81 is the inverter IV81.
, A signal LCSL <0> for controlling a predetermined local column selection line (LCSL). The output of the NAND 82 becomes a signal LCSL <1> for controlling a predetermined local column selection line (LCSL) via the inverter IV82. The output of the NAND 83 becomes a signal LCSL <2> for controlling a predetermined local column selection line (LCSL) via the inverter IV83. The output of the NAND 84 becomes a signal LCSL <3> for controlling a predetermined local column selection line (LCSL) via the inverter IV84.

The main column selection line (MCSL) from the main column decoder 13 is parallel to the local column selection line (LCSL) as shown in FIG.
It is located between the CSL sequences. Here, LCSL
Are arranged at the center symmetrically separated by two. The advantages of this configuration will be described later.

FIG. 9 shows a local column decoder 15-.
FIG. 3 is a circuit diagram showing an arrangement configuration of x for two banks.
A predetermined number of circuit blocks F8 having the configuration shown in FIG. 8 are provided for each bank. There are actually eight circuit blocks F8 for each bank, and MCSL <0> to MCSL
The signal of <7> is received.

Since the inside of the bank BNKx has a general configuration including a memory cell array and a sense amplifier, the memory cell MC and the bit line BL connected thereto are connected to the sense amplifier S / A.
, And the other general configuration is omitted. As in FIG. 1, each bit line BL is shown one by one, omitting a bit line pair. Therefore, each switching element T1 has one pair, and the common data line N2 has one pair. Therefore, the RD line N3 is also shown with one pair omitted.

MCSL is a signal LCAx <0> for each bank of a local column decoder arranged in each bank.
To determine whether to enable the decoding control of <3>,
That is, the driving of the LCSL for controlling the conduction of the switching element T1 is set to a selected / non-selected state. With this configuration, it is possible to simplify a decoding circuit required to realize an independent operation for each bank.

In the above embodiment, 32 LCSs
The main column decoder 13 is provided with the address treated as a common signal to each bank among the 5-bit column addresses necessary for controlling L as the upper 3 bits, and the MCSL output from this circuit is arranged for each bank. The local column decoders 15-x input the data in common. As a result, the column decoder could be replaced with a simple circuit configuration.

That is, regarding the column address commonly input to all the banks, the main column decoder 13
Only the MCSL is a column select line that is commonly input to all banks. By arranging a local column decoder with a simplified circuit configuration in each bank, each bank can be independently controlled. Can control. Therefore, the circuit scale can be reduced.

Further, according to the above configuration, it is not necessary to input a column address to all the banks, so that it is possible to shorten the wiring of the column address system. Therefore, since the charge / discharge current for the wiring of this system can be reduced,
Contributes to low power consumption.

FIG. 10 is a layout diagram showing a main column decoder and one bank adjacent thereto. The memory cell array in the bank BNK0 forms a plurality of cell array blocks separated by sense amplifiers, and the sense amplifier blocks include sense amplifiers shared between adjacent memory cell array blocks.

In the local column decoder 15-0, one of the circuit blocks F8 of FIG. 8 is typically shown as a block. The MCSL (main column selection line) which is the output line of the main column decoder 13 and the LCSL (local column selection line) which is the output line of the local column decoder 15-0 are configured as metal wiring layers on the memory cell array. Extends in a single direction in parallel. And LC
The MCSL is disposed at the center symmetrically spaced by two SLs.

Representatively, one common data line N2 (LDQ line: local DQ line) arranged for each sense amplifier block is shown. A data output line (RD line) N3 common to each bank is also typically shown. Although the switching elements T1 and T2 for controlling the connection of each data line are omitted here, they exist near the intersection of the MCSL and the common data line N2 and near the intersection of the common data line N2 and the RD line, respectively.

As shown in the layout configuration of FIG. 10, by disposing the column decoder system on one side,
Even if the number of banks increases, one main column decoder 13 is sufficient if banks are added along the direction in which MCSL and LCSL extend. Also, in order to increase or decrease the number of sense amplifier blocks in a bank, the simple configuration of the local column decoder 15-x is changed for each bank, and the common data line N2 (LDQ line) for each sense amplifier block is shared while sharing the sense amplifier system. Can be achieved by increasing or decreasing

Next, the MC shown in FIG. 10 and FIG.
The configuration of the SL, ie, the MCSL is arranged in parallel with the LCSL and between the LCSLs (here, the LCS
The advantage of the configuration in which the MCSL is disposed at the center where L is symmetrically separated by two) will be described.

FIG. 11 shows a layout of an MCSL different from the present invention, in which the MCSL is arranged on the side of the LCSL. With such a configuration, if dust has to be attached to a position as shown in the figure on the wiring and must be replaced with a spare decode set, it cannot be replaced with one set.

FIG. 12 shows a layout of the MCSL according to the present invention, in which the MCSL is arranged in the LCSL arrangement. With such a configuration, if dust has to be attached to a position as shown in the figure on the wiring, and it must be replaced with a spare decode set, it is replaced with one set. That is, L on both sides
This indicates that even if the CSL becomes defective, it can be replaced with one set.

Therefore, according to the MCSL layout of the present invention, the MCSL (main column selection line) is
LCSL (local column selection line) selected by
In this case, the efficiency of replacement by the redundancy circuit (SCSL) with respect to the defect of the column selection system is increased. As a result, an improvement in yield is expected.

According to the present invention, the configuration in which the predecoding circuits (11, 12) are provided as in the above embodiment, and the common data line N2 (local DQ line) in each bank is connected via the switching element T2 RD line N3 (Main DQ
It is useful without necessarily using a configuration for connecting to the line).

The point is that the address signal is decoded, and the local column decoder 15 provided for each of a plurality of banks is provided.
-X receives the decode output, and each output line of the local column decoder 15-x functions as a gate control line of the switching element T1 for controlling connection between each of the plurality of bit lines and the common data line N2. Configuration. As a result, the circuit scale of the decoding system is kept small, and the chip area is reduced.

FIG. 13 shows an application example according to the present invention, in which the arrangement of the local column decoder 15-x is shown in FIG.
FIG. 3 is a circuit diagram illustrating a bank. Figure 9 shows the basic configuration
Therefore, the same reference numerals as in FIG. 9 are used.

That is, the circuit block F8 having the configuration shown in FIG.
Are provided in a predetermined number for each bank, but in order to share signal lines that can be shared, local column decoders 15-x are arranged adjacent to each other in adjacent banks.

There are actually eight circuit blocks F8 for each bank, and MCSL <0> to MCSL <7
> Signal is received. Here, a part of the transmission path of the MCSL is shared.

As described above, the local column decoder 1
Although 5-x is provided for each bank, the sharing of signal lines that can be shared achieves at least a reduction in the wiring area.

In FIG. 13, as in FIG. 9, since the inside of the bank BNKx has a general configuration including a memory cell array and a sense amplifier, the memory cell MC and the bit line connected thereto are connected to the sense amplifier S / A. , And the other general configuration is omitted. As in FIG. 1, each bit line BL is shown one by one, omitting a bit line pair. Therefore, each switching element T1 has one pair, and the common data line N2 has one pair. Therefore, the RD line N3 is also shown with one pair omitted.

FIG. 14 shows an application example according to the present invention, and is a layout configuration diagram showing a main column decoder and banks adjacent thereto. In this configuration, the decode blocks of the local column decoder for each bank are alternately divided and arranged with the banks interposed therebetween. This configuration is adopted in a situation where the arrangement pitch of the memory cell array is fine and the arrangement of the local column decoders cannot be integrated in the LCSL having a pitch suitable for the cell array by only one layout.

The memory cell array in the bank BNK0 forms a plurality of cell array blocks divided by sense amplifiers, and the sense amplifier blocks include sense amplifiers shared between adjacent memory cell array blocks.

One of the circuit blocks F8 in FIG. 8 is shown as a block in the local column decoder 15-00. MCSL which is an output line of the main column decoder 13
(Main column selection line) and local column decoder 15-
LCSL (local column select line), which is an output line of 00, is configured as a metal wiring layer on the memory cell array, and extends in parallel in a single direction. And LCS
The MCSL is arranged at the center where two Ls are symmetrically separated from each other.

In the local column decoder 15-00, a circuit block F8 for every other MCSL is formed. In the local column decoder 15-01,
A circuit block F8 is formed for every other MCSL except for the part configured in the block 15-00.

According to the above embodiment, the column address commonly input to all the banks is input only to the main column decoder, and the MCSL (main column selection line) is configured. Are arranged, the LCSLs (local column selection lines) are simplified, and each bank can be independently controlled, so that the circuit size can be reduced.

Further, since it is no longer necessary to input a column address to all the banks, the wiring of the column address system can be shortened. Therefore, since the charge / discharge current for the wiring can be reduced, the effect of suppressing power consumption can be obtained.

[0070]

As described above, according to the present invention, a column address commonly input to all banks is input to only the main column decoder to form a main column selection line, and a circuit is provided for each bank. A local column selection line whose configuration is simplified is arranged. As a result, in a plurality of memory cell array banks operating independently, a circuit size, a wiring scale, and an occupied area for transmitting an address to each of the banks can be reduced, and the layout of the memory cell array contributes to a reduction in chip area. Can be provided.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a main part of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a specific circuit diagram of a part of FIG.

FIG. 3 shows an input signal C in each of the four circuits of FIG. 2;
The figure of the truth value notation which shows the relationship between ADDi, CADDj, and output signal Y01P.

FIG. 4 is a specific circuit diagram of a part of FIG.

5 is an input signal C for each of the eight circuits in FIG. 4;
ADDi, CADDj, CADDk and output signal Y234
The figure of the truth value notation which shows the relationship of P.

FIG. 6 is a specific circuit diagram of a part of FIG.

FIG. 7 is a specific circuit diagram of a part of FIG.

FIG. 8 is a specific circuit diagram of a part of FIG.

FIG. 9 is a circuit diagram showing an arrangement configuration of a local column decoder for two banks.

FIG. 10 is a layout diagram showing a main column decoder and one bank adjacent to the main column decoder.

FIG. 11 is a plan view showing a layout form of main column selection lines different from the present invention.

FIG. 12 is a plan view showing a layout form of a main column selection line according to the present invention.

FIG. 13 is a circuit diagram showing an application example according to the present invention and showing an arrangement configuration of a local column decoder for two banks.

FIG. 14 is a layout diagram showing an application example according to the present invention, showing a main column decoder and a bank adjacent to the main column decoder.

[Explanation of symbols]

11, 12 column predecoder 13 main column decoder 14-0 to 14-3 local column address decoder 15-0 to 15-3 local column decoder MC memory cell S / A sense amplifier MCSL main Column select line LCSL Local column select line N2 Common data line (LDQ line) N3 Common data output line (RD line) T1 Switching element (DQ gate) T2 Switching element (Main DQ gate)

Continued on the front page (72) Inventor Toru Kimura 25-1, Ekimae Honcho, Kawasaki-ku, Kawasaki-shi, Kanagawa Prefecture Inside Toshiba Microelectronics Co., Ltd. (72) Inventor Masaru Koyanagi 580-1, Horikawa-cho, Sai-ku, Kawasaki-shi, Kanagawa Prefecture Co., Ltd. F-term in Toshiba Semiconductor System Engineering Center (reference) 5B024 AA01 AA07 BA15 BA18 CA07 CA16 CA17 CA19

Claims (4)

[Claims] A plurality of banks divided for independently operating the memory cell array, a common data line provided in each of the banks and transmitting data of a plurality of bit lines for each block, A first decoding circuit for decoding an address signal; and a plurality of output lines for inputting at least the address signal passed through the first decoding circuit, each of which is connected to each of the plurality of bit lines and the common data. A second decoding circuit provided for each of the plurality of banks, the second decoding circuit functioning as a signal line for controlling connection between lines. 2. A plurality of banks which are divided to operate independently with respect to the memory cell array, a common data line provided in each of the banks and transmitting data of a plurality of bit lines for each block, A first path for transmitting an address signal common to at least a plurality of banks and for selecting a common predetermined column with respect to the memory cell array of each bank; and a first path for transmitting an address signal for selecting a column independently for each bank. 2 path; and a mechanism controlled by the first and second paths and transmitting data of an activated sense amplifier in each block of the memory cell array to the common data line. Semiconductor storage device. 3. The semiconductor device according to claim 2, wherein said first path having a relationship in which a transmission signal controls said plurality of second paths is disposed between said plurality of second paths. Storage device. 4. The semiconductor memory device according to claim 1, wherein said second decoding circuit has a configuration in which a part of said plurality of banks is shared by adjacent banks.