JP3808667B2 - Semiconductor integrated circuit device - Google Patents

Description

【０１３８】
表１からわかるように、最上位のアドレス信号ADD3は単位領域R<0:7>、あるいは単位領域R<8:15>で同じ値を持つ。また、単位領域R<0:7>、単位領域R<8:15>では、アドレス信号ADD<0:2>によりデコードされる方法は全く同じである。
【０１３９】
したがって、単位領域R<7>と単位領域R<8>との間と、単位領域R<0>の直前とにそれぞれ、中継器群８０-1、８０-2をそれぞれ入れた場合、これら中継器群８０-1、８０-2をアドレス信号ADD3、およびその相補な信号でそれぞれ制御する。これにより、信号線の数を削減でき、デコード回路群８１Ａ、８１Ｂを構成するデコード回路８１-0〜８１-15それぞれに入力される信号の数を減らすことができる。
【０１４０】
例えば図７に示した例では、４ビットのアドレス信号ADD<0:3>をデコードするために必要な信号線の数は８本となるが、第７の実施形態では、BLKSEL線を入れても５本に抑えることができる。
【０１４１】
また、図８で示したプリデコード方式の例と比べても、配線数を減らすことができるだけでなく、デコード回路８１に入力される信号の数を減らすことができる。よって、チップ面積、動作速度の観点からも有利である。
【０１４２】
また、図１２に示す回路構成にした場合、信号BLKSELを非活性としても、少なくともアドレス信号ADD<0:3>が全て“LOW”レベルであれば、たとえば単位領域R<0>が選択された状態になってしまう。これを改善する場合には、たとえばデコード回路群８１を構成するデコード回路をそれぞれラッチ型にすれば良い。
【０１４３】
以上第１〜第７の実施形態により説明した発明においては、負荷容量の重い信号線に、中継器を挿入することで複数に分割し、さらにその信号線を入力とする回路の構成を分割された信号線ごとに逆相で動作する様に配置することで、中継器を含めた回路の動作をさせるためのゲートの段数を増やすことなく、アドレス信号の負荷容量も減らすことができる。その結果として、動作速度の低下を抑制できると同時に、チップ面積の増加を抑制することができる。
【０１４４】
また、救済回路２を構成する比較回路において、アドレス信号をインバータで受けて、その信号をヒューズの情報によりそのまま、あるいは反転させて出力する構成とすることで、アドレス信号線の負荷容量を軽減することができる。その結果として、ＤＲＡＭの集積度の増大に伴う動作速度の低下を抑制できると同時に、チップ面積の増加を抑制することができる。
【０１４５】
［第８の実施形態］
現在、一般的に用いられているリダンダンシ技術の方式は、セルアレイの複数行、または複数列を救済のためのセルアレイ単位として、テストの結果、欠陥のあったセルアレイ単位を、それと同じ大きさのスペアエレメント（リダンダントアレイ）で置き換える方式である。
【０１４６】
欠陥のあったセルアレイ単位のアドレス情報を記憶するには、不揮発性の記憶素子を用いる必要があり、通常ヒューズが用いられている。アドレス情報は複数ビットで構成されるため、複数ビットに応じた複数本のヒューズを含むヒューズセットがリダンダンシの単位となる。
【０１４７】
通常、スペアエレメントとヒューズセットとは１対１に対応され、チップ内にはスペアエレメントと同数のヒューズセットが設けられる。スペアエレメントを使用する場合には、それに対応するヒューズセット内のヒューズをアドレスに応じて切断する。
【０１４８】
近年、動作の高速化のために、ＲａｍｂｕｓＤＲＡＭのように、チップ内部に複数のバンクを持ち、それらのバンクが同時活性される状態を取り得るようなメモリチップが種々提案されている。このようなメモリチップでは、バンクを越えたメモリセルをカバーするようなスペアエレメントを持つことはできないので、救済効率が良いと言われているスペアエレメント集中配置方式（1995年、VLSI symp.予稿集、p108）を採用できず、各バンクに独立にスペアエレメントを用意する必要がある。この時、スペアエレメントとヒューズセットを１対１に対応させる方式では膨大な数のヒューズセットが必要となってしまう。即ち、バンク数や高速動作の制限等からスペアエレメントが狭い範囲しかカバーできない場合に、欠陥が偏在した場合にも対応できるようにする為には、この狭いセルアレイ領域ごとに、スペアエレメントを設けなければならない。これはチップ全体としてみると、チップあたりの平均欠陥数を大幅に越えたスペアエレメントをチップに組み込むことになるため、面積効率を悪化させていることになる。さらにスペアエレメントとヒューズセットとを１対１に対応させる方式では、スペアエレメントの増加に伴ってヒューズセットの数も増加してしまう。
【０１４９】
この問題に対処する方式として、スペアエレメントとヒューズセットとをフレキシブルに対応させるものが提案されている。基本的な考えとしてスペアエレメント数の増加は仕方がないものとするが、ヒューズセットに関しては１対１対応をくずすことで、歩留まりを落とすことなく、チップに組み込むヒューズセットの数の増加を抑えることが可能にできる。以下、この方式を、フレキシブルマッピングリダンダンシーと呼ぶ。
【０１５０】
（参考文献：ISSC '99 "A 1.6GB/s DRAM with Flexible Mapping Redundancy Technique and Additional Refresh Scheme"）フレキシブルマッピングリダンダンシーにおいては、不良アドレスを記憶する記憶回路（以下ヒューズセット）内に、スペアエレメント（以下リダンダントアレイ）とのマッピング情報も記憶させ、ヒューズセットがどのリダンダントアレイと対応させるかの情報を保持する。これにより、１ヒューズセットあたりのヒューズ数は、従来のリダンダントアレイとヒューズセットとを１対１に対応させる方式に比較して、このマッピング情報分増えるわけだが、１チップあたりの平均欠陥数に適した数のヒューズセット数を用意すればよいので、ヒューズセット数は前述の１対１対応に比較して減らすことができ、トータルのヒューズ数（＝ヒューズセット数×１ヒューズセットあたりのヒューズ数）が減る、という利点を持つ。従って、不良が偏在した場合にも自由度の高い不良救済を可能としながら、不良救済に必要なヒューズ数が減ることで、リダンダンシ回路の面積効率向上を図ることができる。
【０１５１】
第８の実施形態は、このようなフレキシブルマッピングリダンダンシーに関するものである。
【０１５２】
第８の実施形態の説明に先立ち、参考例として、フレキシブルマッピングリダンダンシーを説明する。
【０１５３】
図１３は、この発明の第８の実施形態の第１の参考例に係る半導体記憶装置のメモリセルアレイを示す図である。
【０１５４】
まず、図１３に示すように、メモリセルアレイ１００は、ｍ列×ｎ行のマトリクス状のサブアレイＡ(m,n)に分割されている。この例ではメモリセルアレイは行方向に沿ってｍ＝４個、列方向に沿ってｎ＝１６個の計４×１６＝６４個のサブアレイに分割されている。サブアレイはリダンダントアレイにより救済される救済単位の範囲ともなっている。
【０１５５】
行方向に沿って並ぶ４個のサブアレイＡ(0,n)〜Ａ(4,n)は、１つのバンクを構成していて、この例では１６個のバンクBANKn（n＝0〜15）が配置されている。同様に列方向に沿って並ぶ１６個のサブアレイＡ(m,0)〜Ａ(m,15)は、１つのセグメントを構成していて、この例では４個のセグメントSEGMENTm（m＝0〜3）が配置されている。外部からアドレスバッファを介して供給されるローアドレス（ROW ADD）、およびカラムアドレス（COLUMN ADD）が入力されると、それぞれがローデコーダ（ＲＤ）、カラムデコーダ（ＣＤ）でデコードされ、サブアレイ中のワード線（ＷＬ）、カラム選択線（ＣＳＬ）が選択され、そのアドレスにより指定されたメモリセルに書き込みや読み出しといった動作が行うことができる。
【０１５６】
図１３に示すように、各サブアレイＡ(m,n)の行方向に沿った両端に、冗長セルアレイとしてリダンダントアレイＲＡ（m,n）；m＝0〜7、n＝0〜15が配置されている。リダンダントアレイＲＡ（m,n）の総数は、８×１６＝１２８個である。リダンダントアレイＲＡ（m,n）はスペアカラム選択線（ＳＣＳＬ０〜ＳＣＳＬ７）によって選択される。スペアカラム選択線（ＳＣＳＬ０〜ＳＣＳＬ７）は、カラム選択線（ＣＳＬ）と平行に配置され、同一セグメントの全バンクに関して共有化されている。このようなスペアカラム選択線（ＳＣＳＬ０〜ＳＣＳＬ７）は、スペアカラム選択線ドライバ（ＳＣＤ）により駆動される。
【０１５７】
サブアレイＡ（m,n）中のメモリセルに不良があった場合、その不良メモリセルを含むセルアレイ単位に対応するカラム選択線ＣＳＬをスペアカラム選択線ＳＣＳＬで置き換えることで、リダンダントアレイＲＡ(m,n)への置き換えが行われる。どのアドレスに関して、置き換えを行うか否かの制御情報は、不揮発性記憶回路にプログラムされる。不揮発性記憶回路は一般にヒューズが用いられる。この例では、不揮発性記憶回路として、１４個のヒューズセット（ＦＡ０〜ＦＡ１３）が用意され、それぞれカラムデコーダ、およびスペアカラム駆動回路に沿ってアレイ状に配置されている（以下、便宜上、ヒューズセットアレイと呼ぶ）。ヒューズセット（ＦＡ０〜ＦＡ１３）は不良セルの置き換えを実行するか否かを判定する冗長判定回路である。そして、１つのヒューズセットは、１本のスペアカラム選択線ＳＣＳＬを指定する。
【０１５８】
図１４は、この発明の第８の実施形態の第１の参考例に係るヒューズセットアレイを示す図である。なお、図１４中のＡ点〜Ｐ点はそれぞれ、図１３中のＡ点〜Ｐ点それぞれに接続されているものとする。
【０１５９】
図１３、および図１４に示すように、フレキシブルマッピングリダンダンシーでは、ヒューズセット（ＦＡ０〜ＦＡ１３）をそれぞれ、リダンダントアレイＲＡ(m,n)にフレキシブルに対応させる。この例では、１４個のヒューズセット（ＦＡ０〜ＦＡ１３）がそれぞれ、１２８個のリダンダントアレイＲＡ(m,n)のいずれにも対応できる。このため、各ヒューズセット（ＦＡ０〜ＦＡ１３）の出力はそれぞれ、リダンダンシー置き換えをするか否かの置換制御信号線ＲＤＨＩＴ０〜ＲＤＨＩＴ７に、ワイヤドオア接続されている。置換制御信号線ＲＤＨＩＴｎの電位は、通常“LOW”レベルであるが、ｎ番目のスペアカラム選択線ＳＣＳＬｎを駆動するとき、“HIGH”レベルとなる。この場合、ｎ番目の置換制御信号線ＲＤＨＩＴｎに対応するノーマルセルアレイのカラム選択線（ＣＳＬ）は駆動されない。
【０１６０】
図１５は、ヒューズセットの一回路例を示す回路図である。
【０１６１】
図１５に示すように、ヒューズセットは、不良アドレス指定用ヒューズ回路２０１、アドレス比較回路２０２、ヒューズ情報一致検出回路２０３、イネーブル用ヒューズ回路２０４、デコーダ２０５、およびマッピング用ヒューズ回路２０６を含む。
【０１６２】
不良アドレス指定用ヒューズ回路２０１は、不良アドレス情報をヒューズの状態（切断か非切断）に対応させて記憶する。この回路例に係るヒューズ回路２０１の出力はヒューズが切断されている場合“HIGH”レベルとなり、切断されていない場合“LOW”レベルとなる。ヒューズＦＳ（ＦＳ(1)〜ＦＳ(11)）は、救済単位を示すアドレスの数だけ設けられている。この例では、カラム選択線（ＣＳＬ）を指定するためのアドレスａ０〜ａ６、およびバンクを指定するためのアドレスｂ０〜ｂ３にそれぞれ対応して合計１１個設けられている。ヒューズ回路２０１は、ヒューズＦＳ(1)〜ＦＳ(11)ごとに合計１１の不良アドレス情報を出力する。ヒューズ回路２０１の各出力はそれぞれ、アドレス比較回路（ＣＭＰ）２０２（２０２-a0〜２０２-a6、２０２-b0〜２０２-b3）に入力される。
【０１６３】
アドレス比較回路２０２は、ヒューズ回路２０１の出力と、入力アドレス（ａ０〜ａ６、ｂ０〜ｂ３）とを比較する。この回路例に係るアドレス比較回路２０２は、入力アドレス情報が不良アドレス情報に一致した場合、その出力が“HIGH”レベルとなる。比較回路２０２の出力は、ヒューズ情報一致検出回路（ＡＮＤ）２０３に入力される。
【０１６４】
ヒューズ情報一致検出回路２０３は、たとえばＡＮＤ回路であり、イネーブル用ヒューズ回路２０４の出力によってイネーブル／デッセーブルされる。この回路例に係るイネーブル用ヒューズ回路２０４のヒューズＦＳ(12)は、ヒューズ情報一致検出回路２０３をイネーブルするとき、切断される。ヒューズＦＳ(12)が切断されている場合、ヒューズ回路２０４の出力は“HIGH”レベルとなり、ヒューズ情報一致検出回路２０３はイネーブルされる。一方、ヒューズＦＳ(12)が切断されていない場合、ヒューズ回路２０４の出力は“LOW”レベルとなり、ヒューズ情報一致検出回路２０３はデッセーブルされる。
【０１６５】
ヒューズ情報一致検出回路２０３は、アドレス比較回路２０２の出力、およびイネーブル用ヒューズ回路２０４の出力が全て“HIGH”レベルのとき、その出力を“HIGH”レベルとする。ヒューズ情報一致検出回路２０３の出力はデコーダ２０５に入力される。
【０１６６】
デコーダ２０５は、ヒューズ情報一致検出回路２０３の出力が“HIGH”レベルのときにイネーブルされ、マッピング用ヒューズ回路２０６からのマッピング情報をデコードし、置換制御信号線ＲＤＨＩＴ０〜ＲＤＨＩＴ７の一つを“HIGH”レベルとする。
【０１６７】
マッピング用ヒューズ回路２０６は、ヒューズセットと冗長セルアレイとの対応関係情報、即ちマッピング情報を、ヒューズの状態（切断か非切断）に対応させて記憶する。この回路例におけるマッピング情報は、該ヒューズセットを、８個のスペアカラム選択線ＳＣＳＬのどれに対応させるのかの情報であり、３個のヒューズＦＳ(13)〜ＦＳ(15)それぞれの状態の組み合わせ、即ち８通りの組み合わせにより記憶される。
【０１６８】
フレキシブルマッピングリダンダンシーでは、確かにヒューズセットの削減を図れる。しかし、ヒューズセットとリダンダントアレイの対応がフレキシブルであるために、チップの集積度が上がりヒューズセットの数もそれに応じて増加させたとき、一つの置換制御信号線（ＲＤＨＩＴｎ）には、増加させたヒューズセットがそれぞれ接続されることになる。この結果、一つの置換制御信号線（ＲＤＨＩＴｎ）に付加されるジャンクション容量は、増加させたヒューズセットの最終段の出力トランジスタ分増え、その負荷容量が増す。これは置換制御信号線（ＲＤＨＩＴｎ）に伝搬する信号の遅延を招く。一般に、置換制御信号線（ＲＤＨＩＴｎ）のパスはクリティカルパスなので、動作の高速化を妨げる。
【０１６９】
図１６は、第２の参考例に係る３２バンク構成のメモリセルアレイを示す図、図１７はそのヒューズセルアレイを示す図である。なお、図１６中のＡ点〜Ｐ点はそれぞれ、図１７中のＡ点〜Ｐ点それぞれに接続されているものとする。
【０１７０】
たとえば図１６、図１７それぞれに示すように、１６バンク構成から、３２バンク構成に集積度が上がった場合、救済効率を落とさないために、２８個のヒューズセット（ＦＡ０〜ＦＡ１３、ＦＢ０〜ＦＢ１３）を設けたとする。この場合、一つの置換制御信号線（ＲＤＨＩＴｎ）に付加されるジャンクション容量は、図１４に示した１４個のヒューズセット（ＦＡ０〜ＦＡ１３）の場合の２倍となり、置換制御信号線（ＲＤＨＩＴｎ）における信号遅延の影響は、無視できないものとなる。
【０１７１】
また、１４個のヒューズセット（ＦＡ０〜ＦＡ１３）を含むヒューズセットアレイの長さＬ-FSAが、ほぼメモリセルアレイ１００の行方向に沿った長さＬ-MCAに等しかった場合、ヒューズセットを２８個設けるためには、図１７に示すように、ヒューズセットアレイを１４個ずつ、２列にしなければならない。
【０１７２】
チップにおけるヒューズセット配置部のエリアペナルティーの点から考えると、ヒューズセット配置部の面積は、下地となるトランジスタ形成部の面積よりも、配線層の数、および配線層間のピッチに律速される。
【０１７３】
図１７に示すように、ヒューズセット配置部にヒューズセットアレイを２列に配置した場合、このヒューズセット配置部には、８本の置換制御信号線（ＲＤＨＩＴ０〜ＲＤＨＩＴ７）が折り返されて、１６本配置される。このようにヒューズセット配置部に配置される配線層、即ち、置換制御信号線（ＲＤＨＩＴ０〜ＲＤＨＩＴ７）の増加は、ヒューズセット配置部の面積増加、ひいてはチップの面積増加に直結する。
【０１７４】
以上の状況に鑑み、第８の実施形態は、フレキシブルマッピングリダンダンシーを用いた半導体記憶装置において、高集積化の要求を満たしつつ、置換制御信号線の負荷容量を減らすことを目的とする。
【０１７５】
図１８は、この発明の第８の実施形態に係る半導体記憶装置が具備するヒューズセットアレイを示す図である。なお、図１８中のＡ点〜Ｐ点はそれぞれ、図１６中のＡ点〜Ｐ点それぞれに接続されているものとする。
【０１７６】
図１８に示すように、８本の置換制御信号線ＲＤＨＩＴ０〜ＲＤＨＩＴ７は、図１６に示した８個のスペア選択線ドライバ（ＳＣＤ）それぞれに対応して設けられている。置換制御信号線ＲＤＨＩＴ０〜ＲＤＨＩＴ７にはそれぞれ、各対応するスペア選択線ドライバ（ＳＣＤ）を駆動するための置換制御情報が伝わる。置換制御信号線ＲＤＨＩＴ０、ＲＤＨＩＴ１は、４つのセグメントSEGMENT0〜SEGMENT3のうち、SEGMENT0に対応する。同様に置換制御信号線ＲＤＨＩＴ２、ＲＤＨＩＴ３はSEGMENT1、置換制御信号線ＲＤＨＩＴ４、ＲＤＨＩＴ５はSEGMENT2、置換制御信号線ＲＤＨＩＴ６、ＲＤＨＩＴ７はSEGMENT3に対応する。置換制御情報は、ヒューズセットＦＡ０〜ＦＡ１３、またはＦＢ０〜ＦＢ１３から出力される。
【０１７７】
この第８の実施形態では、ヒューズセットＦＡ０〜ＦＡ１３は、８本の置換制御信号線ＲＤＨＩＴ０〜ＲＤＨＩＴ７のうち、４本の置換制御信号線ＲＤＨＩＴ０、ＲＤＨＩＴ２、ＲＤＨＩＴ４、ＲＤＨＩＴ６に対応して設けられ、ヒューズセットＦＢ０〜ＦＢ１３は、他の４本の置換制御信号線ＲＤＨＩＴ１、ＲＤＨＩＴ３、ＲＤＨＩＴ５、ＲＤＨＩＴ７に対応して設けられている。
【０１７８】
図１９は、ヒューズセット（ＦＡ０〜ＦＡ１３）の一回路例を示す回路図である。
【０１７９】
図１９に示すように、ヒューズセットは、図１５に示した参考例と同様に、不良アドレス指定用ヒューズ回路２０１、アドレス比較回路２０２、ヒューズ情報一致検出回路２０３、イネーブル用ヒューズ回路２０４、デコーダ２０５、およびマッピング用ヒューズ回路２０６を含む。
【０１８０】
図１９に示すヒューズセットが、図１５に示したヒューズセットと異なるところは、次の通りである。
【０１８１】
第１に、バンクが“１６”から、“３２”に増えたことにより、バンクを指定するためのアドレスｂ４が１本追加されている。これにより、不良アドレス指定用ヒューズ回路２０１のヒューズＦＳは、カラム選択線（ＣＳＬ）を指定するためのアドレスａ０〜ａ６、およびバンクを指定するためのアドレスｂ０〜ｂ４にそれぞれ対応して合計１２個（ＦＳ１〜ＦＳ１２）設けられる。
【０１８２】
第２に、マッピング用ヒューズ回路２０６は、４本の置換制御信号線のいずれか１本を指定すれば良い。このため、マッピング用ヒューズ回路２０６のヒューズＦＳが１個減り、２個（ＦＳ１４、ＦＳ１５）となる。
【０１８３】
このような第８の実施形態によれば、図１７に示した参考例に係るヒューズセットと比較して、同じセグメント内（救済単位）の二つのスペアカラム選択線ＳＣＳＬ、例えば図１６中のスペアカラム選択線ＳＣＳＬ０、およびＳＣＳＬ１を制御する置換制御信号線ＲＤＨＩＴ０、ＲＤＨＩＴ１に接続されるヒューズセットからの複数の出力はそれぞれ独立となりワイヤードオア接続されていない。
【０１８４】
一方、異なるセグメント（救済単位）どうしでは、参考例のフレキシブルマッピングリダンダンシーの同様に、対応するヒューズセット（図１８中ではＲＤＨＩＴ０、ＲＤＨＩＴ２、ＲＤＨＩＴ４、ＲＤＨＩＴ６に対して、ＦＡ０〜ＦＡ１３、ＲＤＨＩＴ１、ＲＤＨＩＴ３、ＲＤＨＩＴ５、ＲＤＨＩＴ７に対して、ＦＢ０〜ＦＢ１３）の出力同士はワイヤードオア接続されている。結果として、図１７と図１８とを比較してわかるとおり、救済効率を落とさない範囲で、一つの置換制御信号線に接続されるヒューズセットの数を減らすことができる。この例では、２本のスペアカラム選択線それぞれで１６バンク以上を救済しなければならないような確率が極めて低い場合に有効である。従って、一つの置換制御信号線に付加される寄生容量である、ヒューズセットの最終段の出力トランジスタのジャンクション容量が減り、クリティカルパスの一部をなす、置換制御信号線における置換制御情報の遅延を抑えることができる。
【０１８５】
また、図１８に示すように、ヒューズセット配置部に配置される配線層の数、即ち置換制御信号線の数を８本に、図１７に示す参考例の半分に減らせる。このため、置換制御信号線のピッチに律則されているヒューズセット配置部の面積を、その分減らすことができ、チップ面積増加を抑制に効果がある。
【０１８６】
さらに図１７に示す参考例では、マッピング用ヒューズ回路が８本の置換制御信号線のうち、いずれか一つを指定する必要があったが、第８の実施形態では４本の置換制御信号線のうち、いずれか一つを指定するだけで良い。このため、マッピング用ヒューズ回路のヒューズの数を減らせる、という利点もある。
【０１８７】
［第９の実施形態］
図２０は、この発明の第９の実施形態に係る半導体記憶装置が具備するヒューズセットアレイを示す図である。なお、図２０中のＡ点〜Ｐ点はそれぞれ、図１６中のＡ点〜Ｐ点それぞれに接続されているものとする。
【０１８８】
図２０に示すように、第８の実施形態と同様に、２８個のヒューズセットＦＡ０〜ＦＡ１３、ＦＢ０〜ＦＢ１３の２８個のヒューズが設けられている。
【０１８９】
ヒューズセットＦＡ０〜ＦＡ１３の列は、ヒューズセットＦＢ０〜ＦＢ１３の列と並行に配置されている。これらの列の間には、４本の配線層が配置されている。４本の配線層はそれぞれ、これらの列の中間（この例ではヒューズセットＦＡ６とＦＡ７との間、およびＦＢ６とＦＢ７との間）で分離されている。ヒューズセットＦＡ０〜ＦＡ６とヒューズセットＦＢ０〜ＦＢ６との間に配置された４本の配線層はそれぞれ、置換制御信号線ＲＤＨＩＴ０〜ＲＤＨＩＴ３を構成する。また、ヒューズセットＦＡ７〜ＦＡ１３と、ヒューズセットＦＢ７〜ＦＢ１３との間に配置された４本の配線層はそれぞれ、置換制御信号線ＲＤＨＩＴ４〜ＲＤＨＩＴ７を構成する。ヒューズセットＦＡ０〜ＦＡ６、ＦＢ０〜ＦＢ６はそれぞれ、置換制御信号線ＲＤＨＩＴ０〜ＲＤＨＩＴ３に接続され、ヒューズセットＦＡ７〜ＦＡ１３、ＦＢ７〜ＦＢ１３はそれぞれ、置換制御信号線ＲＤＨＩＴ４〜ＲＤＨＩＴ７に接続されている。
【０１９０】
このような第９の実施形態によれば、第８の実施形態と同様に、一つの置換制御信号線（ＲＤＨＩＴｎ）に接続されるヒューズセットの数が減る。これにより、置換制御信号線（ＲＤＨＩＴｎ）に付加されるジャンクション容量が減り、その負荷容量を減らすことができる。よって、置換制御信号線における置換制御情報の遅延を抑制できる。
【０１９１】
また、第９の実施形態では、図２０に示すように、配線層４本分のスペースに、８本の置換制御信号線ＲＤＨＩＴ０〜ＲＤＨＩＴ７を配置することができる。このようにヒューズセット配置部に配置される置換制御信号線の数は、実質的に４本まで減らせるので、ヒューズセット配置部の面積の増加は、さらに抑制しやすくなる。
【０１９２】
ただし、第９の実施形態では、一つのセグメントに対応するヒューズセットの数が、第８の実施形態の２８個から１４個に減るので、救済効率は第８実施形態に比較してやや低下する。しかし、実施に際しては、救済効率の向上を求める場合には第８の実施形態を選択し、チップ面積の増加の抑制をより強く求める場合には第９の実施形態を選択すれば良い。いずれにせよ、一つの置換制御信号線に付加されるジャンクション容量は減るので、その負荷容量は減る。
【０１９３】
［第１０の実施形態］
図２１はこの発明の第１０の実施形態に係る半導体記憶装置のメモリセルアレイを示す図、図２２はそのヒューズセルアレイを示す図である。なお、図２１中のＡ点〜Ｐ点はそれぞれ、図２２中のＡ点〜Ｐ点それぞれに接続されているものとする。
【０１９４】
図２１に示すように、第１０の実施形態は、１つのサブアレイＡ(m,n)に対して、３つのリダンダントアレイＲＡ(m,n)を設けたものである。即ち、各サブアレイＡ(m,n)の行方向に沿った一端に２つ、他端に１つ、冗長セルアレイとしてリダンダントアレイＲＡ（m,n）；m＝0〜11、n＝0〜31が配置されている。リダンダントアレイＲＡ（m,n）の総数は、１２×３２＝３８４個である。リダンダントアレイＲＡ（m,n）はスペアカラム選択線（ＳＣＳＬ０〜ＳＣＳＬ１１）によって選択される。
【０１９５】
また、図２２に示すように、ヒューズセットアレイには、１２本の置換制御信号線ＲＤＨＩＴ０〜ＲＤＨＩＴ１１が、図２１に示した１２個のスペア選択線ドライバ（ＳＣＤ）それぞれに対応して設けられている。置換制御信号線ＲＤＨＩＴ０〜ＲＤＨＩＴ１１にはそれぞれ、各対応するスペア選択線ドライバ（ＳＣＤ）を駆動するための置換制御情報が伝わる。
【０１９６】
置換制御信号線ＲＤＨＩＴ０〜ＲＤＨＩＴ２は、４つのセグメントSEGMENT0〜SEGMENT3のうち、SEGMENT0に対応する。同様に置換制御信号線ＲＤＨＩＴ３〜ＲＤＨＩＴ５はSEGMENT1、置換制御信号線ＲＤＨＩＴ６〜ＲＤＨＩＴ８はSEGMENT2、置換制御信号線ＲＤＨＩＴ９〜ＲＤＨＩＴ１１はSEGMENT3に対応する。置換制御情報は、ヒューズセットＦＡ０〜ＦＡ１３、またはＦＢ０〜ＦＢ１３から出力される。
【０１９７】
この第１０の実施形態では、ヒューズセットＦＡ０〜ＦＡ１３は、１２本の置換制御信号線ＲＤＨＩＴ０〜ＲＤＨＩＴ１１のうち、６本の置換制御信号線ＲＤＨＩＴ０、ＲＤＨＩＴ２、ＲＤＨＩＴ４、ＲＤＨＩＴ６、ＲＤＨＩＴ８、ＲＤＨＩＴ１０に対応して設けられている。また、ヒューズセットＦＢ０〜ＦＢ１３は、他の６本の置換制御信号線ＲＤＨＩＴ１、ＲＤＨＩＴ３、ＲＤＨＩＴ５、ＲＤＨＩＴ７、ＲＤＨＩＴ９、ＲＤＨＩＴ１１に対応して設けられている。
【０１９８】
このような第１０の実施形態においても、第８、第９の実施形態と同様に、一つの置換制御信号線に接続されるヒューズセットの数を減らせるので、置換制御信号線の負荷容量を減らすことができる。
【０１９９】
また、複数の置換制御信号線をそれぞれ、複数のヒューズセットそれぞれに分割して対応させる場合には、互いに等しい数ずつに分割して対応させるのが好ましい。
【０２００】
つまり、置換制御信号線が８本の場合には、第８、第９の実施形態のように４本ずつに分割し、それぞれ１４個のヒューズセットに対応させる。また、置換制御信号線が１２本の場合には、第１０の実施形態のように６本ずつに分割し、それぞれ１４個のヒューズセットに対応させる等である。このように等しい数ずつに分割することで、救済効率の低下を抑制できる。
【０２０１】
たとえば１２本の置換制御信号を８本と４本とに分割し、それぞれ１４個のヒューズセットに対応させた場合、置換制御信号線の負荷容量が減る効果はもちろんあるが、救済効率は、いずれか一方、即ち８本の置換制御信号に対応する１４個のヒューズセットに律則されて低下してしまう。このような事情は、６本ずつ、それぞれ１４個のヒューズセットに対応させることで解消することができる。よって、置換制御信号線は、互いに等しい数ずつに分割するのが好ましい。
【０２０２】
［第１１の実施形態］
以上、第８〜第１０の実施形態により説明した基本構成を基にすると、ヒューズセットの数、置換制御信号線の分割の仕方、同一セグメント内のリダンダントアレイの数（あるいは１つのサブアレイに対するリダンダントアレイの数）等には、種々のバリエーションが考えられる。その一例を第１１の実施形態として説明する。
【０２０３】
図２３はこの発明の第１１の実施形態に係る半導体記憶装置のメモリセルアレイを示す図、図２４はそのヒューズセルアレイを示す図である。なお、図２３中のＡ点〜Ｐ点はそれぞれ、図２４中のＡ点〜Ｐ点それぞれに接続されているものとする。
【０２０４】
第１１の実施形態は、ヒューズセットの数を５６個、置換制御信号線を４本ずつに４分割、さらにリダンダントアレイ数は、１つのサブアレイＡ(m,n)に対して４つとしたものである。
【０２０５】
図２３に示すように、第１１の実施形態は、各サブアレイＡ(m,n)の行方向に沿った両端にそれぞれ２つずつ、冗長セルアレイとしてリダンダントアレイＲＡ（m,n）；m＝0〜15、n＝0〜31が配置されている。リダンダントアレイＲＡ（m,n）の総数は、１６×３２＝５１２個である。リダンダントアレイＲＡ（m,n）はスペアカラム選択線（ＳＣＳＬ０〜ＳＣＳＬ１５）によって選択される。
【０２０６】
また、図２４に示すように、ヒューズセットアレイには、１６本の置換制御信号線ＲＤＨＩＴ０〜ＲＤＨＩＴ１５が、図２１に示した１６個のスペア選択線ドライバ（ＳＣＤ）それぞれに対応して設けられている。置換制御信号線ＲＤＨＩＴ０〜ＲＤＨＩＴ１５にはそれぞれ、各対応するスペア選択線ドライバ（ＳＣＤ）を駆動するための置換制御情報が伝わる。
【０２０７】
置換制御信号線ＲＤＨＩＴ０〜ＲＤＨＩＴ３は、４つのセグメントSEGMENT0〜SEGMENT3のうち、SEGMENT0に対応する。同様に置換制御信号線ＲＤＨＩＴ４〜ＲＤＨＩＴ７はSEGMENT1、置換制御信号線ＲＤＨＩＴ８〜ＲＤＨＩＴ１１はSEGMENT2、置換制御信号線ＲＤＨＩＴ１２〜ＲＤＨＩＴ１５はSEGMENT3に対応する。置換制御情報は、ヒューズセットＦＡ０〜ＦＡ１３、またはＦＢ０〜ＦＢ１３、またはヒューズセットＦＣ０〜ＦＣ１３、またはヒューズセットＦＤ０〜ＦＤ１３、から出力される。
【０２０８】
この第１０の実施形態では、ヒューズセットＦＡ０〜ＦＡ１３は、１６本の置換制御信号線ＲＤＨＩＴ０〜ＲＤＨＩＴ１５のうち、４本の置換制御信号線ＲＤＨＩＴ０、ＲＤＨＩＴ４、ＲＤＨＩＴ８、ＲＤＨＩＴ１２に対応して設けられている。また、ヒューズセットＦＢ０〜ＦＢ１３は、他の４本の置換制御信号線ＲＤＨＩＴ１、ＲＤＨＩＴ５、ＲＤＨＩＴ９、ＲＤＨＩＴ１３に対応して設けられている。また、ヒューズセットＦＣ０〜ＦＣ１３は、さらに別の４本の置換制御信号線ＲＤＨＩＴ２、ＲＤＨＩＴ６、ＲＤＨＩＴ１０、ＲＤＨＩＴ１４に対応して設けられている。また、ヒューズセットＦＤ０〜ＦＤ１３は、残りの４本の置換制御信号線ＲＤＨＩＴ３、ＲＤＨＩＴ７、ＲＤＨＩＴ１１、ＲＤＨＩＴ１５に対応して設けられている。
【０２０９】
このような第１１の実施形態においても、第８〜第１０の実施形態と同様に、一つの置換制御信号線に接続されるヒューズセットの数を減らせるので、置換制御信号線の負荷容量を減らすことができる。
【０２１０】
このような第１１の実施形態以外にも、ヒューズセットの数、置換制御信号線の分割の仕方、同一セグメント内のリダンダントアレイの数（あるいは１つのサブアレイに対するリダンダントアレイの数）等は、種々のバリエーションが考えられる。
【０２１１】
また、同一セグメント内の全てのリダンダントアレイについて、互いにワイヤードオア接続されることのないヒューズセット列にそれぞれ分割できない場合も考えられる。この場合、分割可能な範囲で、あるいは分割可能な範囲の一部のみ、分割すれば良い。
【０２１２】
また、同じセグメント内の二つのＳＣＳＬ、たとえばスペアカラム選択線ＳＣＳＬ０を制御する置換制御信号線ＲＤＨＩＴ０に接続されるヒューズセットＦＡ０〜ＦＡ１３からの出力は、スペアカラム選択線ＳＣＳＬ１を制御する置換制御信号線ＲＤＨＩＴ１に接続されるヒューズセットＦＢ０〜ＦＢ１３からの出力とそれぞれ独立となり、ワイヤードオア接続されていない。しかし、この概念的に分割されたヒューズセットＦＡ０〜１３、ＦＢ０〜１３は実際のチップ内でいかように配置しても良い。ただし、実際問題としては、チップの集積度が上がりヒューズセットの増加と共に、ヒューズセットを一列に並べて配置することは難しくなり、第８〜第１０の実施形態のように２列、あるいは３列、あるいは第１１の実施形態のように４列と並べて配置する方向にある。
【０２１３】
以上、第８〜第１１の実施形態はあくまで一例であり、不良アドレス記憶回路の記憶素子としてはヒューズ以外の素子、たとえばＰＲＯＭセルや、コンデンサを絶縁破壊して記憶する記憶素子（アンチヒューズ）等が使用されても良い。
【０２１４】
また、ヒューズ回路としては、他の構成の回路が用いられても良い。また、ヒューズ回路の配置、数等が異なるもの、実施形態中では、バンクやセグメントといった言葉で代表させているが、概念的には同じもので構成されたアレイといったものについても適用され得るものである。
【０２１５】
また、第８〜第１１の実施形態は、スペアカラム選択線に置き換える方式を例示したが、この発明は、スペアワード線に置き換える方式にも適用できることはもちろんである。
【０２１６】
以上、説明したように、リダンダントアレイとヒューズセットをフレキシブルに対応させる、フレキシブルマッピングリダンダンシーにおいては、通常、リダンダントアレイを駆動するドライバに入力される置換制御信号ＲＤＨＩＴは、各ヒューズセットからの複数の出力端子のそれぞれ対応するもの同士がワイヤードオア接続されている。
【０２１７】
これに対し、第８〜第１１の実施形態に係る半導体記憶装置によれば、同一救済範囲内の複数のリダンダントアレイにおいては、各リダンダントアレイを駆動するドライバに入力される置換制御信号ＲＤＨＩＴに対して、複数のヒューズセット列を各ヒューズセットからの出力端子がワイヤードオア接続されることのないヒューズセット列に分割する。これにより、リダンダンシーによる救済効率を落とすことなく、置換制御信号に対する寄生容量の低下による高速化、及びヒューズ部内の配線数を抑えることが可能になることによるヒューズ部の面積増加の抑制の効果を得ることができる。
【０２１８】
【発明の効果】
以上説明したように、この発明によれば、高集積化の要求を満たしつつ、高集積化に伴った動作速度の低下を抑制することが可能な半導体集積回路装置を提供できる。
【図面の簡単な説明】
【図１】図１はこの発明の第１の実施形態に係る半導体記憶装置の概略構成を示すブロック図。
【図２】図２は救済回路の一構成例を示すブロック図。
【図３】図３（Ａ）はアドレス比較回路の一回路例を示す回路図、図３（Ｂ）はアドレス比較回路の一動作例を示す動作波形図、図３（Ｃ）はヒューズ（Fuse）の状態と出力（FOUT）との関係を示す図。
【図４】図４（Ａ）、（Ｂ）はそれぞれこの発明の第２の実施形態に係るアドレス比較回路の一回路例を示す回路図。
【図５】図５はこの発明の第３の実施形態に係る半導体記憶装置の概略構成を示すブロック図。
【図６】図６はこの発明の第４の実施形態に係る半導体記憶装置の概略構成を示すブロック図。
【図７】図７はアドレス信号で直接デコードされるデコーダの回路図。
【図８】図８（Ａ）はプリデコード方式を用いたデコーダの回路図、図８（Ｂ）はプリデコード回路の回路図、図８（Ｃ）はプリデコード回路の入力と出力との関係を示す図。
【図９】図９（Ａ）はこの発明の第５の実施形態に係るプリデコード方式を用いたアドレスデコーダを示す回路図、図９（Ｂ）はプリデコード回路の回路図、図９（Ｃ）はプリデコード回路の入力と出力との関係を示す図。
【図１０】図１０はこの発明の第５の実施形態の変形例に係るアドレスデコーダを示す回路図である。
【図１１】図１１はこの発明の第６の実施形態に係るプリデコード方式を用いたアドレスデコーダを示す回路図。
【図１２】図１２はこの発明の第７の実施形態に係るプリデコード方式を用いたアドレスデコーダを示す回路図。
【図１３】図１３はこの発明の第８の実施形態の第１の参考例に係るメモリセルアレイを示す図。
【図１４】図１４はこの発明の第８の実施形態の第１の参考例に係るヒューズセットアレイを示す図
【図１５】図１５はヒューズセットの一回路例を示す回路図。
【図１６】図１６はこの発明の第８の実施形態の第２の参考例に係るメモリセルアレイを示す図。
【図１７】図１７はこの発明の第８の実施形態の第２の参考例に係るヒューズセットアレイを示す図
【図１８】図１８はこの発明の第８の実施形態に係る半導体記憶装置が具備するヒューズセットアレイを示す図。
【図１９】図１９はこの発明の第８の実施形態に係る半導体記憶装置が具備するヒューズセットの一回路例を示す回路図。
【図２０】図２０はこの発明の第９の実施形態に係る半導体記憶装置が具備するヒューズセットアレイを示す図。
【図２１】図２１はこの発明の第１０の実施形態に係る半導体記憶装置が具備するヒューズセットアレイを示す図。
【図２２】図２２はこの発明の第１０の実施形態に係る半導体記憶装置が具備するヒューズセットの一回路例を示す回路図。
【図２３】図２３はこの発明の第１１の実施形態に係る半導体記憶装置が具備するヒューズセットアレイを示す図。
【図２４】図２４はこの発明の第１１の実施形態に係る半導体記憶装置が具備するヒューズセットの一回路例を示す回路図。
【符号の説明】
１…セルアレイ、
２Ａ、２Ｂ…救済回路、
３…アドレス発生回路、
４…中継器、
５、５Ａ、５Ｂ、５Ｃ…アドレス信号線、
１０…冗長判定回路、
１１…イネーブル用ヒューズ回路、
１２…アドレス比較回路、
１３…判定回路、
１４…出力回路、
２１…不良アドレス指定用ヒューズ回路、
２２…ラッチ回路、
２３、２３Ａ、２３Ｂ…トランスファ回路、
３１…ＮＭＯＳ、
３２…ＰＭＯＳ、
３３、３４…トランスファゲート、
３５…ラッチ回路２２の出力ノード、
３６、３７Ａ、３７Ｂ…インバータ、
３８Ａ、３８Ｂ…クロックドインバータ、
３９Ａ、３９Ｂ…トランスファゲート、
６０Ａ、６０Ｂ…アドレス信号処理回路、
６１Ａ、６１Ｂ…プリデコード回路群、
６２Ａ、６２Ｂ…デコード回路群、
６３…プリデコード信号線群、
６４…共有化されたＮＭＯＳ、
７０…デコーダ、
７１…ＮＯＲ回路、
７２…グローバル配線、
７３Ａ、７３Ｂ…プリデコード回路、
７４…グローバル配線、
７５…ＮＯＲ回路、
７６Ａ、７６Ｂ…プリデコード回路、
８０…中継器群、
８１Ａ、８１Ｂ…デコード回路群、
１００…メモリセルアレイ、
２０１…不良アドレス指定用ヒューズ回路、
２０２…アドレス比較回路、
２０３…ヒューズ情報一致検出回路、
２０４…イネーブル用ヒューズ回路、
２０５…デコーダ、
２０６…マッピング用ヒューズ回路。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to high-speed operation of a semiconductor integrated circuit device, and is particularly used for a semiconductor memory device having a large-scale storage capacity.
[0002]
[Prior art]
In recent years, dynamic semiconductor memory devices (DRAMs) having a one-transistor / one-capacitor type memory cell structure have been highly integrated and miniaturized due to advances in memory cell improvement / microfabrication technology and circuit design technology. This is a significant step and this trend is expected to continue.
[0003]
As the DRAM is highly integrated, that is, the storage capacity is increased, the number of peripheral circuits integrated on one chip is increasing. For example, a row decoder or column decoder that decodes address information and selects a row or column of a cell array, or a repair circuit that activates a spare cell array by comparing defective address information with input address information, It tends to increase gradually.
[0004]
In recent years, with DRAMs, there has been an increasing demand for speeding up the operation as the storage capacity increases.
[0005]
[Problems to be solved by the invention]
However, as a result of an increase in the number of row decoders, column decoders, relief circuits, etc., it has become a disadvantageous situation for the demand for high-speed operation.
[0006]
Circuits such as a row decoder, a column decoder, or a relief circuit are address information processing circuits that are connected to address signal lines and process address information. That is, as a result of the increase in the number of address information processing circuits, the increase in the load capacity of the address signal line has become remarkable.
[0007]
The increase in the load capacity of the address signal line is very disadvantageous for the demand for high speed operation. For example, if the load capacity of the address signal line increases and the propagation delay of the address signal line increases, the processing operation of the row decoder, column decoder, relief circuit, etc. is delayed, and as a result, the read speed or write speed decreases. End up.
[0008]
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor integrated circuit device capable of suppressing a decrease in operation speed due to high integration while satisfying the demand for high integration. It is to provide.
[0009]
[Means for Solving the Problems]
  ThisThe semiconductor integrated circuit device according to the first aspect of the invention isA first signal line group for transmitting predecoded information obtained by predecoding at least two bits of information, and parallel to the first signal line group and divided into at least two first parts and second parts , Provided between a second signal line group transmitting at least 2 bits of information, a first portion of the second signal line group, and a second portion of the second signal line group, A relay group that inverts logic transmitted to the first part and transmits the information to the second part, a first predecode circuit group that predecodes the information transmitted to the first part, and the first A second predecode circuit group having the same configuration as that of the predecode circuit group and predecoding information transmitted to the second portion; predecode information of the first predecode circuit; and the first signal line Pre-deco A first decode circuit group for decoding the received information and a predecode having the same configuration as the first decode circuit group and transmitted to the predecode information of the second predecode circuit and the first signal line group And a second decoding circuit group for decoding information.
[0021]
  the aboveFirst aspectAccording to the semiconductor integrated circuit device according to the present invention, the second signal line group for transmitting at least 2-bit information is divided into at least two first and second portions, and the first and second portions are divided. Repeater between partsgroupIs provided. The load capacity of the second signal line group is divided by the repeater, and the load capacity can be reduced.
[0022]
The second signal line group is set in parallel with the first signal line group for transmitting predecoded information obtained by predecoding at least two bits of information. With this configuration, the number of signal line groups can be reduced as compared with the case where only signal line groups that transmit predecoded predecoded information are parallel to each other.
[0023]
Further, since the number of signal line groups is reduced, the number of signals input to the first and second decoding circuit groups can be reduced.
[0024]
Therefore, it is possible to suppress a decrease in operation speed due to high integration while satisfying the demand for high integration.
[0025]
  ThisOf the inventionSecond aspectThe semiconductor integrated circuit device according toA signal line group for transmitting a plurality of bits of information divided into at least three first parts, a second part, and a third part, and the plurality of bits of information transmitted to the first part of the signal line group Is transmitted to the second portion, and the first repeater group controlled by at least one bit of information and the first decoding for decoding the plurality of bits of information transmitted to the second portion of the signal line group A plurality of bits of information transmitted to the circuit group and the second part of the signal line group are transmitted to the third part and controlled by at least one bit of information complementary to the at least one bit of information; And a second decoding circuit group having the same configuration as the first decoding circuit group and decoding the information of the plurality of bits transmitted to the third portion of the signal line group.
[0026]
  the aboveSecond aspectAccording to the semiconductor integrated circuit device according to the above, the signal line group for transmitting information of a plurality of bits is divided by the first and second repeater groups, so that the load capacity can be reduced.
[0027]
In addition, since the first repeater group is controlled by at least one bit information and the second repeater group is controlled by the complementary information thereof, the decoding constituting the first and second decode circuit groups The number of input signals to the circuit can be reduced.
[0028]
Therefore, it is possible to suppress a decrease in operation speed due to high integration while satisfying the demand for high integration.
[0029]
  ThisOf the inventionThird aspectThe semiconductor integrated circuit device according toIncluding a plurality of rescue units, and each of the plurality of rescue units,A cell array in which a plurality of memory cells and spare cells are arranged;For each of the plurality of relief units,Among the plurality of spare cells, a plurality of spare selection lines provided for selecting an arbitrary spare cell;For each of the plurality of relief units,A spare selection line driver provided corresponding to each of the plurality of spare selection lines and driving each corresponding spare selection line, and a corresponding spare selection line driver provided corresponding to each of the spare selection line drivers. A replacement control signal line group for transmitting replacement control information for driving the signal, and a plurality of redundancy judgment circuits provided corresponding to some of the replacement control signal line groups among the replacement control signal line groups A second redundancy judgment circuit group, and a second redundancy judgment circuit group provided corresponding to a replacement control signal line other than the part of the replacement control signal lines in the replacement control signal line group. And redundant judgment circuit groupEach of the plurality of redundancy judgment circuits includes a defective address designating program circuit in which defective address information of the cell array is programmed, and whether or not the defective address information programmed in the defective address information program circuit matches the input address information. Based on the coincidence detection circuit for detecting the correspondence, the mapping program circuit in which the correspondence information with the replacement control signal line group is programmed, the detection result of the coincidence detection circuit and the correspondence relation information of the mapping program circuit, And a replacement control signal line for controlling the spare selection line in the same repair unit among the repair units. The output of the output circuit is not wired-or connected, and among the repair units, the repair unit in a different repair unit Replacement control signal lines for controlling the pair selection line only, the output of the output circuit of the redundancy determination circuit group for wired connections.
[0030]
  the aboveThird aspectAccording to the semiconductor integrated circuit device of the present invention, a plurality of redundancy judgment circuits are made to correspond to a part of the replacement control signal line group in the replacement control signal line group and a part of the replacement control signal line group other than this part, respectively. Provide. As a result, the number of redundancy determination circuits connected to one replacement control signal line can be reduced, and the load capacity can be reduced.
[0031]
In addition, since the redundancy judgment circuit is provided corresponding to a part of the replacement control signal line group or a part of the replacement control signal line group, compared with the case where the redundancy judgment circuit is associated with one replacement control signal line. This increases the relief efficiency and is advantageous for high integration.
[0032]
Therefore, it is possible to suppress a decrease in operation speed due to high integration while satisfying the demand for high integration.
[0033]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0034]
[First Embodiment]
FIG. 1 is a block diagram showing a schematic configuration of a semiconductor memory device according to the first embodiment of the present invention.
[0035]
As shown in FIG. 1, the first embodiment includes four cell arrays 1-1 to 1-4, two relief circuits 2A-1 and 2A-2 corresponding to the cell arrays 1-2 and 1-3, It comprises two relief circuits 2B-1 and 2B-2 corresponding to the cell arrays 1-1 and 1-4, an address generation circuit (ADB) 3, and two repeaters 4-1 and 4-2. .
[0036]
The address generation circuit 3 outputs an address signal to the address signal line 5A. The address signal line 5A is connected to the relief circuits 2A-1, 2A-2 and the repeaters 4-1, 4-2, respectively.
[0037]
The repeater 4-1 amplifies the level of the address signal transmitted to the address signal line 5A and outputs it to the address signal line 5B-1. In the first embodiment, the repeater 4-1 is an inverter, inverts the logic of the address signal transmitted to the address signal line 5A, and outputs it to the address signal line 5B-1. The address signal line 5B-1 is connected to the relief circuit 2B-1.
[0038]
The repeater 4-2 amplifies the level of the address signal transmitted to the address signal line 5A and outputs it to the address signal line 5B-2. In the first embodiment, the repeater 4-2 is an inverter, which inverts the logic of the address signal transmitted to the address signal line 5A and outputs it to the address signal line 5B-2. The address signal line 5B-2 is connected to the relief circuit 2B-2.
[0039]
In the first embodiment, the relief circuits 2B-1 and 2B-2 have a configuration different from that of the relief circuits 2A-1 and 2A-2, and process an address signal with reverse logic.
[0040]
FIG. 2 is a block diagram illustrating a configuration example of the relief circuit 2. FIG. 2 illustrates a relief circuit 2 that decodes 2-bit address signals ADD0 and ADD1.
[0041]
As shown in FIG. 2, the relief circuit 2 includes a plurality of redundancy judgment circuits 10 (10-1 to 10-4). Each of the redundancy judgment circuits 10 corresponds to a unit (relief unit) for replacing a defective cell at a time.
[0042]
The redundancy judgment circuit 10 includes an enable fuse circuit (ENABLE FUSE) 11 indicating that the judgment circuit is used, an address comparison circuit 12 (12-1, 12-2) provided for each bit, and a judgment circuit ( Fuse information coincidence detection circuit) 13.
[0043]
The enabling fuse circuit 11 includes a fuse (not shown). Information (hereinafter referred to as enable information) indicating whether or not to use the redundancy judgment circuit 10 is programmed in this fuse.
[0044]
Each of the address comparison circuits 12 also includes a fuse (not shown). These fuses are programmed with defective address information of the cell array. The programmed defective address information is compared with the input address information.
[0045]
The determination circuit 13 receives the output FOUT0 of the enable fuse circuit 11, the output FOUT1 of the address comparison circuit 12-1, and the output FOUT2 of the comparison circuit 12-2. If these signals all output coincidence information, A control signal instructing to replace the address is output to the output circuit 14.
[0046]
The output circuit 14 is, for example, a NAND circuit that receives the output signals of the redundancy determination circuits 10-1 to 10-4. The output circuit 14 sets the output bSPRON to the “HIGH” level if even one of the outputs of the redundancy judgment circuits 10-1 to 10-4 is “LOW” level. The output bSPRON is a replacement control signal that instructs activation of the spare drive circuit.
[0047]
FIG. 3A is a circuit diagram showing one circuit example of the address comparison circuit 12.
[0048]
First, as shown in FIG. 3A, the address comparison circuit 12 includes a defective address designating fuse circuit 21, a latch circuit 22 composed of a plurality of inverters, and a transfer circuit 23.
[0049]
The defective address designating fuse circuit 21 includes a fuse. This fuse is programmed with defective address information of the cell array. The latch circuit 22 latches the defective address information output from the fuse circuit 21. The transfer circuit 23 selects and outputs either the address signal ADD or bADD which is a complementary signal (inverted signal) thereof based on the defective address information latched by the latch circuit 22.
[0050]
FIG. 3B is an operation waveform diagram showing an operation example of the address comparison circuit 12.
[0051]
Signals bFUP and FDWN shown in FIG. 3B are signals that are activated when the power is turned on. First, the power supply potential Vcc rises toward the “HIGH” level as the power is turned on. Along with this, the potential of the signal bFUP rises (time tON).
[0052]
After a certain time has elapsed since the power supply potential Vcc becomes “HIGH” level, the potential of the signal bFUP changes to “LOW” level. As a result, the PMOS 31 of the fuse circuit 21 that receives the signal bFUP at its gate is turned on (time t1). When the PMOS 31 is turned on, the output node (FLAT) of the fuse circuit 21 becomes the “HIGH” level, and the latch circuit 22 latches the initial information of the “HIGH” level. The signal bFUP transitions to the “HIGH” level after a sufficient time has elapsed for the latch circuit 22 to latch the “HIGH” level of the output level (FLAT). As a result, the PMOS 31 is turned off.
[0053]
After the signal bFUP transitions to the “HIGH” level, the signal FDWN transitions to the “HIGH” level. As a result, the NMOS 32 of the fuse circuit 21 that receives the signal FDWN at its gate is turned on (time t2). When the NMOS 32 is turned on, the output node (FLAT) of the fuse circuit 21 transitions to the “LOW” level when the fuse is “not blown” and maintains the “HIGH” level when it is “broken”. Thereby, the latch circuit 22 latches information corresponding to the state of the fuse. The signal FDWN transitions to the “LOW” level after a sufficient time has elapsed for the latch circuit 22 to latch the “LOW” level of the output level (FLAT). As a result, the NMOS 32 is turned off.
[0054]
In this way, the latch circuit 22 latches defective address information corresponding to whether the fuse is “cut” or “not blown”. The latched defective address information is supplied to the transfer circuit 23.
[0055]
Here, it is assumed that when the output FOUT of the comparison circuit 12 becomes “LOW” level, “determined that the defective address information and the input address information match”. In this case, when the address signal ADD = HIGH, if it is desired to match the defective address information with the input address information, the fuse may be blown. As a result, the output of the latch circuit 22 can make the transfer gate 33 for transferring the address signal ADD “off” and the transfer gate 34 for transferring the address signal bADD “on”. If the address signal ADD = HIGH, since the address signal bADD = LOW, the output FOUT is at the “LOW” level. FIG. 3C shows the relationship between the fuse state and the output FOUT.
[0056]
Next, an operation example of the relief circuit 2 will be described.
[0057]
First, the semiconductor memory device is tested before shipment.
[0058]
When a defective cell is found by this test, first, the fuse in the enable fuse circuit 11 (hereinafter referred to as an enable fuse) is cut, and enable information that “uses the redundancy judgment circuit 10” is programmed. Further, the fuses in the address comparison circuits 12-1 and 12-2 are cut, and "address information of defective cells" is programmed.
[0059]
In actual use, address signals ADD0 and ADD1 are externally input as input address information to the redundancy determination circuits 10-1 to 10-4, respectively. The input address information is compared with the defective address information in the address comparison circuits 12-1 and 12-2 provided in the redundancy determination circuits 10-1 to 10-4, respectively. Comparison information between the defective address information and the input address information, that is, outputs FOUT1 and FOUT2 are input to the determination circuit 13, respectively. The determination circuit 13 further refers to the output FOUT0 indicating the enable information, and outputs information indicating whether or not they match only when the enable fuse is blown.
[0060]
If any one of the determination circuits 13 provided in each of the redundancy determination circuits 10-1 to 10-4 outputs a signal that "defective address information and input address information match", the output circuit 14 is replaced. The control signal bSPRON is activated, and a normal cell is replaced with a spare cell.
[0061]
In the case of such a configuration, if even one defective cell is to be remedied, the number of redundancy judgment circuits 10 must be increased accordingly. Further, the number of redundancy judgment circuits 10 needs to be increased in order not to reduce the manufacturing yield as the density and miniaturization of memory cells progress.
[0062]
Due to these factors, the number of redundancy judgment circuits 10 tends to increase. Although the increase in the number of redundancy judgment circuits 10 mainly affects the chip area, it also leads to an increase in the load capacity of the address signal line 5 through which the address signals ADD0, bADD0, ADD1, and bADD1 are transmitted. An increase in the load capacity of the address signal line 5 affects the operation speed. In order to cope with such an increase in load capacity, it is necessary to increase the drive capability of the address generation circuit 3. In order to enhance the drive capability of the address generation circuit 3, for example, the size of the MOSFET that drives the address signal line 5 must be increased, which increases the chip area.
[0063]
On the other hand, in the first embodiment, the address signal line 5 is divided into a first portion 5A and a second portion 5B-1 (or 5B-2), and the first portion 5A and the second portion 5A are separated from each other. A repeater 4-1 (or 4-2) is provided between the portion 5B-1 (or 5B-2). As a result, the load capacity of the first portion 5A connected to the address generation circuit 3 in the address signal line 5 is the relief circuit 2A-1, 2A among the four relief circuits 2 each including the redundancy judgment circuit 10. -2 and the increase of the load capacity is suppressed. Therefore, even if the drive capability of the address generation circuit 3 is not so much enhanced, the relief circuits 2A-1 and 2A-2 can be operated at high speed, and the relief circuits 2B-1 and 2B-2 The relays 4-1 and 4-2 can be operated at high speed.
[0064]
Therefore, according to the first embodiment, it is possible to increase the operation speed while suppressing an increase in the chip area.
[0065]
All the conventional relief circuits 2 are circuits having the same configuration. For this reason, when it is assumed that the repeater 4 is provided between the relief circuits 2, the repeater 4 needs to be configured by two or more stages of inverters. For this reason, when the increase in the number of circuits required for the repeater 4 and the delay of the address signal due to the repeater 4 are taken into consideration, it is disadvantageous for suppressing the increase in area and speeding up the operation.
[0066]
On the other hand, in the first embodiment, the repeater 4 is composed of one or odd number of inverters, and the relief circuits 2B-1 and 2B-2 are opposite to the relief circuits 2A-1 and 2A-2. The address signal is processed by logic.
[0067]
In order to cause the relief circuits 2B-1 and 2B-2 to process the address signal with the reverse logic of the relief circuits 2A-1 and 2A-2, for example, the output of the latch circuit 22 shown in FIG. The node 35 may be connected to the PMOS of the transfer gate 33 and the NMOS of the transfer gate 34, and the output of the inverter 36 may be connected to the NMOS of the transfer gate 33 and the PMOS of the transfer gate 34.
[0068]
According to such a configuration, it is possible to reduce the number of inverters constituting the repeater 4 as compared with the case where all the relief circuits 2 have the same circuit configuration, and it is advantageous in suppressing the increase in chip area. be able to.
[0069]
Further, since the number of inverters constituting the repeater 4 can be reduced, the delay of the address signal from the address generation circuit 3 to the relief circuits 2B-1 and 2B-2 can be suppressed, which is advantageous for speeding up the operation. Can also be obtained.
[0070]
[Second Embodiment]
4A and 4B are circuit diagrams showing circuit examples of the address comparison circuit according to the second embodiment of the present invention. Note that in FIGS. 4A and 4B, portions common to those in FIG. 3A are denoted by common reference numerals.
[0071]
As shown in FIG. 4A, the address comparison circuit 12A includes a defective address designating fuse circuit 21, a latch circuit 22 composed of a plurality of inverters, an inverter 37A that receives an address signal ADD, and a transfer circuit that transfers the inverter 37A. 23A and the like. Each of the defective address designating fuse circuit 21 and the latch circuit 22 is the same as the address comparison circuit 12 shown in FIG.
[0072]
Transfer circuit 23A includes a clocked inverter 38A and a transfer gate 39A.
[0073]
The clocked inverter 38A is “OFF” when the output (output node 35) of the latch circuit 22 is “HIGH” level, and “ON” when it is “LOW” level. The transfer gate 39A is “ON” when the output (output node 35) of the latch circuit 22 is “HIGH” level, and “OFF” when it is “LOW” level.
[0074]
The inverter 37A inverts and supplies the logic level of the address signal ADD to the input of the clocked inverter 38A and the input of the transfer gate 39A.
[0075]
The address comparison circuit 12B shown in FIG. 4B is different from the address comparison circuit 12A in the circuit configuration of the transfer circuit 23B.
[0076]
Transfer circuit 23B includes a clocked inverter 38B and a transfer gate 39B.
[0077]
The clocked inverter 38B is “ON” when the output (output node 35) of the latch circuit 22 is “HIGH” level, and “OFF” when it is “LOW” level. The transfer gate 39B is “OFF” when the output (output node 35) of the latch circuit 22 is “HIGH” level, and “ON” when it is “LOW” level.
[0078]
Further, the inverter 37B inverts and supplies the logic level of the inverted address signal bADD to the input of the clocked inverter 38B and the input of the transfer gate 39B.
[0079]
According to the address comparison circuits 12A and 12B according to the second embodiment as described above, the inverter 37A or 37B receives the address signal ADD or bADD. For this reason, the capacity of the circuit subsequent to the inverter 37A or 37B, for example, the capacity of the transfer circuit 23A or 23B, or the capacity of the wiring through which the output FOUT is transmitted is not applied to the address signal line 5. Therefore, an increase in the load capacity of the address signal line 5 with an increase in the number of relief circuits 2 can be suppressed.
[0080]
Further, when the second embodiment is combined with the first embodiment, the following effects can be further obtained.
[0081]
For example, the address comparison circuit 12A is used for the relief circuits 2A-1 and 2A-2 shown in FIG. 1, and the address comparison circuit 12B is used for the relief circuits 2B-1 and 2B-2 shown in FIG.
[0082]
The output (output node 35) of the latch circuit 22 of the address comparison circuit 12A is at the “LOW” level when the fuse (Fuse) is blown. Therefore, the clocked inverter 38A is “ON” and the transfer gate 39A is “OFF”. Therefore, when the address signal ADD = LOW, the output FOUT = LOW.
[0083]
Further, the output (output node 35) of the latch circuit 22 of the address comparison circuit 12B is at the “LOW” level when the fuse (Fuse) is blown. Therefore, the clocked inverter 38B is “off” and the transfer gate 39B is “on”. Therefore, when the address signal bADD = HIGH, that is, when the address signal ADD = LOW, the output FOUT = LOW, and the output FOUT of the address comparison circuit 10A and the output FOUT of the address comparison circuit 10B both become “LOW” level. Become. That is, by using the address comparison circuits 10A and 10B according to the second embodiment, the address signal line 5 that has been conventionally required in a complementary manner can be eliminated by either one. Can be reduced. Therefore, an increase in chip area can be suppressed.
[0084]
In this case, the address comparison circuit 10A is used for the relief circuits 2A-1 and 2A-2, and the address comparison circuit 10B is used for the relief circuits 2B-1 and 2B-2. Therefore, the address comparison circuits are different between the relief circuits 2A-1 and 2A-2 and the relief circuits 2B-1 and 2B-2. For example, if the logic for cutting the fuse is changed, the relief circuit 2A- It is also possible to use the same address comparison circuit for 1, 2A-2 and the relief circuits 2B-1, 2B-2. The same applies to the first embodiment.
[0085]
[Third Embodiment]
The third embodiment is another example of a semiconductor memory device using the comparison circuits 10A and 10B according to the second embodiment.
[0086]
FIG. 5 is a block diagram showing a schematic configuration of a semiconductor memory device according to the third embodiment of the present invention.
[0087]
As shown in FIG. 5, in the third embodiment, no repeater is used for the address signal line 5. The address signal line 5 is used in a complementary manner as in the prior art. In FIG. 5, an address signal line / 5 is a signal line through which the inverted address signal bADD is transmitted, and is a signal line complementary to the signal line 5. The address comparison circuit 10A is used for the relief circuits 2A-1 and 2A-2, and the address comparison circuit 10B is used for the relief circuits 2B-1 and 2B-2.
[0088]
According to the third embodiment, the capacity of the circuit subsequent to the inverter 37A or 37B, for example, the capacity of the transfer circuit 23A or 23B, or the capacity of the wiring through which the output FOUT is transmitted is applied to the address signal lines 5 and / 5. No longer joins. Therefore, as in the first and second embodiments, it is possible to suppress an increase in the load capacity of the address signal lines 5 and / 5 with an increase in the number of relief circuits 2.
[0089]
Further, since the repeater 4 can be omitted and the number of relief circuits connected to the address signal line is reduced as compared with the conventional one, the address signals from the address generation circuit 3 to the relief circuit 2B-1 or 2B-2 can be reduced. Delay can be minimized.
[0090]
[Fourth Embodiment]
The fourth embodiment is still another example of the semiconductor memory device having the comparison circuits 10A and 10B according to the second embodiment. In the third embodiment, all the relief circuits 2 corresponding to a certain cell array are the same circuit. But of course not. The fourth embodiment is an example in which comparison circuits 10A and 10B are mixed in the relief circuit 2 corresponding to each cell array.
[0091]
FIG. 6 is a block diagram showing a schematic configuration of a semiconductor memory device according to the fourth embodiment of the present invention.
[0092]
As shown in FIG. 6, the relief circuits 2A-11 and 2B-11 correspond to the cell array 1-1. The circuit scale of the relief circuit 2A-11 is, for example, half that of the relief circuit 2A-1, and similarly, the circuit scale of the relief circuit 2B-11 is, for example, half that of the relief circuit 2B-1. The cell array 1-2 has relief circuits 2A-22 and 2B-22, the cell array 1-3 has a relief circuit 2A-33, the relief circuit 2B-33, and the cell array 1-4 has a relief circuit 2A-44. 2B-44 corresponds to each. The circuit sizes of the relief circuits 2A-22, 2A-33, 2A-44 are each half of the relief circuit 2A-1, for example, and the relief circuits 2B-22, 2B-33, 2B-44 are each, for example, the relief circuit 2B. Half of -1.
[0093]
Even if it is such a structure, the effect similar to 3rd Embodiment can be acquired.
[0094]
[Fifth Embodiment]
The fifth embodiment relates to an address decoder using a predecoding method, for example, a row decoder or a column decoder. Prior to the description of the fifth embodiment, an address signal predecoding method will be described.
[0095]
FIG. 7 is a circuit diagram of an address decoder that directly decodes an address signal.
[0096]
As shown in FIG. 7, the 4-bit address signal ADD <0: 3> has 2^FourThere are 16 combinations. Address signals ADD <0: 3> are input to the 16 sets of decoding circuits 50-0 to 50-15 in accordance with 16 combinations.
[0097]
Decode circuits 50-0 to 50-15 are, for example, four-input NAND circuits, and their output nodes R <0:15> are set to “LOW” level only when all four inputs are at “HIGH” level. . When the 4-bit address signal ADD <0: 3> is directly decoded, one address signal line is connected to 8 sets out of 16 sets of decode circuits 50-0 to 50-15.
[0098]
FIG. 8A is a circuit diagram showing an address decoder using a predecode method, and FIG. 8B is a circuit diagram of a predecode circuit.
[0099]
In contrast to the decoder shown in FIG. 7, a decoder using a predecode method first predecodes a 4-bit address signal ADD <0: 3> using the predecode circuit shown in FIG. , Predecode signals XA <0: 3> and XB <0: 3> are generated. These predecode signals XA <0: 3> and XB <0: 3> are input to 16 sets of decode circuits 50-0 to 50-15 as shown in FIG. FIG. 8C shows the predecode circuit input (address signals ADD <0: 3>, bADD <0: 3>) and output (predecode signals XA <0: 3>, XB <0: 3>). Show the relationship.
[0100]
When the predecode method is used, the predecode signal lines corresponding to the address signal lines may be connected to four sets of the 16 sets of decode circuits 50-0 to 50-15. Therefore, the load on the predecode signal line can be halved, and the decode circuits 50-0 to 50-15 need only have two inputs, and the decode circuits 50-0 to 50-15 can be simplified.
[0101]
As described above, the predecoding method is widely used because it can reduce the load capacity of the signal line and can simplify the decoding circuit as compared with the case where the predecoding method is not employed.
[0102]
FIG. 9A is a circuit diagram showing an address decoder using the predecoding scheme according to the fifth embodiment of the present invention, and FIG. 9B is a circuit diagram of the predecoding circuit.
[0103]
First, as shown in FIG. 9A, the address signals bADD2 and bADD3 are transmitted to the address signal line 5. The address signal line 5 is divided into a first part 5A and a second part 5B, and a repeater 4 is provided between the first part 5A and the second part 5B. An example of the repeater 4 is an inverter, which inverts the logic of the address signals bADD2 and bADD3 transmitted to the first part 5A and transmits it to the second part 5B.
[0104]
A first address signal processing circuit 60A is connected to the first portion 5A, and a second address signal processing circuit 60B is connected to the second portion 5B.
[0105]
The first address signal processing circuit 60A includes a predecode circuit group 61A (61-0, 61-1) and a decode circuit group 62A (62-0 to 62-7) arranged in the vicinity thereof. The predecode circuit group 61A predecodes the address signals bADD2 and bADD3 and outputs predecode signals XB0 and XB1. The decode circuit group 62A decodes the predecode signals XB0 and XB1 and the predecode signals XA0 to XA3 transmitted to the predecode signal line group 63, and outputs decode outputs R0 to R7. Predecode signals XA0 to XA3 are obtained by predecoding address signals ADD0 and ADD1 by a predecode circuit shown in FIG. 9B. The predecode signal line group 63 is arranged in parallel with the address signal line 5.
[0106]
The second address signal processing circuit 60B includes a predecode circuit group 61B (61-2, 61-3) and a decode circuit group 62B (62-8 to 62-15) arranged in the vicinity thereof. The predecode circuit group 61B predecodes signals having the same phase as the address signals ADD2 and ADD3 transmitted to the second portion 5B, and outputs predecode signals XB3 and XB4. The decode circuit group 62B decodes the predecode signals XB3 and XB4 and the predecode signals XA0 to XA3 transmitted to the predecode signal line group 63, and outputs decode outputs R8 to R15. FIG. 9C shows the relationship between the address signals ADD <0: 3> and bADD <0: 3> and the predecode signals XA <0: 3> 0-3 and XB <0: 3>.
[0107]
According to the address decoder according to the fifth embodiment, the load capacity of the signal line can be reduced as compared with the case where the address signal is directly input to the decoder, as in the predecoding method. Further, the address signal line 5 can be reduced in load capacity by providing the repeater 4.
[0108]
Further, when the 4-bit address signal ADD <0: 3> is decoded, the number of address signal lines arranged in parallel to each other is eight. This does not change even when the predecoding method shown in FIG. 8 is used. However, in the fifth embodiment, there are four predecode signal lines 63 and two address signal lines 5 for a total of six, and the number of signal lines arranged in parallel to each other can be reduced. As a result, an increase in chip area can be suppressed.
[0109]
Further, as shown in FIG. 9A, the circuit of the first address signal processing circuit 60A and the circuit of the first address signal processing circuit 60B are the same circuits.
[0110]
That is, when the circuit of the first address signal processing circuit 60A and the circuit of the first address signal processing circuit 60B are formed on the integrated circuit chip, they can be formed with the same circuit pattern. This contributes to uniform circuit patterns. Uniform circuit patterns are also useful for high integration.
[0111]
Next explained is a modification of the fifth embodiment of the invention.
[0112]
FIG. 10 is a circuit diagram showing an address decoder according to a modification of the fifth embodiment of the present invention.
[0113]
As shown in FIG. 10, when the decode circuit 62 (62-0 to 62-3) is, for example, a NAND circuit, the NMOS 64 receiving the predecode signal XB <0: 3> can be shared with each other. . In this case, the load on the predecode circuit 61 (61-0 to 61-3) can be reduced, and the number of NMOSs can be reduced, so that the effect of reducing the area of the decode circuit 62 can be obtained.
[0114]
In the fifth embodiment, an address decoder using a CMOS NAND circuit is illustrated, but a decoder using a CMOS NOR circuit or a dynamic decoder controlled by a precharge signal may be used.
[0115]
As an address decoder to which the fifth embodiment is applied, for example, a row decoder or a column decoder is preferable.
[0116]
In addition, the circuits shown in FIGS. 9 and 10 can correspond to both the row decoder and the column decoder, or a part thereof.
[0117]
[Sixth Embodiment]
FIG. 11 is a circuit diagram showing an address decoder using a predecoding scheme according to the sixth embodiment of the present invention.
[0118]
Hereinafter, the sixth embodiment will be described with reference to FIG. 11, taking as an example a decoding method in a block composed of 64 sets of unit regions R <0:63>.
[0119]
As shown in FIG. 11, the decoders 70 (70-0 to 70-3) grouped in 16 sets are predecoded signals XA <0: 3>, XB <0: 3>, XC <0: 3>. And 64 sets of unit areas R <0:63> are decoded.
[0120]
Predecode signal XB <0: 3> is generated from address signal bADD <2: 3>. bADD <2: 3> is gated by the NOR circuit 71 (71-0 to 71-3) and inverted and amplified by the signal bBLKSEL for enabling the block shown in FIG. It is converted into a signal in phase with the signal ADD <2: 3>.
[0121]
The load capacity of the signal line can be reduced also by receiving the address signal bADD <2: 3> at the gate and inverting and amplifying the address signal bADD <2: 3> into the signal lines 5A ′ and 5B ′ that are actually used for decoding control. it can. Therefore, it is possible to increase the speed of decoding control.
[0122]
Further, even if the address signal bADD <2: 3> is supplied to the global wiring 72 that is also used for other blocks similar to those in FIG. The capacitances 73A and 73B and the wiring capacitance are separated. Therefore, the load capacity of the global wiring 72 can also be kept small.
[0123]
Predecode signal XC <0: 3> is used in units of 16 sets. This is very similar to the fifth embodiment except that the address signal bADD <4: 5> is supplied to the global wiring 74 that is not inverted in the block shown in FIG. That is.
[0124]
For the unit region R <0:31> shown in FIG. 11, the address signal bADD <4: 5> is a local inversion circuit from the global wiring 74. In this circuit example, the NOR circuit 75 (75-0, 75- Is supplied to the predecode circuit 76A via 1). Predecode circuit 76A outputs a predecode signal XC <0: 1>.
[0125]
Further, the address signal bADD <4: 5> is directly supplied from the global wiring 74 to the predecode circuit 76B for the unit region R <32:63> shown in FIG. Predecode circuit 76B outputs predecode signal XC <2: 3>.
[0126]
Even in such a system, the capacitance of the decoder 70 is separated from the global wiring 74 by the NOR circuit 75 and the predecode circuit 76B. Therefore, the load capacity of the global wiring 74 can also be kept small.
[0127]
Further, the signal bBLKSEL for enabling the block shown in FIG. 11 is input to the NOR circuit 71 (71-0 to 71-3), and the address signal bADD <2: 5> is gated by the signal bBLKSEL.
[0128]
According to such a configuration, it is possible to reduce unnecessary current consumption. Further, if the method used in the predecode signal XC <0: 3> is used, the address signal bADD <4: 5> If is reset, the predecode signal XC <0: 3> can always be reset.
[0129]
Also in the examples as shown in FIGS. 9 and 10, unnecessary current consumption can be reduced as described above if the repeater 4 is controlled by the signal bBLKSEL for enabling the block.
[0130]
[Seventh Embodiment]
FIG. 12 is a circuit diagram showing an address decoder using a predecode system according to the seventh embodiment of the present invention. Hereinafter, the seventh embodiment will be described with reference to FIG. 12, taking as an example a decoding method in a block composed of 16 sets of unit regions R <0:15>.
[0131]
As shown in FIG. 12, in the seventh embodiment, the address signal line group 5 is divided into at least three first portions 5A, second portions 5B, and third portions 5C. A repeater group 80-1 including a plurality of in-phase repeaters is provided between the first portion 5A and the second portion 5B. In this circuit example, the in-phase repeaters constituting the repeater group 80-1 are each a three-input AND circuit, a signal obtained by inverting the highest address signal ADD3, an enable signal BLKSEL, and an address signal ADD. Any one of <0: 2> is input. When the enable signal BLKSEL is at the “HIGH” level, the repeater group 80-1 takes an AND logic of the signal obtained by inverting the address signal ADD3 and the address signal ADD <0: 2> and transmits it to the second portion 5B. .
[0132]
A repeater group 80-2 including a plurality of in-phase repeaters is provided between the second portion 5B and the second portion 5C. In this circuit example, the in-phase repeaters constituting the repeater group 80-1 are each a three-input AND circuit, and the most significant address signal ADD3, enable signal BLKSEL, and repeater group 80-1 Any one of the three outputs is input. The repeater group 80-2 takes the AND logic of the address signal ADD3 and any one of the three outputs from the repeater group 80-1 when the enable signal BLKSEL is at "HIGH" level, and the third part Tell 5C.
[0133]
A decode circuit group 81A (81-0 to 81-7) is connected to the second portion 5B. The decode circuit group 81A decodes a signal transmitted to the second portion 5B and selects one of the unit regions R <0: 7>.
[0134]
A decode circuit group 81B (81-8 to 81-15) is connected to the third portion 5C. The circuit configuration of the decode circuit group 81B is the same as that of the decode circuit group 81A. The decode circuit group 81B decodes the signal transmitted to the third portion 5C and selects any one of the unit regions R <8:15>.
[0135]
The seventh embodiment has a plurality of in-phase repeater groups 80 (80-1 and 80-2) instead of the type that inverts signals as in the past, and configures these repeater groups 80. Each repeater is controlled by the most significant address signal used for decoding and its complementary signal.
[0136]
When 16 sets of unit areas R <0:15> are decoded with a 4-bit signal of the address signal ADD <0: 3>, the following address assignment is conceivable.
[0137]
[Table 1]

[0138]
As can be seen from Table 1, the most significant address signal ADD3 has the same value in the unit region R <0: 7> or the unit region R <8:15>. In the unit region R <0: 7> and the unit region R <8:15>, the decoding method using the address signal ADD <0: 2> is exactly the same.
[0139]
Therefore, when the repeater groups 80-1 and 80-2 are respectively inserted between the unit region R <7> and the unit region R <8> and immediately before the unit region R <0>, these relays are connected. The instrument groups 80-1 and 80-2 are controlled by the address signal ADD3 and its complementary signal, respectively. As a result, the number of signal lines can be reduced, and the number of signals input to the decode circuits 81-0 to 81-15 constituting the decode circuit groups 81A and 81B can be reduced.
[0140]
For example, in the example shown in FIG. 7, the number of signal lines required to decode the 4-bit address signal ADD <0: 3> is eight, but in the seventh embodiment, a BLKSEL line is inserted. Can be reduced to five.
[0141]
Compared with the example of the predecoding method shown in FIG. 8, not only the number of wirings can be reduced, but also the number of signals input to the decoding circuit 81 can be reduced. Therefore, it is advantageous from the viewpoint of chip area and operation speed.
[0142]
In the case of the circuit configuration shown in FIG. 12, even if the signal BLKSEL is deactivated, for example, the unit region R <0> is selected if at least the address signals ADD <0: 3> are all at the “LOW” level. It becomes a state. In order to improve this, for example, the decode circuits constituting the decode circuit group 81 may be latched.
[0143]
In the above-described inventions according to the first to seventh embodiments, a signal line with a heavy load capacity is divided into a plurality of parts by inserting a repeater, and the circuit configuration using the signal line as an input is divided. By arranging each signal line to operate in reverse phase, the load capacity of the address signal can be reduced without increasing the number of gate stages for operating the circuit including the repeater. As a result, it is possible to suppress a decrease in operating speed and at the same time suppress an increase in chip area.
[0144]
Further, in the comparison circuit constituting the relief circuit 2, the address signal is received by the inverter, and the signal is output as it is or inverted by the fuse information, thereby reducing the load capacity of the address signal line. be able to. As a result, it is possible to suppress a decrease in operating speed due to an increase in the degree of integration of DRAMs and at the same time suppress an increase in chip area.
[0145]
[Eighth Embodiment]
Currently, a commonly used redundancy technology method uses a plurality of rows or columns of cell arrays as cell array units for relief, and a defective cell array unit as a result of a test is spared of the same size. This is a replacement method using elements (redundant arrays).
[0146]
In order to store the address information of the defective cell array unit, it is necessary to use a nonvolatile storage element, and a fuse is usually used. Since the address information is composed of a plurality of bits, a fuse set including a plurality of fuses corresponding to the plurality of bits is a unit of redundancy.
[0147]
Normally, a spare element and a fuse set are in one-to-one correspondence, and the same number of fuse sets as spare elements are provided in a chip. When a spare element is used, the fuse in the corresponding fuse set is cut according to the address.
[0148]
In recent years, in order to increase the operation speed, various types of memory chips have been proposed, such as a Rambus DRAM, which has a plurality of banks inside the chip and can take a state in which these banks are activated simultaneously. Such a memory chip cannot have a spare element that covers a memory cell beyond a bank, so a spare element concentrated arrangement method (1995, VLSI symp. , P108) cannot be adopted, and it is necessary to prepare spare elements for each bank independently. At this time, the method in which the spare element and the fuse set are in a one-to-one correspondence requires a huge number of fuse sets. In other words, if the spare element can cover only a narrow range due to restrictions on the number of banks, high-speed operation, etc., a spare element must be provided for each narrow cell array region in order to cope with the uneven distribution of defects. I must. When this is considered as a whole chip, spare elements that greatly exceed the average number of defects per chip are incorporated into the chip, which deteriorates the area efficiency. Further, in the system in which the spare elements and the fuse sets are made to correspond one-to-one, the number of fuse sets increases as the number of spare elements increases.
[0149]
As a system for dealing with this problem, a system that flexibly corresponds a spare element and a fuse set has been proposed. Although the basic idea is to increase the number of spare elements, there is no choice but to reduce the number of fuse sets built into the chip without reducing the yield by destroying the one-to-one correspondence with fuse sets. Can be made possible. Hereinafter, this method is referred to as flexible mapping redundancy.
[0150]
(Reference: ISSC '99 "A 1.6GB / s DRAM with Flexible Mapping Redundancy Technique and Additional Refresh Scheme") In flexible mapping redundancy, a spare element (hereinafter referred to as a fuse set) is stored in a storage circuit (hereinafter referred to as a fuse set) for storing defective addresses. Mapping information with the redundant array) is also stored, and information regarding which redundant array the fuse set is associated with is retained. As a result, the number of fuses per fuse set is increased by this mapping information compared to the conventional one-to-one correspondence between redundant arrays and fuse sets, but it is suitable for the average number of defects per chip. Therefore, the number of fuse sets can be reduced compared to the one-to-one correspondence described above, and the total number of fuses (= number of fuse sets × number of fuses per fuse set) Has the advantage of reducing. Accordingly, even when defects are unevenly distributed, it is possible to improve the area efficiency of the redundancy circuit by reducing the number of fuses necessary for the defect relief while enabling the defect relief with a high degree of freedom.
[0151]
The eighth embodiment relates to such flexible mapping redundancy.
[0152]
Prior to the description of the eighth embodiment, flexible mapping redundancy will be described as a reference example.
[0153]
FIG. 13 is a diagram showing a memory cell array of the semiconductor memory device according to the first reference example of the eighth embodiment of the present invention.
[0154]
First, as shown in FIG. 13, the memory cell array 100 is divided into a matrix-like subarray A (m, n) of m columns × n rows. In this example, the memory cell array is divided into a total of 4 × 16 = 64 subarrays, where m = 4 along the row direction and n = 16 along the column direction. The sub-array is also a range of repair units that are repaired by the redundant array.
[0155]
Four subarrays A (0, n) to A (4, n) arranged in the row direction constitute one bank, and in this example, 16 banks BANKn (n = 0 to 15) are provided. Has been placed. Similarly, 16 subarrays A (m, 0) to A (m, 15) arranged in the column direction constitute one segment, and in this example, four segments SEGMENTm (m = 0 to 3). ) Is arranged. When a row address (ROW ADD) and a column address (COLUMN ADD) supplied from the outside via an address buffer are input, they are decoded by a row decoder (RD) and a column decoder (CD), respectively. A word line (WL) and a column selection line (CSL) are selected, and operations such as writing and reading can be performed on a memory cell designated by the address.
[0156]
As shown in FIG. 13, redundant arrays RA (m, n); m = 0 to 7, and n = 0 to 15 are arranged as redundant cell arrays at both ends along the row direction of each subarray A (m, n). ing. The total number of redundant arrays RA (m, n) is 8 × 16 = 128. The redundant array RA (m, n) is selected by spare column selection lines (SCSL0 to SCSL7). Spare column selection lines (SCSL0 to SCSL7) are arranged in parallel with the column selection line (CSL) and are shared for all banks in the same segment. Such spare column selection lines (SCSL0 to SCSL7) are driven by a spare column selection line driver (SCD).
[0157]
When a memory cell in the sub-array A (m, n) is defective, the redundant array RA (m, n) is replaced by replacing the column selection line CSL corresponding to the cell array unit including the defective memory cell with the spare column selection line SCSL. n) is replaced. Control information regarding which address is to be replaced is programmed in the nonvolatile memory circuit. A nonvolatile memory circuit generally uses a fuse. In this example, 14 fuse sets (FA0 to FA13) are prepared as nonvolatile memory circuits, and are arranged in an array along the column decoder and the spare column drive circuit (hereinafter, for convenience, the fuse set). Called an array). The fuse set (FA0 to FA13) is a redundancy determination circuit that determines whether or not to replace a defective cell. One fuse set designates one spare column selection line SCSL.
[0158]
FIG. 14 is a diagram showing a fuse set array according to a first reference example of the eighth embodiment of the present invention. Note that points A to P in FIG. 14 are connected to points A to P in FIG. 13, respectively.
[0159]
As shown in FIGS. 13 and 14, in the flexible mapping redundancy, each of the fuse sets (FA0 to FA13) is flexibly associated with the redundant array RA (m, n). In this example, each of the 14 fuse sets (FA0 to FA13) can correspond to any of the 128 redundant arrays RA (m, n). For this reason, the outputs of the fuse sets (FA0 to FA13) are wired or connected to replacement control signal lines RDHIT0 to RDHIT7 for determining whether or not to perform redundancy replacement. The potential of the replacement control signal line RDHITn is normally “LOW” level, but becomes “HIGH” level when the nth spare column selection line SCSLn is driven. In this case, the column selection line (CSL) of the normal cell array corresponding to the nth replacement control signal line RDHITn is not driven.
[0160]
FIG. 15 is a circuit diagram showing a circuit example of a fuse set.
[0161]
As shown in FIG. 15, the fuse set includes a defective address designation fuse circuit 201, an address comparison circuit 202, a fuse information coincidence detection circuit 203, an enable fuse circuit 204, a decoder 205, and a mapping fuse circuit 206.
[0162]
The defective address designating fuse circuit 201 stores the defective address information corresponding to the state of the fuse (cut or not cut). The output of the fuse circuit 201 according to this circuit example is “HIGH” level when the fuse is cut, and “LOW” level when the fuse is not cut. The fuses FS (FS (1) to FS (11)) are provided by the number of addresses indicating the repair unit. In this example, a total of 11 addresses are provided corresponding to addresses a0 to a6 for designating column selection lines (CSL) and addresses b0 to b3 for designating banks. The fuse circuit 201 outputs a total of 11 defective address information for each of the fuses FS (1) to FS (11). Each output of the fuse circuit 201 is input to an address comparison circuit (CMP) 202 (202-a0 to 202-a6, 202-b0 to 202-b3).
[0163]
The address comparison circuit 202 compares the output of the fuse circuit 201 with the input addresses (a0 to a6, b0 to b3). In the address comparison circuit 202 according to this circuit example, when the input address information coincides with the defective address information, the output becomes “HIGH” level. The output of the comparison circuit 202 is input to the fuse information coincidence detection circuit (AND) 203.
[0164]
The fuse information coincidence detection circuit 203 is an AND circuit, for example, and is enabled / disabled by the output of the enable fuse circuit 204. The fuse FS (12) of the enable fuse circuit 204 according to this circuit example is cut when the fuse information coincidence detection circuit 203 is enabled. When the fuse FS (12) is cut, the output of the fuse circuit 204 becomes “HIGH” level, and the fuse information coincidence detection circuit 203 is enabled. On the other hand, when the fuse FS (12) is not cut, the output of the fuse circuit 204 becomes “LOW” level, and the fuse information coincidence detection circuit 203 is disabled.
[0165]
The fuse information coincidence detection circuit 203 sets the output to the “HIGH” level when the output of the address comparison circuit 202 and the output of the enable fuse circuit 204 are all at the “HIGH” level. The output of the fuse information coincidence detection circuit 203 is input to the decoder 205.
[0166]
The decoder 205 is enabled when the output of the fuse information coincidence detection circuit 203 is at “HIGH” level, decodes the mapping information from the mapping fuse circuit 206, and sets one of the replacement control signal lines RDHIT0 to RDHIT7 to “HIGH”. Level.
[0167]
The mapping fuse circuit 206 stores correspondence information between the fuse set and the redundant cell array, that is, mapping information, corresponding to the state of the fuse (cut or not cut). The mapping information in this circuit example is information indicating which of the eight spare column selection lines SCSL corresponds to the fuse set, and combinations of the states of the three fuses FS (13) to FS (15). That is, it is memorized by eight combinations.
[0168]
With flexible mapping redundancy, you can certainly reduce the number of fuse sets. However, since the correspondence between the fuse set and the redundant array is flexible, when the degree of integration of the chip is increased and the number of fuse sets is increased accordingly, one replacement control signal line (RDHITn) is increased. Each fuse set will be connected. As a result, the junction capacitance added to one replacement control signal line (RDHITn) increases by the output transistor at the final stage of the increased fuse set, and the load capacitance increases. This causes a delay in the signal propagated to the replacement control signal line (RDHITn). In general, the path of the replacement control signal line (RDHITn) is a critical path, which hinders speeding up of the operation.
[0169]
FIG. 16 is a diagram showing a memory cell array having a 32-bank configuration according to the second reference example, and FIG. 17 is a diagram showing the fuse cell array. Note that points A to P in FIG. 16 are connected to points A to P in FIG. 17, respectively.
[0170]
For example, as shown in FIGS. 16 and 17, when the integration density is increased from the 16-bank configuration to the 32-bank configuration, 28 fuse sets (FA0 to FA13, FB0 to FB13) are provided so as not to reduce the repair efficiency. Is provided. In this case, the junction capacitance added to one replacement control signal line (RDHITn) is twice that of the 14 fuse sets (FA0 to FA13) shown in FIG. The effect of signal delay is not negligible.
[0171]
Further, when the length L-FSA of the fuse set array including 14 fuse sets (FA0 to FA13) is substantially equal to the length L-MCA along the row direction of the memory cell array 100, 28 fuse sets are provided. In order to provide, as shown in FIG. 17, 14 fuse set arrays must be arranged in two rows.
[0172]
Considering the area penalty of the fuse set placement portion in the chip, the area of the fuse set placement portion is determined by the number of wiring layers and the pitch between the wiring layers, rather than the area of the underlying transistor formation portion.
[0173]
As shown in FIG. 17, when the fuse set array is arranged in two rows in the fuse set arrangement section, eight replacement control signal lines (RDHIT0 to RDHIT7) are folded back to the fuse set arrangement section, and 16 lines are arranged. Be placed. Thus, an increase in the wiring layers arranged in the fuse set arrangement part, that is, the replacement control signal lines (RDHIT0 to RDHIT7) directly leads to an increase in the area of the fuse set arrangement part, and hence an increase in the area of the chip.
[0174]
In view of the above situation, an object of the eighth embodiment is to reduce the load capacity of a replacement control signal line while satisfying the requirement for high integration in a semiconductor memory device using flexible mapping redundancy.
[0175]
FIG. 18 is a diagram showing a fuse set array provided in a semiconductor memory device according to the eighth embodiment of the present invention. It is assumed that points A to P in FIG. 18 are connected to points A to P in FIG. 16, respectively.
[0176]
As shown in FIG. 18, eight replacement control signal lines RDHIT0 to RDHIT7 are provided corresponding to the eight spare selection line drivers (SCD) shown in FIG. Replacement control information for driving each corresponding spare selection line driver (SCD) is transmitted to replacement control signal lines RDHIT0 to RDHIT7. The replacement control signal lines RDHIT0 and RDHIT1 correspond to SEGMENT0 among the four segments SEGMENT0 to SEGMENT3. Similarly, replacement control signal lines RDHIT2 and RDHIT3 correspond to SEGMENT1, replacement control signal lines RDHIT4 and RDHIT5 correspond to SEGMENT2, and replacement control signal lines RDHIT6 and RDHIT7 correspond to SEGMENT3. The replacement control information is output from the fuse sets FA0 to FA13 or FB0 to FB13.
[0177]
In the eighth embodiment, the fuse sets FA0 to FA13 are provided corresponding to the four replacement control signal lines RDHIT0, RDHIT2, RDHIT4, and RDHIT6 among the eight replacement control signal lines RDHIT0 to RDHIT7. The sets FB0 to FB13 are provided corresponding to the other four replacement control signal lines RDHIT1, RDHIT3, RDHIT5, and RDHIT7.
[0178]
FIG. 19 is a circuit diagram illustrating a circuit example of the fuse set (FA0 to FA13).
[0179]
As shown in FIG. 19, the fuse set has a defective address designation fuse circuit 201, an address comparison circuit 202, a fuse information coincidence detection circuit 203, an enable fuse circuit 204, and a decoder 205, as in the reference example shown in FIG. , And a mapping fuse circuit 206.
[0180]
The fuse set shown in FIG. 19 is different from the fuse set shown in FIG. 15 as follows.
[0181]
First, as the number of banks increases from “16” to “32”, one address b4 for designating a bank is added. Thus, a total of 12 fuses FS of the defective address designating fuse circuit 201 correspond to the addresses a0 to a6 for designating the column selection line (CSL) and the addresses b0 to b4 for designating the banks. (FS1 to FS12) are provided.
[0182]
Second, the mapping fuse circuit 206 may designate one of the four replacement control signal lines. For this reason, the number of fuses FS in the mapping fuse circuit 206 is reduced to one (FS14, FS15).
[0183]
According to such an eighth embodiment, compared to the fuse set according to the reference example shown in FIG. 17, two spare column selection lines SCSL in the same segment (relief unit), for example, the spare in FIG. A plurality of outputs from the fuse sets connected to the replacement control signal lines RDHIT0 and RDHIT1 for controlling the column selection lines SCSL0 and SCSL1 are independent from each other and are not wired or connected.
[0184]
On the other hand, in different segments (relief units), as in the flexible mapping redundancy of the reference example, the corresponding fuse set (FA0 to FA13, RDHIT1, RDHIT3, RDHIT5 for RDHIT0, RDHIT2, RDHIT4, and RDHIT6 in FIG. 18). The outputs of FB0 to FB13) are wired or connected to RDHIT7. As a result, as can be seen from a comparison between FIG. 17 and FIG. 18, the number of fuse sets connected to one replacement control signal line can be reduced within a range where the repair efficiency is not lowered. This example is effective when the probability that 16 banks or more must be relieved by each of the two spare column selection lines is extremely low. Accordingly, the junction capacitance of the output transistor at the final stage of the fuse set, which is a parasitic capacitance added to one replacement control signal line, is reduced, and the delay of the replacement control information in the replacement control signal line that forms part of the critical path is reduced. Can be suppressed.
[0185]
Further, as shown in FIG. 18, the number of wiring layers arranged in the fuse set arrangement portion, that is, the number of replacement control signal lines can be reduced to eight, half of the reference example shown in FIG. For this reason, the area of the fuse set arrangement portion regulated by the pitch of the replacement control signal line can be reduced by that amount, and an increase in chip area is effectively suppressed.
[0186]
Further, in the reference example shown in FIG. 17, the mapping fuse circuit needs to designate any one of the eight replacement control signal lines. In the eighth embodiment, four replacement control signal lines are used. You only need to specify one of them. For this reason, there is also an advantage that the number of fuses in the mapping fuse circuit can be reduced.
[0187]
[Ninth Embodiment]
FIG. 20 is a diagram showing a fuse set array included in a semiconductor memory device according to the ninth embodiment of the present invention. Note that points A to P in FIG. 20 are connected to points A to P in FIG. 16, respectively.
[0188]
As shown in FIG. 20, similarly to the eighth embodiment, 28 fuses of 28 fuse sets FA0 to FA13 and FB0 to FB13 are provided.
[0189]
The rows of fuse sets FA0 to FA13 are arranged in parallel with the rows of fuse sets FB0 to FB13. Four wiring layers are arranged between these columns. Each of the four wiring layers is separated in the middle of these columns (between fuse sets FA6 and FA7 and between FB6 and FB7 in this example). The four wiring layers arranged between the fuse sets FA0 to FA6 and the fuse sets FB0 to FB6 constitute replacement control signal lines RDHIT0 to RDHIT3, respectively. Also, the four wiring layers arranged between the fuse sets FA7 to FA13 and the fuse sets FB7 to FB13 constitute replacement control signal lines RDHIT4 to RDHIT7, respectively. The fuse sets FA0 to FA6 and FB0 to FB6 are respectively connected to replacement control signal lines RDHIT0 to RDHIT3, and the fuse sets FA7 to FA13, FB7 to FB13 are respectively connected to replacement control signal lines RDHIT4 to RDHIT7.
[0190]
According to the ninth embodiment, as in the eighth embodiment, the number of fuse sets connected to one replacement control signal line (RDHITn) is reduced. Thereby, the junction capacity added to the replacement control signal line (RDHITn) is reduced, and the load capacity can be reduced. Therefore, it is possible to suppress the delay of replacement control information in the replacement control signal line.
[0191]
In the ninth embodiment, as shown in FIG. 20, eight replacement control signal lines RDHIT0 to RDHIT7 can be arranged in a space for four wiring layers. As described above, the number of replacement control signal lines arranged in the fuse set arrangement part can be substantially reduced to four, so that an increase in the area of the fuse set arrangement part is further easily suppressed.
[0192]
However, in the ninth embodiment, since the number of fuse sets corresponding to one segment is reduced from 28 in the eighth embodiment to 14, the relief efficiency is slightly lowered as compared with the eighth embodiment. However, in the implementation, the eighth embodiment may be selected when increasing the relief efficiency and the ninth embodiment is selected when the suppression of the increase in the chip area is more strongly required. In any case, since the junction capacity added to one replacement control signal line is reduced, the load capacity is reduced.
[0193]
[Tenth embodiment]
FIG. 21 is a diagram showing a memory cell array of a semiconductor memory device according to the tenth embodiment of the present invention, and FIG. 22 is a diagram showing the fuse cell array. It is assumed that points A to P in FIG. 21 are connected to points A to P in FIG. 22, respectively.
[0194]
As shown in FIG. 21, in the tenth embodiment, three redundant arrays RA (m, n) are provided for one subarray A (m, n). That is, two at one end along the row direction of each subarray A (m, n), one at the other end, and redundant array RA (m, n) as a redundant cell array; m = 0 to 11, n = 0 to 31 Is arranged. The total number of redundant arrays RA (m, n) is 12 × 32 = 384. The redundant array RA (m, n) is selected by spare column selection lines (SCSL0 to SCSL11).
[0195]
As shown in FIG. 22, the fuse set array is provided with 12 replacement control signal lines RDHIT0 to RDHIT11 corresponding to the 12 spare selection line drivers (SCD) shown in FIG. Yes. Replacement control information for driving each corresponding spare selection line driver (SCD) is transmitted to replacement control signal lines RDHIT0 to RDHIT11.
[0196]
The replacement control signal lines RDHIT0 to RDHIT2 correspond to SEGMENT0 among the four segments SEGMENT0 to SEGMENT3. Similarly, replacement control signal lines RDHIT3 to RDHIT5 correspond to SEGMENT1, replacement control signal lines RDHIT6 to RDHIT8 correspond to SEGMENT2, and replacement control signal lines RDHIT9 to RDHIT11 correspond to SEGMENT3. The replacement control information is output from the fuse sets FA0 to FA13 or FB0 to FB13.
[0197]
In the tenth embodiment, the fuse sets FA0 to FA13 correspond to six replacement control signal lines RDHIT0, RDHIT2, RDHIT4, RDHIT6, RDHIT8, and RDHIT10 out of twelve replacement control signal lines RDHIT0 to RDHIT11. Is provided. The fuse sets FB0 to FB13 are provided corresponding to the other six replacement control signal lines RDHIT1, RDHIT3, RDHIT5, RDHIT7, RDHIT9, and RDHIT11.
[0198]
In the tenth embodiment as well, as in the eighth and ninth embodiments, the number of fuse sets connected to one replacement control signal line can be reduced, so that the load capacity of the replacement control signal line can be reduced. Can be reduced.
[0199]
Further, when the plurality of replacement control signal lines are respectively divided and corresponded to the plurality of fuse sets, it is preferable to divide and correspond to the same number.
[0200]
In other words, when there are eight replacement control signal lines, the replacement control signal lines are divided into four as in the eighth and ninth embodiments, each corresponding to 14 fuse sets. Further, when there are 12 replacement control signal lines, it is divided into 6 pieces as in the tenth embodiment, and each of them corresponds to 14 fuse sets. By dividing into equal numbers in this way, it is possible to suppress a reduction in repair efficiency.
[0201]
For example, when the 12 replacement control signals are divided into 8 and 4, and each of them corresponds to 14 fuse sets, there is of course an effect of reducing the load capacity of the replacement control signal line. On the other hand, that is, it is reduced to 14 fuse sets corresponding to 8 replacement control signals. Such a situation can be solved by making six fuses correspond to 14 fuse sets. Therefore, it is preferable that the replacement control signal lines are divided into equal numbers.
[0202]
[Eleventh embodiment]
As described above, based on the basic configuration described in the eighth to tenth embodiments, the number of fuse sets, the method of dividing the replacement control signal line, the number of redundant arrays in the same segment (or the redundant array for one subarray) For example, various variations are possible. One example will be described as an eleventh embodiment.
[0203]
FIG. 23 is a diagram showing a memory cell array of a semiconductor memory device according to the eleventh embodiment of the present invention, and FIG. 24 is a diagram showing the fuse cell array. Note that points A to P in FIG. 23 are connected to points A to P in FIG. 24, respectively.
[0204]
In the eleventh embodiment, the number of fuse sets is 56, the number of replacement control signal lines is divided into four, and the number of redundant arrays is four for one subarray A (m, n). is there.
[0205]
As shown in FIG. 23, in the eleventh embodiment, redundant arrays RA (m, n) as redundant cell arrays, two at each end along the row direction of each subarray A (m, n); m = 0 ˜15, n = 0˜31 are arranged. The total number of redundant arrays RA (m, n) is 16 × 32 = 512. The redundant array RA (m, n) is selected by spare column selection lines (SCSL0 to SCSL15).
[0206]
As shown in FIG. 24, the fuse set array is provided with 16 replacement control signal lines RDHIT0 to RDHIT15 corresponding to the 16 spare selection line drivers (SCD) shown in FIG. Yes. Replacement control information for driving each corresponding spare selection line driver (SCD) is transmitted to replacement control signal lines RDHIT0 to RDHIT15.
[0207]
The replacement control signal lines RDHIT0 to RDHIT3 correspond to SEGMENT0 among the four segments SEGMENT0 to SEGMENT3. Similarly, replacement control signal lines RDHIT4 to RDHIT7 correspond to SEGMENT1, replacement control signal lines RDHIT8 to RDHIT11 to SEGMENT2, and replacement control signal lines RDHIT12 to RDHIT15 to SEGMENT3. The replacement control information is output from fuse sets FA0 to FA13, FB0 to FB13, fuse sets FC0 to FC13, or fuse sets FD0 to FD13.
[0208]
In the tenth embodiment, the fuse sets FA0 to FA13 are provided corresponding to four replacement control signal lines RDHIT0, RDHIT4, RDHIT8, and RDHIT12 among the 16 replacement control signal lines RDHIT0 to RDHIT15. . The fuse sets FB0 to FB13 are provided corresponding to the other four replacement control signal lines RDHIT1, RDHIT5, RDHIT9, and RDHIT13. Further, the fuse sets FC0 to FC13 are provided corresponding to four other replacement control signal lines RDHIT2, RDHIT6, RDHIT10, and RDHIT14. The fuse sets FD0 to FD13 are provided corresponding to the remaining four replacement control signal lines RDHIT3, RDHIT7, RDHIT11, and RDHIT15.
[0209]
In the eleventh embodiment as well, as in the eighth to tenth embodiments, the number of fuse sets connected to one replacement control signal line can be reduced, so that the load capacity of the replacement control signal line can be reduced. Can be reduced.
[0210]
In addition to the eleventh embodiment, the number of fuse sets, the method of dividing the replacement control signal line, the number of redundant arrays in the same segment (or the number of redundant arrays for one subarray), etc. Variations are possible.
[0211]
Further, there may be a case where all redundant arrays in the same segment cannot be divided into fuse set rows that are not wired-or-connected to each other. In this case, it suffices to divide within a separable range or only a part of the separable range.
[0212]
The outputs from the fuse sets FA0 to FA13 connected to two SCSLs in the same segment, for example, the replacement control signal line RDHIT0 for controlling the spare column selection line SCSL0, are the replacement control signal lines for controlling the spare column selection line SCSL1. The outputs from the fuse sets FB <b> 0 to FB <b> 13 connected to the RDHIT <b> 1 are independent from each other and are not connected to the wired OR. However, the conceptually divided fuse sets FA0 to FA13 and FB0 to FB13 may be arranged in any manner in an actual chip. However, as an actual problem, as the integration density of the chip increases and the number of fuse sets increases, it becomes difficult to arrange the fuse sets in a line, and two or three rows as in the eighth to tenth embodiments, Or it is in the direction arrange | positioned along with 4 rows like 11th Embodiment.
[0213]
As described above, the eighth to eleventh embodiments are merely examples, and as a storage element of the defective address storage circuit, an element other than a fuse, such as a PROM cell, a storage element (antifuse) for storing a capacitor by dielectric breakdown, or the like. May be used.
[0214]
Further, as the fuse circuit, a circuit having another configuration may be used. In addition, in the embodiments, the fuse circuit is different in arrangement and number, and in the embodiments, it is represented by words such as bank and segment. However, it can also be applied to an array composed of the same thing conceptually. is there.
[0215]
In the eighth to eleventh embodiments, the method of replacing with a spare column selection line is exemplified. However, the present invention can be applied to a method of replacing with a spare word line.
[0216]
As described above, in the flexible mapping redundancy in which the redundant array and the fuse set are flexibly associated with each other, the replacement control signal RDHIT input to the driver that drives the redundant array usually has a plurality of outputs from each fuse set. Corresponding terminals are wired or connected to each other.
[0217]
On the other hand, according to the semiconductor memory devices according to the eighth to eleventh embodiments, in the plurality of redundant arrays within the same repair range, the replacement control signal RDHIT input to the driver that drives each redundant array. Thus, the plurality of fuse set rows are divided into fuse set rows in which output terminals from each fuse set are not wired-or connected. As a result, it is possible to increase the speed by reducing the parasitic capacitance with respect to the replacement control signal and to suppress the increase in the area of the fuse portion by reducing the number of wirings in the fuse portion without reducing the relief efficiency due to redundancy. be able to.
[0218]
【The invention's effect】
As described above, according to the present invention, it is possible to provide a semiconductor integrated circuit device capable of satisfying a demand for high integration while suppressing a decrease in operation speed due to high integration.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a schematic configuration of a semiconductor memory device according to a first embodiment of the present invention;
FIG. 2 is a block diagram illustrating a configuration example of a relief circuit.
3A is a circuit diagram showing an example of an address comparison circuit, FIG. 3B is an operation waveform diagram showing an example of an operation of the address comparison circuit, and FIG. 3C is a fuse (Fuse). ) Is a diagram showing the relationship between the state and output (FOUT).
FIGS. 4A and 4B are circuit diagrams each showing a circuit example of an address comparison circuit according to the second embodiment of the present invention.
FIG. 5 is a block diagram showing a schematic configuration of a semiconductor memory device according to a third embodiment of the present invention.
FIG. 6 is a block diagram showing a schematic configuration of a semiconductor memory device according to a fourth embodiment of the present invention.
FIG. 7 is a circuit diagram of a decoder that is directly decoded by an address signal.
8A is a circuit diagram of a decoder using a predecode method, FIG. 8B is a circuit diagram of a predecode circuit, and FIG. 8C is a relationship between input and output of the predecode circuit. FIG.
9A is a circuit diagram showing an address decoder using a predecoding method according to a fifth embodiment of the present invention, FIG. 9B is a circuit diagram of a predecoding circuit, and FIG. ) Is a diagram showing the relationship between the input and output of the predecode circuit.
FIG. 10 is a circuit diagram showing an address decoder according to a modification of the fifth embodiment of the present invention.
FIG. 11 is a circuit diagram showing an address decoder using a predecoding scheme according to a sixth embodiment of the present invention;
FIG. 12 is a circuit diagram showing an address decoder using a predecoding method according to a seventh embodiment of the present invention;
FIG. 13 is a view showing a memory cell array according to a first reference example of the eighth embodiment of the present invention;
FIG. 14 is a diagram showing a fuse set array according to a first reference example of the eighth embodiment of the present invention;
FIG. 15 is a circuit diagram showing an example of a circuit of a fuse set.
FIG. 16 is a view showing a memory cell array according to a second reference example of the eighth embodiment of the present invention;
FIG. 17 is a view showing a fuse set array according to a second reference example of the eighth embodiment of the present invention;
FIG. 18 is a view showing a fuse set array included in a semiconductor memory device according to an eighth embodiment of the present invention;
FIG. 19 is a circuit diagram showing a circuit example of a fuse set included in a semiconductor memory device according to an eighth embodiment of the present invention;
FIG. 20 is a view showing a fuse set array included in a semiconductor memory device according to a ninth embodiment of the present invention;
FIG. 21 is a view showing a fuse set array provided in a semiconductor memory device according to a tenth embodiment of the present invention;
FIG. 22 is a circuit diagram showing a circuit example of a fuse set included in a semiconductor memory device according to a tenth embodiment of the present invention;
FIG. 23 is a view showing a fuse set array included in a semiconductor memory device according to an eleventh embodiment of the present invention;
FIG. 24 is a circuit diagram showing a circuit example of a fuse set included in a semiconductor memory device according to an eleventh embodiment of the present invention;
[Explanation of symbols]
1 ... cell array,
2A, 2B ... relief circuit,
3 ... Address generation circuit,
4 ... Repeater,
5, 5A, 5B, 5C ... address signal lines,
10: Redundancy determination circuit,
11 ... Fuse circuit for enabling,
12: Address comparison circuit,
13: determination circuit,
14 ... Output circuit,
21 ... Fuse circuit for specifying a defective address,
22 ... Latch circuit,
23, 23A, 23B ... transfer circuit,
31 ... NMOS,
32 ... PMOS,
33, 34 ... Transfer gate,
35 ... Output node of the latch circuit 22,
36, 37A, 37B ... inverter,
38A, 38B ... Clocked inverter,
39A, 39B ... Transfer gate,
60A, 60B ... Address signal processing circuit,
61A, 61B ... Predecode circuit group,
62A, 62B ... decode circuit group,
63: Predecode signal line group,
64 ... Shared NMOS,
70: Decoder,
71 ... NOR circuit,
72 ... Global wiring,
73A, 73B ... Predecode circuit,
74 ... Global wiring,
75 ... NOR circuit,
76A, 76B ... Predecode circuit,
80 ... repeater group,
81A, 81B ... decode circuit group,
100: Memory cell array,
201 ... Fuse circuit for specifying a defective address,
202 ... Address comparison circuit,
203 ... fuse information coincidence detection circuit,
204... Fuse circuit for enabling,
205 ... Decoder,
206 A mapping fuse circuit.

Claims (11)

A first signal line group for transmitting predecoded information obtained by predecoding at least two bits of information;
A second signal line group for transmitting at least two bits of information parallel to the first signal line group and divided into at least two first and second parts;
Information that is provided between the first part of the second signal line group and the second part of the second signal line group and that transmits information transmitted to the first part by inverting its logic. A group of repeaters to be transmitted to part 2,
A first predecode circuit group for predecoding information transmitted to the first portion;
A second predecode circuit group having the same configuration as the first predecode circuit group and predecoding information transmitted to the second portion;
A first decode circuit group for decoding predecode information of the first predecode circuit and predecode information transmitted to the first signal line group;
A second decode circuit group that has the same configuration as the first decode circuit group and decodes predecode information of the second predecode circuit and predecode information transmitted to the first signal line group. A semiconductor integrated circuit device. The repeater group is activated when the first and second predecode circuit groups and the first and second decode circuit groups are selected, and the first and second predecode circuit groups, 2. The semiconductor integrated circuit device according to claim 1 , wherein the semiconductor integrated circuit device is deactivated when the first and second decoding circuit groups are not selected. Said first, second predecode circuit group, and the first, second decoding circuit group, any claims 1 and 2, characterized in that each of any of the row decoder, and a column decoder A semiconductor integrated circuit device according to claim 1. A group of signal lines, each of which is divided into at least three first parts, a second part, and a third part, and carries information of a plurality of bits;
A plurality of bits transmitted to the first part of the signal line group to the second part, and a first repeater group controlled by at least one bit of information;
A first decoding circuit group for decoding the information of the plurality of bits transmitted to the second portion of the signal line group;
The second repeater group controlled by at least one bit information complementary to the at least one bit information while transmitting the plurality of bits of information transmitted to the second portion of the signal line group to the third portion When,
A semiconductor integrated circuit comprising: a second decoding circuit group having the same configuration as the first decoding circuit group, wherein the second decoding circuit group decodes the information of the plurality of bits transmitted to the third portion of the signal line group apparatus. The first and second repeater groups are activated when the first and second decode circuit groups are selected, and the first and second predecode circuit groups and the first and second repeater groups are activated. 5. The semiconductor integrated circuit device according to claim 4 , wherein said semiconductor integrated circuit device is deactivated when said decode circuit group is not selected. It said first, second decoding circuit group, row decoder, and a column semiconductor integrated circuit device according to claims 4 and 5 any one, characterized in that each of any of the decoders. A cell array including a plurality of repair units, each of the plurality of repair units having a plurality of memory cells and spare cells disposed;
A plurality of spare selection lines provided for selecting any spare cell among the plurality of spare cells in each of the plurality of repair units ;
A spare selection line driver that is provided corresponding to each of the plurality of spare selection lines in each of the plurality of repair units and drives each corresponding spare selection line;
A replacement control signal line group provided corresponding to each of the spare selection line drivers and transmitting replacement control information for driving each corresponding spare selection line driver;
A first redundancy judgment circuit group comprising a plurality of redundancy judgment circuits provided corresponding to a part of the substitution control signal line groups among the substitution control signal line groups;
Wherein among the substituent control signal line group, and a second redundancy determination circuit group including a plurality of redundancy judgment circuit provided corresponding to the replacement control signal lines other than the replacement control signal line of said portion ,
Each of the plurality of redundancy judgment circuits detects a defective address designation program circuit in which defective address information of the cell array is programmed, and detects whether or not the defective address information programmed in the defective address information program circuit matches the input address information The matching control circuit, the mapping program circuit in which the correspondence information with the replacement control signal line group is programmed, the replacement control based on the detection result of the match detection circuit and the correspondence information of the mapping program circuit An output circuit that outputs the replacement control information to a signal line,
Of the repair units, the replacement control signal line for controlling the spare selection line in the same repair unit does not connect the output of the output circuit of the redundancy determination circuit by wired OR connection,
Only the replacement control signal line for controlling the spare selection line in a different repair unit among the repair units is wired or connected to the output of the output circuit of the redundancy judgment circuit group . The cell array is composed of a plurality of subarrays arranged in a matrix,
8. The semiconductor integrated circuit device according to claim 7 , wherein the spare selection line is shared by subarrays along a row direction or a column direction. 8. The semiconductor integrated circuit device according to claim 7 , wherein the number of replacement control signal lines other than the partial replacement control signal line is equal to the number of the partial replacement control signal lines. It said first redundancy determination circuit group, a semiconductor integrated circuit device according to any one claims 7 to 9, characterized in that it is arranged in parallel with said second redundancy determination circuit group. The first decoding circuit group includes:
A first plurality of decode circuits including a transistor that receives predecode information transmitted to the first signal line group, and a transistor that receives predecode information of the first predecode circuit;
The second decoding circuit group includes:
A second plurality of decode circuits including a transistor that receives predecode information transmitted to the first signal line group, and a transistor that receives predecode information of the second predecode circuit;
The transistor receiving predecode information of the first predecode circuit is shared by the first plurality of decode circuits,
2. The semiconductor integrated circuit device according to claim 1 , wherein a transistor receiving predecode information of the second predecode circuit is shared by the second plurality of decode circuits .

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