JPH11162199A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the time required to gather information for judging whether a flash memory is acceptable or not. SOLUTION: This memory is provided with an X decoding means (12) provided with a normal operation mode for decoding an inputted X address and generating selecting signals for driving a pertinent work line to a selected level and a test mode for generating the selection signals for simultaneously driving the work lines to the selected level by the assertion of test signals. By simultaneously driving the word lines to the selected level by the assertion of the test signals, the number of memory cells writable by one write operation is increased and the time required for the screening is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device,
Furthermore, the present invention relates to a technique for reducing the time required for the screening, and to a technique which is effective when applied to, for example, flash memory screening.

[0002]

2. Description of the Related Art Japanese Patent Application Laid-Open No. 2-289997 describes a batch erase type EEPROM (electrically erasable and programmable read only memory). This batch erase type EEPROM can be understood as having the same meaning as the flash memory in this specification. The flash memory is capable of rewriting information by electrical erasing and writing,
(Electrically Programmable Read Only
As in the case of (memory), the memory cell can be composed of one transistor, and has a function of electrically erasing all memory cells or a block of memory cells collectively. Therefore, flash memory is
The stored information can be rewritten in the state of being mounted on the system, the rewriting time can be reduced by the batch erasing function, and the chip occupation area can be reduced.

[0003]

In order to determine the quality of a flash memory, wafer probing is performed. Wafer probing is performed by writing a predetermined test pattern into a flash memory, then reading the test pattern and comparing it with an expected value. If the value matches the expected value, the flash memory is determined to be good. If the value does not match the expected value, it is determined to be defective.

[0004] A word line stripe pattern is written to determine the presence or absence of a short or cut between adjacent word lines, and a bit line stripe pattern is written to determine the presence or absence of a short or cut between adjacent bit lines. . Here, writing a word line stripe pattern means writing a predetermined test pattern every other word line, and writing a bit line stripe pattern means writing a predetermined test pattern every other bit line. Means to write.

In the flash memory, when an X address signal is input, writing is performed on one word line (for example, 512 bytes) of the memory array selected by the X decoding means. Therefore, for example, 1638 in the X direction
64M with 4 bits, 512 bytes size in Y direction
In order to perform writing and erasing of the bit memory cell array, 2 n times of writing and erasing operations are required.

In order to rewrite the word line stripe pattern, 2 n times of writing and erasing operations are required. To rewrite the bit line stripe pattern, 2 n times of writing and erasing operations are required. An erase operation is required.

As described above, in collecting information for judging pass / fail of a flash memory, it takes a long time to write a test pattern into the flash memory, so that a long time is required for screening.

An object of the present invention is to provide a technique for shortening the time required for screening.

[0009]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, a normal operation mode in which an input X address is decoded to form a selection signal for driving a corresponding word line to a selection level, and a plurality of word lines are simultaneously activated by a test signal being asserted. X decoding means (12) having a test mode for forming a selection signal for driving to a selection level is provided. The X decode means (12) can be configured to include a group of logic gates for performing a logical operation on a test signal group instructing simultaneous driving of 2 n word lines and an X address signal. The X-decoding means performs a first logical gate group (10, 3) for performing a logical operation of a first test signal instructing simultaneous driving of all the odd-numbered word lines and an X address signal.
0), a second test signal for instructing simultaneous selection of all even-numbered word lines, and a second logic gate group (20, 40) for performing a logical operation on the X address signal. Can be.

According to the above means, the X decode means simultaneously drives the plurality of word lines to the selected level when the test signal is asserted. This increases the number of memory cells that can be written in one write operation, shortens the time required for collecting information for judging the quality of the flash memory, and achieves a reduction in screening time.

At this time, a normal operation mode in which the input Y address is decoded to form a selection signal for selecting a corresponding bit line, and a plurality of bit lines are simultaneously selected by asserting a test signal. Y-decoding means (16) having a test mode for forming a selection signal for the operation can be provided.

The Y decoding means includes a third logic gate group (110, 130) for performing a logical operation of a third test signal for instructing simultaneous selection of all the odd-numbered bit lines and a Y address signal; A fourth test gate group (120, 1
40).

[0014]

FIG. 4 shows a data processing device including a flash memory as an example of a semiconductor memory device according to the present invention.

Reference numeral 65 denotes a flash memory card formed in a card shape including a plurality of flash memory chips. The flash memory card 65 is not particularly limited, but is provided with a random access memory together with a central processing unit (CPU) 61. A bus 66 to which a memory (RAM) 62 and a read-only memory (ROM) 63 are commonly connected;
It is connected via an interface circuit (I / F) 64. The flash memory card 65 is detachably attached to the data processing device by an appropriate connector. The flash memory card 65 stores various programs executable by the CPU 61, various data, and the like.

When the flash memory card 65 is mounted on the data processing device, the flash memory card 65
1 is accessed. The ROM 63 has a CPU 6
The program executed in step 1 is stored. RAM 62
Is a temporary storage area for data to be processed,
It is used as a work area for the arithmetic processing in 61.

Although not particularly limited, the flash memory card 65 is a JEIDA memory card (type I), that is, a memory card having an interface adapted to the JEIDA memory card interface. Then, the local memory 65b and the card controller 65
a, and both are connected by a local bus 65c, and are configured as a whole on a card board. Local memory 6
5b includes, but is not limited to, 20 flash memories having a storage capacity of 4 megabits. The card controller 65a controls the flash memory via an interface compatible with the JEIDA.

FIG. 5 shows the flash memory card 65.
Is representatively shown as an example of the configuration of a plurality of flash memories constituting.

The flash memory 100 shown in FIG.
Is an AND type, although not particularly limited,
It is formed on one semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique.

The flash memory 100 shown in FIG.
Although not particularly limited, data input / output pins PI / O0 to PI / O7 of 8 bits, address input pins PA0 to PA18 of 19 bits, and a period of an erase operation and a data write operation of stored information of the flash memory cell array 13 , An input pin 24 for a chip enable signal CE *, an input pin 25 for an output enable signal OE *, a write enable signal, and a signal R / B * (* means low active or signal inversion). And an input pin 26 for the signal WE *. The signal R / B *, the chip enable signal CE *, the output enable signal OE *, and the write enable signal WE * are not particularly limited, but can be input or output via a control buffer 21 including a plurality of buffers. .

Although not shown, a high-potential-side power supply pin such as 5 V, a low-potential-side power supply pin such as 0 V, and 12
A high voltage pin such as V is provided, through which power for operation is supplied.

The flash memory cell array 13 is formed by arranging a plurality of flash memory cells each constituted by an insulated gate field effect transistor having a two-layer gate structure in a matrix (to be described in detail later). The sources of all the flash memory cells constituting the flash memory cell array 13 are connected to the source selection switch 9.

The address buffer 11 converts an address signal supplied from the address input pins PA0 to PA18 into an internal complementary address signal. The converted address signal is transmitted to an X decoder and driver 12 and a Y decoder and selector 16 at the subsequent stage via an address latch (not shown). The X decoder and driver 12 decodes the input X address signal and drives a word line based on a selection signal obtained by decoding.

The Y address decoder and selector 16
Decodes the input Y address signal and, based on it,
It has a function of selecting a plurality of bit lines drawn from the flash memory cell array 13. The Y address decoder / selector 16 includes a read circuit 17a including a sense amplifier for amplifying a read signal from the bit line selected by the Y decoder / selector 16, and an erase / write for erasing and writing the flash memory cell array 13. Write circuit 17b is coupled. Then, the read circuit 17
a and the erase / write circuit 17b are coupled to an I / O buffer 18 including an input buffer for taking in write data or command data supplied from the outside and an output buffer for data. Also, the read circuit 17a
The operation of the erase / write circuit 17b is controlled by the controller 19.

The command data fetched via the I / O buffer 18 is supplied to a controller 19. The controller 19 receives a chip enable signal CE *, an output enable signal OE *, a write enable signal WE *, and the like, which are externally supplied, and performs read, erase, and write operations of the flash memory.
It controls various internal operations such as write verify.

FIG. 1A shows the relationship between the X-decoder and driver 12, the Y-decoder and selector 16, and the flash memory cell array 13. FIG. 1B shows the flash memory cell array 13. A cross section of one flash memory cell is typically shown.

As shown in FIG. 1A, the flash memory cell array 13 includes, but is not limited to, a plurality of word lines w1, w2, w3, and w4 and a plurality of bit lines b1 formed to intersect the word lines w1, w2, w3, and w4. , B2, b3, b4
And a flash memory cell MC connected to the intersection of the word line and the bit line. Here, one flash memory cell MC includes a floating gate 86, a control gate 87, a source diffusion region 88 formed above the semiconductor substrate 85 as shown in FIG.
And a drain diffusion region 89. The oxide film between the floating gate 86 and the semiconductor substrate 85 enables electron transfer using a tunnel phenomenon. Control gate 87 is coupled to corresponding word lines w1 to w4, drain diffusion region 89 is coupled to corresponding bit lines b1 to b4, and source diffusion region 88 is coupled to source line 8. A source line switch 9 is coupled to the source line 8, and the level of the voltage supplied to the source diffusion region 88 of the flash memory cell MC is switched by the source switch 9.

At the time of writing information, the drain diffusion region 89
Is applied with a predetermined level, a high voltage Vpp is applied to control gate 87, and source diffusion region 88 is grounded. Thereby, the flash memory cell M
C is turned on, a current flows, and avalanche breakdown occurs near the drain diffusion region 89 to generate electrons and holes. The holes flow toward the ground via the semiconductor substrate 85, and the electrons flow in the channel direction and flow into the drain diffusion region 89. At this time, some of the electrons are
Is accelerated by an electric field between the gate electrode and the drain diffusion region 19 and injected into the floating gate 16 to increase the threshold voltage of the flash memory cell MC.

On the other hand, erasing is performed in the drain diffusion region 8
9 is opened, the control gate 87 is grounded,
This is performed by applying a high voltage Vpp to the source diffusion region 18. A tunnel phenomenon occurs due to a potential difference between the source diffusion region 88 and the floating gate 86, and electrons are extracted from the floating gate 86, so that the threshold value of the flash memory cell decreases.

In FIG. 1A, an X decoder and a driver 12 are provided with two systems of X decoders and drivers 121 and 122 for driving a word line to a selected level by decoding an input X address signal.
Consists of The first X decoder and driver 121 is used to drive odd-numbered word lines w1 and w3 in the flash memory cell array 13 to a selected level, and the second X decoder and driver 122 is used to drive even-numbered word lines in the flash memory cell array 13. It is used to drive the word lines w2, w4 to which it belongs to a selected level. Then, the first X decoder and driver 121,
The first and second test signals TS0 and TS1 are input to the second X decoder and driver 122, respectively. The first and second test signals TS0 and TS1 are
It is used to speed up information collection for judging pass / fail of a flash memory in a test mode such as screening. For example, in a state where the first test signal TS0 is asserted to a high level, the output signals from the first X decoder and driver 121 are set to a high level, so that the odd-numbered word lines w1 and w3 are simultaneously driven to a selected level. . In a state where the second test signal TS1 is asserted to the high level, the output signals from the second X decoder and driver 122 are set to the high level, so that the even-numbered word lines w2 and w4 are simultaneously driven to the selected level.

The Y decoder and driver 16 comprises two systems of Y decoders and selectors 161 and 162 for decoding input address signals and selecting corresponding bit lines based on the decoded results. The first Y decoder and selector 161 is used to select odd-numbered bit lines in the flash memory cell array 13, and the second Y decoder and selector 162 is used to select even-numbered bit lines in the flash memory cell array 13. Used for For example, when the third test signal TS2 is asserted to a high level, the odd-numbered bit lines b1 and b3 are simultaneously selected. When the fourth test signal TS3 is asserted to a high level, the even-numbered bit lines b2 and b4 are simultaneously selected.

FIG. 2 shows a detailed configuration example of the X decoder and driver 12.

As shown in FIG. 2, X decoder and driver 12 includes, but is not limited to, four logic gate groups 10, 20, 30, and 40. Logic gate group 10, 3
0 belongs to the first X decoder and driver 121, and the logic gates 20 and 40 belong to the second X decoder and driver 122.

The logic gate group 10 includes a two-input NOR gate 3
1, 32 and 33 are combined. That is, the A0 address is input to one input terminal of the NOR gate 31, and the A3 address is input to one input terminal of the NOR gate 32. The first test signal TS0 is input to the other input terminals of the NOR gates 31 and 32. Then, the output signals of the NOR gates 31 and 32 are output to the NOR gate 33 in the subsequent stage.
, And their NOR logics are obtained, which are used as output signals of the logic gate group 10, and the corresponding word lines w
1

The logic gate group 20 includes a two-input NOR gate 3
4, 35, 36 are combined. That is, the A0 address is input to one input terminal of the NOR gate 34, and the A3 address is input to one input terminal of the NOR gate 35. The other input terminals of the NOR gates 34 and 35 receive the second test signal TS1. Then, the output signals of the NOR gates 34 and 35 are output to the NOR gate 36 at the subsequent stage.
, And their NOR logics are obtained, which are output signals of the logic gate group 20, and the corresponding word lines w
2

The logic gate group 30 includes a two-input NOR gate 3
7, 38 and 39 are combined. That is, the A0 address is input to one input terminal of the NOR gate 37, and the A3 address is input to one input terminal of the NOR gate 38. The other input terminals of the NOR gates 37 and 38 receive the first test signal TS0. The output signals of the NOR gates 37 and 38 are output to the NOR gate 39 at the subsequent stage.
, And their NOR logics are obtained, which are output signals of the logic gate group 30, and the corresponding word lines w
3

The logic gate group 40 includes a two-input NOR gate 4
1, 42 and 43 are combined. In other words, the A0 system address is input to one input terminal of the NOR gate 41, and the A3 system address is input to one input terminal of the NOR gate 42. The second test signal TS1 is input to the other input terminals of the NOR gates 41 and 42. The output signals of the NOR gates 41 and 42 are output to the NOR gate 43 of the subsequent stage.
To obtain the NOR logic of them, which is used as an output signal of the logic gate group 40, and the corresponding word line w
4 When the first test signal TS0 goes high, the output terminals of the logic gate groups 10, 30 are fixed at high level, and the word lines w1, w3 are driven. When the second test signal TS1 goes high, the output terminals of the logic gate groups 20, 40 are fixed at high level, and the word lines w2, w4 are driven.

FIG. 3 shows a detailed configuration example of the Y decoder and selector 16.

As shown in FIG. 3, Y decoder and selector 16 includes, but is not limited to, four logic gate groups 110, 120, 130, and 140. The logic gate groups 110 and 130 belong to the first Y decoder and selector 161, and the logic gates 120 and 140 belong to the second Y decoder and selector 162.

The logic gate group 110 is formed by connecting two-input NOR gates 131, 132, and 133. That is,
The A2 system address is input to one input terminal of the NOR gate 131, and A is input to one input terminal of the NOR gate 132.
The system 4 address is input. NOR gate 131, 132
The third test signal TS2 is input to the other input terminal of the third test signal TS2. Then, the output signals of the NOR gates 131 and 132 are input to the NOR gate 133 in the subsequent stage, and their NOR logics are obtained. The NOR signals are taken as the output signals of the logic gate group 110 and coupled to the corresponding selector Q1. Selector Q1
Is an n-channel MOS transistor, which is turned on when the output signal of the logic gate group 110 is set to a high level, and the bit line b1 is conducted to the I / O line.

The logic gate group 120 is formed by combining two-input NOR gates 134, 135, and 136. That is,
The A2 address is input to one input terminal of the NOR gate 134, and A is input to one input terminal of the NOR gate 135.
The system 4 address is input. NOR gates 134 and 135
The fourth test signal TS3 is input to the other input terminal of the second test signal. Then, the output signals of the NOR gates 134 and 135 are input to the NOR gate 136 at the subsequent stage, and their NOR logics are obtained. The NOR signals are taken as the output signals of the logic gate group 120, and are coupled to the corresponding selector Q2. Selector Q2
Is an n-channel MOS transistor, which is turned on when the output signal of the logic gate group 120 is set to a high level, and the bit line b2 is conducted to the I / O line.

The logic gate group 130 is formed by connecting two-input NOR gates 137, 138 and 139. That is,
The A2 system address is input to one input terminal of the NOR gate 137, and A is input to one input terminal of the NOR gate 138.
The system 4 address is input. NOR gate 137,138
The third test signal TS2 is input to the other input terminal of the third test signal TS2. Then, the output signals of the NOR gates 137 and 138 are input to the NOR gate 139 at the subsequent stage, and their NOR logics are taken. The output is taken as the output signal of the logic gate group 130, and is coupled to the corresponding selector Q3. Selector Q3
Is an n-channel MOS transistor, which is turned on when the output signal of the logic gate group 130 is set to the high level, and the bit line b3 is conducted to the I / O line.

Logic gate group 140 is formed by combining two-input NOR gates 141, 142, and 143. That is,
The A2 system address is input to one input terminal of the NOR gate 141, and A is input to one input terminal of the NOR gate 142.
The system 4 address is input. NOR gate 141, 142
The fourth test signal TS3 is input to the other input terminal of the second test signal. Then, the output signals of NOR gates 141 and 142 are input to NOR gate 143 at the subsequent stage, and their NOR logics are taken. The output signals are used as output signals of logic gate group 140 and are coupled to corresponding selector Q4. Selector Q4
Is an n-channel MOS transistor, which is turned on when the output signal of the logic gate group 140 is set to a high level, and the bit line b4 is conducted to the I / O line. here,
As shown in FIG. 5, a read circuit 17 is connected to the I / O line.
a and the erase / write circuit 17b.

The operation will be described.

The first, second, third and fourth test signals TS
In a state where 0, TS1, TS2, and TS3 are asserted to a low level, normal operation of the flash memory 100 is enabled.

Writing is performed as follows.

An X address signal is fetched through an address buffer 11 and is fetched by an X decoder and driver 12.
, And is decoded to drive one word line to the selected level. Then, the Y address is fetched via the address buffer 11, is input to the Y decoder and selector 16, the corresponding bit line is selected based on the decoding result, and the high voltage Vpp is applied to the memory cell. Source line 8 is grounded by source line switch 9. Corresponding to the write data described later,
In some cases, a corresponding bit line is selected based on the decoding result, and a ground voltage is applied to the memory cell. I
When the write data is fetched via the / O buffer 18, it is transmitted to the selected bit line via the erase / write circuit 17b and the Y decoder and selector 16. As a result, a current flows through the corresponding memory cell,
The generation of hot electrons increases the threshold value. When a ground voltage is applied to the selected bit line, the threshold does not change. In a flash memory, an erasing operation is performed immediately before writing.

Reading is performed as follows.

As in the case of the write operation, an X address signal is fetched through the address buffer 11 and is input to the X decoder and driver 12 and decoded, so that one word line is at the selected level. Is driven. Then, the Y address is fetched via the address buffer 11 and is read by the Y decoder and selector 16.
And a corresponding bit line is selected based on the decoding result. When the source line 8 is grounded by the source line switch 9 and data is written into the memory cell and the threshold value is high, a high level signal is supplied from the word line to the control gate 87 of the memory cell. Also, the memory cell does not turn on and the bit line
No current flows through On the other hand, when the memory cell is erased, a current flows from the bit line to the source line 8 because the memory cell is turned on. Whether or not a current flows from the bit line to the source line 8 is determined by the read circuit 17a.

The erasure is performed as follows.

By setting all the word lines w1 to w4 and all the bit lines b1 to b4 to the non-selected state, all the flash memory cells are set to the non-selected state. When all the word lines w1 to w4 are not selected, all the word lines are set to the low level, and the drains of the flash memory cells MC are opened. A high voltage is applied to the source line 8 via the source line switch 9. Then, the threshold value of the memory cell is shifted to a lower value due to the tunnel phenomenon. Since the source line is common, all memory cells are erased collectively.

The screening will be described.

The batch writing on the entire surface of the flash memory cell array 13 is performed as follows.

In wafer probing, first, second, third and fourth test signals TS0, TS1, TS2 and T
S3 is asserted high. Thereby, all the word lines w1 to w3 are driven to the selected level, and
All bit lines b1 to b4 are selected. A high voltage Vpp is applied to the memory cell via the selected bit line,
Source line 8 is grounded by source line switch 9. I
When a test pattern for writing is fetched via the / O buffer 18, it is sent to the erase / write circuit 17.
By being transmitted to the selected bit line via b and the Y decoder and selector 16, batch writing on the entire surface of the flash memory cell array 13 is enabled.

The writing of the word line stripe pattern is performed as follows.

In wafer probing, by asserting the first test signal TS0 to the high level, the odd-numbered word lines w1 and w3 can be driven to the selected level. At this time, the third and fourth test signals TS2 , TS
When 3 is asserted to a high level, writing to all the flash memory cells MC coupled to the odd-numbered word lines w1 and w3 is enabled. The assertion of the second test signal TS1 to the high level drives the even-numbered word lines w2 and w4 to the selected level. At this time, the third and fourth test signals TS2 and TS3 are asserted to the high level. The even-numbered word lines w2
Writing to all the flash memory cells MC coupled to w4 is enabled.

The writing of the bit line stripe pattern is performed as follows.

In the wafer probing, the first and second test signals TS0 and TS1 are asserted to a high level, so that the word lines w1, w2, w3 and w4 are simultaneously set to the selection level regardless of the address input at that time. be able to. In this state, when the third test signal TS2 is asserted to a high level, the odd-numbered bit lines b
Since 1 and b3 are selected, writing to all the flash memory cells MC coupled to the odd-numbered bit lines b1 and b3 is enabled. Similarly, the word line w
When the fourth test signal TS3 is asserted to a high level in a state where 1, w2, w3, and w4 are simultaneously set to the selection level, the even-numbered bit lines b2 and b4 are selected. Writing to all the flash memory cells MC coupled to the lines b2 and b4 is enabled.

According to the above-described example, the following effects can be obtained.

(1) The X decoder and driver 12 decodes the input X address and forms a selection signal for driving the corresponding word line to a selection level, and the test signals TS0 and TS1 are used in the normal operation mode. Since it has a test mode in which a selection signal for simultaneously driving all word lines to a selection level by being asserted is provided, it is possible to assert test signals TS0 and TS1 to a high level in wafer probing. , Regardless of the address input at that time, word lines w1, w
2, w3, and w4 can be simultaneously set to the selection level. Therefore, by applying an address signal as in the related art, writing of the test pattern is performed at a higher speed than in the case where the word lines are individually selected one by one. Thus, the screening time can be shortened.

(2) First logic gate group 10, 30 for performing a logical operation on first test signal TS0 and X address signal
And second logic gate groups 20 and 40 for performing a logical operation on the second test signal TS1 and the X address signal.
Since the decoder and the driver 12 are configured, all the odd-numbered word lines w1 and w3 and all the even-numbered word lines w2 and w4 can be individually driven to the selected level. Therefore, the first test signal TS0 is asserted to a high level to simultaneously drive all the odd-numbered word lines w1 and w3 to the selected level, and all the odd-numbered word lines w1 and w3.
Test pattern can be written to the flash memory cell corresponding to. Similarly, the second test signal TS1 is asserted to a high level to simultaneously drive all even-numbered word lines w2 and w4 to a selected level, and the flash memory corresponding to all even-numbered word lines w2 and w4 A test pattern can be simultaneously written in a cell.

(3) A normal operation mode in which the Y decoder and selector 16 decodes the input Y address and forms a selection signal for selecting a corresponding bit line;
Since a test signal is asserted to form a selection signal for selecting a plurality of bit lines at the same time, the test signals TS2 and TS3 are asserted to a high level during wafer probing. Since all bit lines b1, b2, b3, and b4 can be simultaneously selected regardless of the address input at that time, the number of memory cells that can be written by one write operation is increased, and the test pattern is reduced. Since writing can be performed in a short time, the time required for screening can be reduced.

(4) Third logic gate group 110, 1 for performing a logical operation on the third test signal TS2 for simultaneously selecting all the odd-numbered bit lines and the Y address signal
30 and a fourth test signal TS3 for simultaneously selecting all the even-numbered bit lines, and fourth logic gate groups 120 and 140 for performing a logical operation on the Y address signal. Is configured,
All the odd-numbered bit lines b1 and b3 and the even-numbered bit lines b2 and b4 can be individually selected. Therefore, the third test signal TS2 is asserted to a high level to simultaneously select all the odd-numbered bit lines b1 and b3, and test the flash memory cells corresponding to all the odd-numbered bit lines b1 and b3. If you write a pattern,
The writing of the bit line stripe can be performed at high speed by one writing operation. Similarly, the fourth test signal TS3 is asserted to a high level to simultaneously select all the even-numbered bit lines b2 and b4, and perform a test on the flash memory cells corresponding to all the even-numbered bit lines b2 and b4. If a pattern is written, writing for a bit line stripe can be performed at high speed by one writing operation.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say.

For example, the X decoder and the driver and the Y decoder and the selector can correspond to more word lines and bit lines by increasing the number of logic gate groups.

Further, the present invention is not limited to the even or odd number, and 2 n word lines can be simultaneously driven, and 2 n bit lines can be simultaneously selected. .

In the above description, the invention made mainly by the present inventor is described in the field of application AND
Although the present invention has been described for the case where the present invention is applied to a flash memory of the type, the present invention is not limited to this, and various flash memories, furthermore, a static random access memory and a dynamic random access memory
The present invention can be applied to various semiconductor storage devices such as a memory.

The present invention can be applied on the condition that at least a plurality of word lines or a plurality of bit lines are included.

[0069]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, since a plurality of word lines can be simultaneously driven to the selected level, the number of writable memory cells can be increased by one write operation, and a test pattern can be written at high speed. The time required for screening can be reduced.

Further, since a plurality of bit lines can be simultaneously selected, the number of memory cells which can be written by one writing operation is increased, and the time required for screening can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram and a cross-sectional view of an example of a configuration of a main part of a flash memory as an example of a semiconductor memory device according to the present invention.

FIG. 2 is a detailed configuration example circuit diagram of an X decoder and a driver in the flash memory.

FIG. 3 is a detailed configuration example circuit diagram of a Y decoder and a driver in the flash memory.

FIG. 4 is a block diagram illustrating a configuration example of a data processing device including the flash memory.

FIG. 5 is a block diagram showing an overall configuration example of the flash memory.

[Explanation of symbols]

10, 20, 30, 40, 110, 120, 130, 1
Reference Signs List 40 logic gate group 11 address buffer 12 X decoder and driver 13 flash memory cell array 16 Y decoder and selector 17a readout circuit 17b erase / write circuit 18 I / O buffer 19 controller 21 control buffer 121 first X driver and driver 122 second X driver and Driver 161 First Y decoder and selector 162 Second Y decoder and selector b1, b2, b3, b4 Bit line w1, w2, w3, w4 Word line

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Shino Saki Yoshihiro 3-1-1, Higashi Koigabo, Kokubunji-shi, Tokyo Within Hitachi Ultra LSE Engineering Co., Ltd. (72) Inventor Koji Shigematsu Tokyo 3-1, 1-1 Higashi-Koigabo, Kokubunji-shi Hitachi Ultra-LSI Engineering Co., Ltd. (72) Inventor Hisako Fujioka 3-1-1, Higashi-Koigabo, Kokubunji-shi, Tokyo Hitachi Ultra-SII Engineering Katsumoto Kase, Inventor Katsumoto Kase 3-1-1, Higashi Koigakubo, Kokubunji-shi, Tokyo Hitachi Ultra LSE Engineering Co., Ltd. Address 1 Inside Hitachi Ultra LSE Engineering Co., Ltd. (7 2) Inventor Hidefumi Mukada 3-1-1, Higashi Koigabo, Kokubunji-shi, Tokyo Inside Hitachi Ultra-SII Engineering Co., Ltd.

Claims (5)

[Claims] A plurality of word lines and a plurality of bit lines formed so as to intersect the word lines, wherein the word lines are driven to a selected level and the bit lines are selected. A semiconductor memory device capable of reading and writing information, comprising decoding means for driving the word line to a selected level, wherein the decoding means comprises 2 n words (n is a positive integer). A semiconductor memory device comprising a logic gate group for performing a logical operation of a test signal group for instructing simultaneous driving of lines and an X address signal. 2. A method for generating a selection signal for simultaneously selecting a plurality of bit lines, comprising: Y decoding means for simultaneously selecting 2 n (n is a positive integer) bit lines 2. The semiconductor memory device according to claim 1, further comprising a logic gate group for performing a logical operation on a test signal group for instructing the operation and a Y address signal. 3. A semiconductor device comprising: a plurality of word lines; and a plurality of bit lines formed to cross the word lines, wherein the word lines are driven to a selected level and the bit lines are selected. In the semiconductor memory device capable of reading and writing information, the semiconductor memory device includes decoding means for driving the word line to a selected level, and the decoding means instructs simultaneous driving of all the odd-numbered word lines. A first logic gate group for performing a logical operation between the first test signal and the X address signal, a second test signal for instructing simultaneous selection of all even-numbered word lines, and a logical operation for the X address signal. And a second group of logic gates to be performed. 4. A method for generating a selection signal for simultaneously selecting a plurality of bit lines by asserting a test signal, the Y decoding means comprising: a simultaneous decoding of all odd-numbered bit lines; A third logic gate group for performing a logical operation of a third test signal instructing selection and a Y address signal; a fourth test signal instructing simultaneous selection of all even-numbered bit lines; 4. The semiconductor memory device according to claim 3, comprising: a fourth group of logic gates for performing a logical operation. 5. A nonvolatile memory cell constituted by an insulated gate field effect transistor having a two-layer gate structure, wherein a control gate and a drain diffusion region of the nonvolatile memory cell correspond to the corresponding word line and bit line, respectively. 5. The semiconductor memory device according to claim 3, further comprising: