JPH11144493A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory device whose yield can be enhanced by relieving a defective address many times. SOLUTION: In correspondence to fuse sets RFS0 to RFS15, for relief, which are used to set a defective address inside a defective-address changeover circuit 15, relief judgment means JFC0 to JFC15 which are composed of program elements such as fuses or the like which can store information indicating whether the fuse sets are used or not are installed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique particularly effective when applied to a defect remedy method in a semiconductor memory device and a nonvolatile semiconductor memory device. For example, an electrically erasable and erasable EEPROM (electrically erasable EEPROM) is used. The present invention relates to a technology that is effective when a flash memory that can electrically and collectively erase multiple pieces of stored information is used.

[0002]

2. Description of the Related Art A flash memory is a nonvolatile semiconductor memory device having a function of electrically erasing all memory cells in a chip or a group of memory cells in a group of memory cells in a chip.

In a conventional flash memory, a spare memory column and a defective address switching circuit are provided in a memory array portion, and an address of a memory column in which a defect is detected by a probe test is blown in a defective address switching circuit. In some cases, a rescue function is provided in which a setting is made in such a manner that when a defective address is accessed, a spare memory row is switched to perform rescue. Moreover,
The defective address switching circuit is configured to be able to set a plurality of defective addresses, and is configured to be able to repair a plurality of (for example, 16) memory columns.

[0004]

In a flash memory, a stress such as heating in a wafer state is applied after the above-described defective address is relieved, and a retention defect, that is, a threshold value due to writing or erasing does not rise or fall due to the stress. Checks are being performed. However, in the conventional flash memory, although a plurality of defective addresses can be set, there is no information indicating whether or not the defective addresses are used. Is performed, even if a defect is found in the subsequent wafer baking process and retention defect inspection, there is no remedy method, and it cannot be fully exhibited while having a rescue function for a plurality of defective addresses. It turned out that there was.

An object of the present invention is to provide a semiconductor memory device capable of relieving a defective address any number of times and improving the yield.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0007]

The following is a brief description of an outline of typical inventions disclosed in the present application.

In other words, a rescue fuse comprising a program element such as a fuse capable of storing information indicating whether or not a rescue fuse is used, corresponding to a rescue fuse set for setting a defective address in the defective address switching circuit. The determination means is provided.

Thus, when a defect is found by a wafer baking process and a retention defect inspection after the defective address is relieved, the defective address can be set again to an unused rescue fuse set in the defective address switching circuit. As a result, the yield of the semiconductor memory device can be improved.

In addition, a nonvolatile memory element such as FAMOS having a floating gate can be used instead of a fuse as a program element for setting the above-mentioned defective address and information indicating the use or non-use of the defective address. Can be set, and a device for cutting a fuse by a laser or the like becomes unnecessary, so that a tester used for inspection can perform rescue, and when a fuse is used, rescue processing cannot be performed unless the wafer is in a wafer state. By using a nonvolatile memory element as a program element, a remedy process can be performed even after the nonvolatile memory element is sealed in a package or the like.

The technique of using a nonvolatile memory element as a program element is based on a technique of using a nonvolatile memory element as a memory cell in a nonvolatile semiconductor memory device such as a flash memory or an EEPROM from the viewpoint of commonality of processes and cost reduction. It is desirable to apply in.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of a flash memory to which the present invention is applied. Although not particularly limited,
Each circuit block shown in FIG. 1 is formed on one semiconductor chip such as single crystal silicon.

In FIG. 1, reference numeral 11 denotes a memory array in which memory cells each composed of a MOSFET having a floating gate are arranged in a matrix. In this embodiment, the memory array is divided into memory mats 11A and 11B. A circuit block SL & that includes a sense latch circuit for holding write data for one row (one sector) and amplifying and holding a signal read on a bit line at the time of reading, and a Y decoder circuit for selecting a bit line.
Y-DEC is provided. Also, the memory mat 11
A and 11B have spare memory arrays RMC1, RMC on one side.
2 are provided. Although not particularly limited, this embodiment is configured so that 8-bit data is input / output in parallel, and correspondingly, the spare memory columns RMC1, RMC1
A total of 16 sets of MC2 are also provided, each set having eight sets.

An X decoder 12 decodes an externally input X address signal X-add and selects one of the word lines in the memory array 11 corresponding to the address signal. A Y address signal (bit line select signal) for sequentially transferring externally applied write data to the sense latch SL or sequentially outputting data read from the memory mats 11A and 11B to the sense latch SL to the outside is provided. A Y address counter to be generated, 15 is a Y-related defective address switching circuit for setting a defective address corresponding to the defective bit line and replacing it with a spare memory column, and 16 is provided to a sense latch SL integrated with the Y decoder Y-DEC. This is a main amplifier that amplifies the read data and outputs the amplified data to the outside. Reference numeral 17 denotes an I / O buffer for input / output of read data and write data.
It is configured to input and output data through common external terminals I / O0 to I / O7, and to have a command and address signal input function to save the number of external terminals.

Further, the Y-system defective address switching circuit 1
A program element such as a fuse which has a rescue fuse set for setting a plurality of defective addresses in 5 and which can store information indicating whether or not each rescue fuse is used corresponding to each rescue fuse set Is provided.

Further, the flash memory of this embodiment is not particularly limited, but has a command latch circuit 21 for holding a command given from an external microprocessor or the like, and decodes the latched command to perform an operation corresponding to the command. A sequencer 22 for sequentially forming and outputting a control signal for each circuit in the memory to be executed. When a command is given from the outside, the sequencer 22 is configured to decode the command and automatically start a corresponding process. ing.

The sequencer 22 is, for example, a ROM (Read Only Memory) storing a series of microinstructions necessary for executing a command (instruction), like a control section of a microprogram type CPU. By generating the start address of the microinstruction group corresponding to the command latched by the command latch circuit 21 and applying the head address to the sequencer 22, the microprogram can be started.

Further, in the flash memory of this embodiment, in addition to the above circuits, a write / erase determination circuit for determining whether the threshold value of a memory cell selected at the time of data writing has sufficiently reached a write level or an erase level. 23, a control signal input buffer circuit 24 to which a control signal supplied from an external microprocessor or the like is input, a write voltage, an erase voltage, a read voltage, a verify voltage, etc. based on an externally supplied power supply voltage Vcc. And a power supply switching circuit 2 for selecting a desired voltage from these voltages according to the operation state of the memory and supplying the selected voltage to the memory array 11 and the X decoder 12.
6. A trimming decoder 27 for adjusting the level of a voltage generated in the power supply circuit 25 is provided.

Although not particularly limited, the flash memory of this embodiment shares the external terminal (pin) I / O for the input / output of the read data signal and the write data signal and the input of the command and the address signal as described above. ing. For this reason, the I / O buffer 17 is configured to discriminate these input signals in accordance with the control signal from the control signal input buffer circuit 24 and supply them to a predetermined internal circuit. Further, in this embodiment, information indicating whether or not the rescue fuse in the defective address switching circuit 15 is used can be read out to the outside via the I / O buffer 17.

The control signals input from an external microprocessor or the like to the flash memory of this embodiment include:
For example, there are a reset signal RES, a chip selection signal CE, a write control signal WE, an output control signal OE, a command data enable signal CDE for indicating whether a command or data input or an address input, a serial clock SC, and the like. Further, a terminal is provided for outputting a ready / busy signal R / B for indicating that a command or the like cannot be input from the memory side to an external microprocessor.

FIG. 2 shows a configuration example of a defective address switching circuit which is the gist of the present invention. The defective address switching circuit according to the present embodiment includes 16 defective address setting fuse circuit sets RF capable of setting up to 16 defective addresses.
In addition to S0 to RFS15, rescue determination fuse circuits JFC0 to JFC15 for indicating whether or not each fuse circuit set is used are provided corresponding to each fuse circuit set. Further, the defective address setting fuse circuit sets RFS0 to RFS15 are in one-to-one correspondence with one of the 16 sets of spare memory rows RMC1 and RMC2.

The defective address set in the defective address setting fuse circuit sets RFS0 to RFS15 is input to one input terminal of comparators CMP0 to CMP15, and the other input terminal of the comparators CMP0 to CMP15 has the Y address counter 14 connected thereto. The address switching signals AC0 to AC15 are output when the two address signals are compared and matched. By the address switching signals AC0 to AC15, the supply of the Y address signal from the Y address counter 14 to the Y decoder is cut off, and the spare memory column set corresponding to the fuse circuit set in which the coincident defective address is set is selected. It is configured to:

FIG. 3 shows the fuse circuit JF for repair judgment.
A specific circuit configuration example of C0 to JFC15 is shown. As shown in FIG.
Ci (i = 0, 1, 2, $ 15) is the power supply voltage Vcc
A fuse element Fi composed of a polysilicon layer or the like connected in series between the power supply and a ground point, and a MOSFET Qi. A read clock RCL for reading the state of the fuse is provided at the gate terminal of the MOSFET Qi.
K can be input.

Therefore, when the read clock RCLK is set to a high level, a detection signal of a low level (ground potential) is detected according to the state of the fuse Fi if the fuse Fi is in a cut state, and high if the fuse Fi is in a non-cut state. A level (Vcc) detection signal is output. Then, the output signal of each repair determination fuse circuit JFCi is supplied to an output buffer circuit OBF provided in the I / O buffer 17 via a transmission gate TGi formed of, for example, a CMOS transmission gate.

The output buffer circuit OBF comprises a series P-channel MOSFET Qp and an N-channel MOSFET
Push-pull output stage OPT composed of ET Qn
And control logic gate circuits G1 to G5 for forming signals for controlling the gate terminals of the output MOSFETs Qp and Qn.
A signal is output during a period when the out enable signal OE is at a high level, and during a period when the out enable signal OE is at a low level, both the output MOSFETs Qp and Qn are turned off to be in an output high impedance state. ing.

Although not particularly limited, the flash memory according to this embodiment has eight data input / output terminals and 16 relief circuit fuse circuits in consideration of the fact that there are 16 fuse circuits for repair determination. Fuse circuit JFC0
15 are grouped into two groups, and the control terminal of the transmission gates TG0, TG2, TG4 ‥‥ TG14 connected to one output terminal of the rescue judging fuse circuits of each group receives the selection clock / SCLK1. Further, a transmission gate T connected to one output terminal of the other repair judgment fuse circuit.
The selection clock / SCLK2 is input to the control terminals of G1, TG3, TG5 ‥‥ TG15. The selection clocks / SCLK1 and / SCLK2 are configured so that the signals are set to the low level as the valid level and are not simultaneously set to the valid level.

As a result, as shown in FIG. 4, when the high-level read clock RCLK is supplied, one of the repair decision fuse circuits of each set is selected according to the selection clocks / SCLK1 and / SCLK2. Is output from the output buffer circuit OBF.

Further, an output signal of the main amplifier 16 for amplifying read data is supplied to the output buffer circuit OBF.
Are provided with transmission gates TG20 to TG27 that can be supplied / cut off, and the transmission gate TG20 is controlled by the read clock RCLK. Note that, instead of using the read clock RCLK as a signal for controlling the transmission gates TG20 to TG27, a NAND gate circuit having the selected clocks / SCLK1 and / SCLK2 as input signals is provided, and the transmission signal is output by the NAND gate circuit. Gate TG20 ~
You may comprise so that TG27 may be controlled.

As a result, as shown in FIG. 5, when the selected clocks / SCLK1 and / SCLK2 are both at an invalid level, that is, at a high level, the transmission gates TG20 to TG27 are opened to open the main amplifier 1
6 is supplied to the output buffer circuit OBF, while, as shown in FIG.
In a state where K is at a high level, which is an effective level, the transmission gates TG20 to TG27 are cut off, and the supply of the output signal of the main amplifier 16 to the output buffer circuit OBF is cut off. A low-level selection clock (/ SCLK) of the determination fuse circuit
1 or / SCLK2) is supplied to the output buffer circuit OBF.

In the remedy judging fuse circuit set of the embodiment of FIG. 3, adjacent fuse circuits are paired to output either one of the detection signals. However, the fuse circuits JFC0 and JFC8 are connected to each other. Also JFC
1 and JFC9, and JFC2 and JFC10 can be combined.

In the embodiment, a fuse element which can be cut by a laser or the like is used as a program element. However, a nonvolatile memory element such as FAMOS having a floating gate constituting a memory cell of a flash memory or an EEPROM is used. You may. Further, in the embodiment, the transmission gates TG0 to TG15, TG20 to TG27
Used a CMOS transmission gate as
Two P-channel MOSFETs and two N-channel MOs
SFETs are connected in series and any one set of P, NM
A clocked inverter configured to input a clock to the gate terminal of the OSFET may be used.

As described above, in the above embodiment, information indicating whether or not the rescue fuse is used is stored in correspondence with the rescue fuse set for setting the defective address in the defective address switching circuit. Since a rescue judging means comprising a program element such as a fuse or the like is provided, if a defect is found by a wafer baking process and a retention defect inspection after relieving a defective address, the defective address is remedied in the defective address switching circuit. It is possible to set the fuse set again, thereby improving the yield of the semiconductor memory device.

A non-volatile memory element such as FAMOS having a floating gate can be used instead of a fuse as a program element for setting the defective address and information indicating whether or not the defective address is used. Can be set, and a device for cutting a fuse by a laser or the like becomes unnecessary, so that a tester used for inspection can perform rescue, and when a fuse is used, rescue processing cannot be performed unless the wafer is in a wafer state. However, by using a nonvolatile memory element as a program element, there is an effect that a rescue process can be performed even after sealing in a package or the like.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say. For example, in the above-described embodiment, the description has been given of the embodiment in which the defective address switching circuit and the spare memory are provided only for the Y-system address to relieve the bit line defect. However, the present invention is not limited thereto. The present invention can also be applied to a case where a defective address switching circuit and a spare memory row are provided for an X-system address or both an X-system address and a Y-system address to relieve a word line defect.

In the above description, the case where the invention made by the present inventor is mainly applied to a flash memory, which is the field of application as the background, has been described. However, the present invention is not limited to this, and it is possible to repair a defective address. The present invention can be widely applied to all semiconductor memory devices in which stress is applied later and the inspection is performed again to determine the presence / absence of a defective address.

[0037]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the present invention can provide a semiconductor memory device capable of relieving a defective address any number of times, thereby improving the yield.

[Brief description of the drawings]

FIG. 1 is an overall block diagram schematically showing an embodiment of a flash memory according to the present invention.

FIG. 2 is a block diagram showing a configuration example of a defective address switching circuit of the flash memory according to the present invention.

FIG. 3 is a circuit diagram showing a specific example of a circuit for storing information on the presence / absence of setting of a defective address.

FIG. 4 is a timing chart showing a timing at the time of reading information on whether or not a defective address is set;

FIG. 5 is a timing chart showing signal states at the time of reading information from a memory cell in the flash memory of the embodiment.

[Explanation of symbols]

 Reference Signs List 11 memory array 11A, 11B memory mat 12 X decoder 14 Y address counter 15 Y-related defective address switching circuit 16 main amplifier 17 I / O buffer 21 command latch circuit 22 sequencer 23 write / erase determination circuit 24 control signal input buffer circuit 25 power supply circuit 26 Power supply switching circuit 27 Trimming decoder

Continuing on the front page (72) Inventor Terutaka Okada 3-1-1 Higashi Koigakubo, Kokubunji, Tokyo Metropolitan Government Inside Hitachi Ultra LSE Engineering Co., Ltd. Address 1 Hitachi Ultra LSE Engineering Co., Ltd. (72) Inventor Hisako Fujioka 3-1-1 Higashi Koigakubo, Kokubunji-shi, Tokyo Hitachi Ultra LSI Engineering Co., Ltd. (72) Inventor Hiroyuki Uchida 5-2-1, Josuihoncho, Kodaira-shi, Tokyo In the Semiconductor Division, Hitachi, Ltd.

Claims (4)

[Claims] 1. A defective memory having a plurality of spare memory columns or spare memory rows provided separately from normal memory cells in a memory array and a plurality of defective address setting means capable of setting a defective address. A semiconductor memory device including a defective address switching circuit for replacing a memory column or a memory row corresponding to the address and an address signal to be supplied to the decoder with a spare memory column or a spare memory row when the addresses coincide with each other; Corresponding to the plurality of defective address setting means, a relief determining means having a program element capable of storing information indicating whether or not each defective address setting means is set,
A semiconductor memory device characterized in that the information indicating the presence or absence of the setting can be output to the outside. 2. The rescue judging means according to claim 1, wherein a plurality of the rescue judging means are arranged in groups, and one of the sets is selectively output from an external terminal. Semiconductor storage device. 3. The semiconductor according to claim 1, wherein the information indicating the presence or absence of the setting of the defective address is configured to be output from an external input / output terminal for read data and write data. Storage device. 4. The semiconductor memory device according to claim 1, wherein said program element comprises a nonvolatile memory element.