JP3886679B2 - Semiconductor memory device and control method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device capable of selecting all memory cells in a memory cell array, and more particularly to a semiconductor memory capable of performing a burn-in test in which a desired stress is applied to all memory cells in a state where all memory cells are selected. Intended for equipment.
[0002]
[Prior art]
One technique for schooling (inspecting) a semiconductor memory is called a burn-in test. The burn-in test is to inspect the destruction state of the memory cell by applying stress in the operation state of the memory cell, for example, the writing state in a state where the conditions are severely accelerated by increasing the temperature and the power supply voltage.
[0003]
In the burn-in test, it is necessary to apply stress for a much longer time than normal memory access, so testing for each address while incrementing the address takes a huge amount of test time, which is actually impossible It is. For this reason, it is common to apply stress to each memory cell simultaneously with all the memory cells selected at the same time.
[0004]
FIG. 6 is a schematic circuit diagram of a conventional selection control circuit for selecting all memory cells in a semiconductor memory. The address buffer 31 buffers externally input address signals by the input first stage circuit 32 and then generates two types of positive and negative signals Ai and / Ai by NAND gates G1 and G2. These two types of signals are input to the decoding circuit 33 and decoded.
[0005]
The NAND gates G1 and G2 receive all cell test signals that are at a low level during the burn-in test. When this signal becomes low level, the outputs of the NAND gates G1 and G2 both become high level, and all memory cells are selected.
[0006]
FIG. 7 is a diagram showing a schematic configuration of a memory cell array in the SRAM. Each memory cell is connected between a word line and a bit line pair, and a column transfer gate 34 is connected to the bit line pair. The column transfer gate 34 is on / off controlled by a column decoder 35.
[0007]
During normal SRAM writing, only one word line and one set of column transfer gates 34 are selected, and data on the data line pair Din, / Din is written only to a specific memory cell. On the other hand, during the burn-in test, all the word lines and all the column transfer gates 34 are selected, and the data on the data line pair Din, / Din is written into all the memory cells.
[0008]
By the way, recent semiconductor memories have been increasingly provided with spare cells that can be replaced with defective cells in order to improve yield. In this type of memory, a defective cell in which a failure such as a short-circuit failure has occurred is replaced with a spare cell in row units or column units.
[0009]
The address indicating the defective portion is stored in the chip by cutting the fuse element. When an address is input from the outside during normal operation of the memory, this address is compared with the address of the defective part stored in the chip, and if they match, replacement with a spare cell is performed.
[0010]
[Problems to be solved by the invention]
However, when a burn-in test is performed on a memory having a defective cell, all the memory cells are forcibly selected by the circuit shown in FIG. 6 described above, so that a defective cell is also selected. For this reason, for example, when a short circuit failure occurs in the bit line, a leak current flows from the data line Din to the ground terminal via the bit line as shown by the thick line path in FIG. The high-level voltage will decrease. When the high level voltage of the data line Din decreases, the stress level supplied to other normal cells also decreases accordingly, and normal screening cannot be performed.
[0011]
Such a problem may occur not only when a short circuit failure to the ground level occurs but also when a short circuit failure to the power supply voltage level occurs. In this case, the low level voltage rises and the stress level on the low level side becomes insufficient.
[0012]
These problems can occur not only when the memory cell itself is defective, but also when a column-related defect or a row-related defect occurs.
[0013]
The present invention has been made in view of these points, and an object of the present invention is to provide a semiconductor memory device in which the stress level applied to each memory cell when all cells are selected is not affected by a defective cell. There is to do.
[0014]
[Means for Solving the Problems]
In order to solve the above-described problem, according to one embodiment of the present invention, a semiconductor memory device capable of selecting all memory cells in a memory cell array predecodes an address signal input from the outside in units of a plurality of address bits. First predecoding means, a defect information storage means for predecoding and storing addresses corresponding to defective cells in units of the plurality of address bits, a predecoding result of the first predecoding means, A first selection unit that selects and outputs one of the predecode results of the defect information storage unit; a second predecode unit that performs address decoding based on an output of the first selection unit; Inversion means for inverting the output signal of the second predecoding means, output signal of the second predecoding means, and the inverting means Second selection means for selecting and outputting any one of the output signals, and when the all memory cell selection signal instructing selection of all memory cells is input, the first selection means While selecting the predecode result of the information storage means, the second selection means selects the output signal of the inversion means, and during normal cell access, the first selection means is the first predecode means A semiconductor memory device is provided in which a predecode result is selected, and the second selection means selects a decode result of the second predecode means.
[0016]
In one aspect of the present invention, the result of predecoding the address corresponding to the defective cell in units of a plurality of address bits is stored as defective information, so that not only the address of the defective cell but also information indicating that there is no defective portion Can also be remembered. Therefore, by using this defect information, it becomes possible to easily select all other memory cells except for the defective cells.
[0017]
In one embodiment of the present invention, a defective cell can be replaced by a column unit or a row unit, and a column or row including the defective cell can be excluded from the burn-in test.
[0018]
Further, even when the memory cells are configured in units of blocks and the defective cells are replaced in units of blocks, the problem that desired stress is not applied to other normal memory cells due to the influence of the defective cells can be solved.
[0019]
According to one aspect of the present invention, in a method for controlling a semiconductor memory device capable of selecting all memory cells in a memory cell array, a first method of predecoding an address signal input from the outside in units of a plurality of address bits is provided. A step, a second step of predecoding and storing an address for replacing a defective cell in units of the plurality of address bits, and a predecoding result of the first and second steps to be selected and output Based on the output of the third step, the fourth step for final address decoding, the decoding result of the fourth step, and the inverted signal of the decoding result are selected. And a fifth step for outputting, and when all memory cell selection signals instructing selection of all memory cells are input, The third step selects the predecode result of the second step, the fifth step selects an inverted signal of the decode result of the fourth step, and the third step is the first step during normal cell access. While selecting the predecode result of one step, the fifth step selects the decode result of the fourth step.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a semiconductor memory device according to the present invention will be specifically described with reference to the drawings. Hereinafter, a semiconductor memory device capable of performing a burn-in test by simultaneously applying stress to all the memory cells in a state where all the memory cells are selected will be described.
[0021]
FIG. 1 is a block diagram of an embodiment of a semiconductor memory device according to the present invention. FIG. 1 mainly shows a portion for performing address decoding, and other portions are omitted.
[0022]
The semiconductor memory device of FIG. 1 includes an address buffer 1, a first predecoder (first predecode unit) 2, a register circuit 3, a fuse data storage unit (defective information storage unit) 4, a first Multiplexer (first selection means) 5, second predecoder (second predecoding means) 6, inverter (inversion means) 7, second multiplexer (selection means, second selection means) 8 And a memory cell array 9.
[0023]
The address buffer 1 is configured in the same manner as in FIG. 6, and after buffering an address signal input from the outside, outputs two types of positive and negative address signals. The first predecoder 2 predecodes the address signals A0 to An in units of m (m <n) bits. FIG. 2 shows an example in which the address signal is predecoded in units of 3 bits. When decoding is performed in units of 3 bits, 8-bit outputs B0 to B7 are obtained. Only one of these 8 bits is “1”.
[0024]
The decoding result of the first predecoder 2 is latched by the register circuit 3 at a common timing. Thereby, the predecode result of the first predecoder 2 can be synchronized with the clock.
[0025]
On the other hand, the fuse data storage unit 4 stores an address corresponding to the defective portion using a fuse element. Specifically, as in the first predecoder 2, the result of predecoding the address corresponding to the defective portion in units of m bits is stored. The fuse data storage unit 4 stores data of 2 ^m bits in total.
[0026]
If there is a defective part, the bit corresponding to the defective part is set to “1”. Therefore, if there is no defective portion, the fuse data storage unit 4 stores all “0” data.
[0027]
Conventionally, since a fuse element is provided for each bit of an address of a defective portion, a state where no defective portion exists cannot be expressed by a fuse element. For example, when none of the fuse elements is cut, it is considered that the addresses are all “0” or all “1”.
[0028]
On the other hand, in the present embodiment, since the fuse element is assigned to the result of predecoding the address signal, a state where there is no defective portion can be expressed as all “0”.
[0029]
In the present embodiment, the number of fuse elements is increased as compared with the conventional case. However, since the address signal is normally decoded in a plurality of stages, if a fuse element is provided corresponding to the predecode result in the first stage, The number of fuse elements can be reduced to about 2 to 3 times that of the conventional one, and the circuit configuration is not likely to be complicated.
[0030]
In recent high-speed synchronous memory, the result of predecoding the address is stored in a register in advance, and the time for accessing the memory is generally shortened. It is more natural to store the predecoded result, and the system can be unified.
[0031]
The first multiplexer 5 in FIG. 1 selects either the output of the fuse data storage unit 4 or the output of the first predecoder 2 according to the logic of the all memory cell selection signal test. Specifically, the output of the first predecoder 2 is selected during normal operation of the memory (when test is at low level), and fuse data is stored during burn-in test (when test is at high level). Select the output of part 4.
[0032]
The second predecoder 6 performs decoding based on the output of the first predecoder 2 or the output of the fuse data storage unit 4 and outputs a final decode signal.
[0033]
The second multiplexer 8 selects either the output of the second predecoder 6 or its inverted output according to the logic of the all memory cell selection signal test. Specifically, the output of the second predecoder 6 is selected during normal operation of the memory (when the test is at a low level), and the second output is selected during the burn-in test (when the test is at a high level). The inverted output of the predecoder 6 is selected.
[0034]
The output of the second multiplexer 8 is supplied to a column transfer gate in the memory cell array 9. As a result, any one of the column transfer gates is turned on, and the data of the data line pair Din, / Din is supplied to the bit line pair connected to the gate.
[0035]
Although omitted in FIG. 1, a circuit similar to that in FIG. 1 is also provided on the row side. On the row side, any one word line is driven by the output of the second multiplexer 8.
[0036]
FIG. 3 is a circuit diagram showing the internal configuration of the second multiplexer 8. The second multiplexer 8 includes transfer gates 11 and 12 and inverters 13 to 15. The output of the second predecoder 6 is input to the transfer gate 12, and the signal obtained by inverting the output of the second predecoder 6 by the inverter 7 of FIG. 1 is input to the transfer gate 11.
[0037]
If all the memory cell selection signals test are at a high level, the transfer gate 11 is turned on and the output of the inverter 7 is selected. If all the memory cell selection signals test are at a low level, the transfer gate 12 is turned on and the second signal is output. The output of the predecoder 6 is selected.
[0038]
Next, the operation of the semiconductor memory device of FIG. 1 when performing a burn-in test will be described. When performing the burn-in test, all the memory cells in the memory cell array 9 are selected, and all the memory cell selection signals test are at a high level. Therefore, the first multiplexer 5 in FIG. 1 selects the output signal of the fuse data storage unit 4. As described above, the address of the defective part is predecoded and stored in the fuse data storage unit 4.
[0039]
More specifically, the fuse data storage unit 4 stores “1” only for the bit corresponding to the address of the defective part. If there is no defective portion, the fuse data storage unit 4 stores all “0”.
[0040]
The output of the fuse data storage unit 4 is input to the second predecoder 6 via the first multiplexer 5, and final address decoding is performed. As a result, only the address corresponding to the defective part is selected. If no defective part exists anywhere, the output of the second predecoder 6 deselects all addresses.
[0041]
Further, the second multiplexer 8 selects the output of the inverter 7 because the all memory cell selection signal test is at a high level. That is, the second multiplexer 8 deselects the address selected by the second predecoder 6 and selects an address that has not been selected.
[0042]
As a result, only the address corresponding to the defective portion is not selected, and all other addresses are selected. Therefore, a desired stress can be applied to all the other columns except for the column in which a failure has occurred.
[0043]
If the burn-in test is performed in this state, the problem that a desired stress cannot be applied to a normal memory cell due to the influence of a column or word line in which a short circuit failure has occurred as in the prior art does not occur.
[0044]
FIG. 4 is a diagram showing memory access during normal operation of the memory. FIG. 4A shows an example in which replacement with a spare cell is performed because an attempt is made to access a defective cell, and FIG. Shows an example in which the memory cell to be accessed is a non-defective product. FIG. 5 is a diagram showing memory access during a burn-in test. FIG. 5A shows an example in which all cells except for a defective cell are selected, and FIG. 5B shows an example in which no defective cell exists. Show.
[0045]
As described above, according to the present embodiment, the result of predecoding the address of the defective part is stored as fuse data in correspondence with the result of predecoding the address signal input from the outside. Not only can it be replaced, but also the state that no defect exists can be set by the fuse data. Therefore, by using the fuse data, it is possible to apply a desired stress to all the memory cells except the defective portion during the burn-in test.
[0046]
In this embodiment, since the selection of the first and second multiplexers 8 is controlled by the all-cell selection signal test, it is not necessary to separately provide signals for selecting these multiplexers.
[0047]
Further, FIG. 1 shows an example in which the output of the second predecoder 6 is the final decoding result, but the address may be decoded using three or more stages of predecoders. In this case, among the predecoders of three or more stages, the fuse data storage unit 4 of FIG. 1 is provided corresponding to any predecoder other than the final stage, and the inverter 7 of FIG. Just connect.
[0048]
By the way, in recent large-capacity memories, the memory cell array 9 is often divided into a plurality of array blocks. In this case, since a spare cell (spare column or spare row) and a fuse element are provided for each array block, the fuse data storage unit 4 of FIG. 1 may be provided for each block.
[0049]
【The invention's effect】
As described above in detail, according to the present invention, when all memory cell selection signals are input, all other memory cells except for a predetermined range of memory cells including the defective cells are selected. Screening such as burn-in test can be performed. As a result, the problem that the desired stress is not applied to other normal memory cells under the influence of the defective cell does not occur, and the screening reliability is improved.
[0050]
In addition, since the address corresponding to the defective cell is predecoded in units of a plurality of address bits and stored as defective information, not only the address of the defective cell but also information that no defective portion exists is stored. I can leave. Therefore, by using this defect information, it becomes possible to easily select all other memory cells except for the defective cells.
[Brief description of the drawings]
FIG. 1 is a block diagram of an embodiment of a semiconductor memory device according to the present invention.
FIG. 2 is a diagram showing an example in which an address signal is predecoded in units of 3 bits.
3 is a circuit diagram showing an internal configuration of a second multiplexer 8. FIG.
FIG. 4 is a diagram showing memory access during normal operation of the memory.
FIGS. 5A and 5B are diagrams showing memory access during a burn-in test. FIGS.
FIG. 6 is a schematic circuit diagram of a conventional selection control circuit that selects all memory cells in a semiconductor memory.
FIG. 7 is a diagram showing a schematic configuration of a memory cell array in SRAM.
FIG. 8 is a diagram showing an example of a leak path.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Address buffer 2 1st predecoder 3 Register circuit 4 Fuse data memory | storage part 5 1st multiplexer 6 2nd predecoder 7 Inverter 8 2nd multiplexer 9 Memory cell array

Claims (5)

In a semiconductor memory device capable of selecting all memory cells in a memory cell array,
First predecoding means for predecoding an address signal input from outside in units of a plurality of address bits;
A defect information storage means for predecoding and storing an address corresponding to a defective cell in units of the plurality of address bits;
First selection means for selecting and outputting either the predecode result of the first predecode means and the predecode result of the defect information storage means;
Second predecoding means for performing address decoding based on the output of the first selection means;
Inverting means for inverting the output signal of the second predecoding means;
Second selection means for selecting and outputting either the output signal of the second predecoding means or the output signal of the inverting means,
When an all memory cell selection signal instructing selection of all memory cells is input, the first selection means selects a predecode result of the defect information storage means, and the second selection means is the inversion means. When the normal cell access is performed, the first selection means selects the predecode result of the first predecode means, and the second selection means selects the second predecode means. A semiconductor memory device characterized by selecting a decoding result of.   2. The semiconductor memory device according to claim 1, wherein the defect information storage means predecodes and stores addresses for replacing defective cells in units of columns in units of the plurality of address bits.   2. The semiconductor memory device according to claim 1, wherein the defect information storage means predecodes and stores an address for replacing a defective cell in a row unit in units of the plurality of address bits. A memory cell array divided into a plurality of blocks,
The semiconductor memory device according to claim 1, wherein the defect information storage unit stores an address for replacing a defective cell for each block. In a control method of a semiconductor memory device capable of selecting all memory cells in a memory cell array,
A first step of predecoding an externally input address signal in units of a plurality of address bits;
A second step of predecoding and storing an address for replacing a defective cell in units of the plurality of address bits;
A third step of selecting and outputting one of the predecode results of the first and second steps;
A fourth step of performing final address decoding based on the output of the third step;
A fifth step of selecting and outputting one of the decoding result of the fourth step and an inverted signal of the decoding result;
When an all memory cell selection signal instructing selection of all memory cells is input, the third step selects the predecode result of the second step, and the fifth step determines the decode result of the fourth step. When the inverted signal is selected and the normal cell access is performed, the third step selects the predecode result of the first step, and the fifth step selects the decode result of the fourth step. A method for controlling a semiconductor memory device.

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