JP2006107583A - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a semiconductor memory device which does not require redundancy analysis and reduces time and labor for a device test by making failure decision by the device itself. <P>SOLUTION: The semiconductor memory device comprises an MIOT (multi-I/O test) deciding circuit 7 for making failure decision of the predetermined number of memory cells 1a from data read out of the predetermined number of memory cells 1a selected by matrix decoders 4a, 4b, a redundancy storage circuit 8 for storing a defective address decode signal generated by the matrix decoders 4a, 4b at the time of the failure decision, and a redundancy circuit 9 for generating a spare cell selection signal according to collation of the decode signal generated by the matrix decoders 4a, 4b with the defective address decode signal stored in the redundancy storage circuit 8. The semiconductor memory device performs failure decision by itself and thereby eliminates the need for making a redundancy analysis such as the conventional memory array test carried out with a memory tester or the like in a pre-test process, and reduces time and labor for the device test. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor memory device having a redundant configuration for repairing a defective memory cell in a memory cell array by replacing it with a spare cell.

As a conventional semiconductor memory device, there is a semiconductor memory device including a composite memory provided with a memory cell array and a redundant relief address storage memory cell array for storing defective addresses in the memory cell array. In this composite memory, a memory cell array is tested by a memory tester or the like in a pretest process (redundancy analysis). If it is determined that the defect is found in the pretest process and the repair is possible, the defective address to be repaired is written in the memory cell array for storing the redundant repair address. Thereafter, when an address (defective address) in the memory cell array is input, a redundant relief signal is output from the redundant relief address storage memory cell array to the memory cell array, and a spare cell is accessed instead of a normal memory cell in the memory cell array. (See, for example, Patent Document 1).
In addition, when a failure occurs due to burn-in or the like after assembly, or a cell that has not been sufficiently repaired by detecting a failure in a wafer state test, a detailed test after assembly may fail. In this case, it cannot be remedied, resulting in a defective product. In recent years, MCP (multi-chip package) in which a plurality of devices are sealed in one package has been commercialized. In such a product, even if one of the devices in it becomes defective after assembly, even if the other devices mounted on it are non-defective, the product will be defective. Yield is further reduced compared to products with memory.

JP 2002-56690 A

Since the conventional semiconductor memory device is configured as described above, it is necessary to test the memory cell array using a memory tester or the like in the pretest process. Such redundancy analysis takes time in testing the semiconductor memory device. There was a problem.
Also, when testing in the wafer state, if a detailed test or a test with strict test conditions is to be performed, the test cannot be performed over a long time due to productivity, so in the test in the wafer state, A defect cannot be completely detected and repaired. Therefore, there are problems such as a decrease in product yield.

  The present invention has been made to solve the above-described problems. By performing the failure determination by the device itself, it is not necessary to carry out a redundancy analysis, thereby reducing the labor of the device test and making the electric test even after assembly. An object of the present invention is to obtain a semiconductor memory device capable of storing address information to be repaired automatically.

  A semiconductor memory device according to the present invention includes a multi I / O test determination circuit for determining a failure of a predetermined number of memory cells based on data read from the predetermined number of memory cells selected by a decoder, and a multi I / O The redundancy memory circuit that stores the decoded signal generated by the decoder when the failure is determined by the test determination circuit as defective address information, and the decoded signal generated by the decoder and the redundancy memory circuit when the power is turned on A redundancy circuit that generates a spare cell selection signal in accordance with the verification with the defective address information, and the decoder selects a spare cell in the memory cell array according to the decode signal when the spare cell selection signal is generated by the redundancy circuit. The defective memory cell is replaced with a spare cell to rescue it.

  According to the present invention, the multi-I / O test determination circuit for determining the failure of the predetermined number of memory cells based on the data read from the predetermined number of memory cells selected by the decoder is provided. By using the device itself, it is not necessary to perform a redundant analysis, such as testing the memory cell array using a memory tester or the like in the pre-test process as in the prior art. Since a device that becomes defective in a simple test can be repaired by replacing it with a spare cell, the yield can be improved.

Embodiment 1 FIG.
FIG. 1 is a circuit diagram showing a semiconductor memory device according to Embodiment 1 of the present invention. In FIG. 1, a memory cell array 1 is replaced with a plurality of normally used memory cells 1a and when these memory cells 1a are defective. Thus, a spare cell 1b in the row and column directions for relieving the defective memory cell 1a is provided. Although not shown in FIG. 1, the memory cell array 1 is divided into a plurality of redundant blocks each including a plurality of memory cells 1a and spare cells 1b for relieving the plurality of memory cells 1a.
Address input buffer 2 receives external address signal Ext. An is input and an internal address signal is output. The predecoder (decoder) 3 predecodes the internal address signal and generates a predecode signal for selecting one of the redundant blocks divided into a plurality of redundant blocks. The row decoder (decoder) 4a and the column decoder (decoder) 4b decode the internal address signal in a row and a column, and select a corresponding memory cell 1a in the redundant block selected by the predecode signal based on the row and column decode signal. To choose.
The data input / output buffer 5 is connected to the external data I / O signal Ext. The DQn is input / output, and the sense amplifier / write driver 6 adjusts data read from the selected memory cell 1a and data to be written to the selected memory cell 1a to a certain level.

The MIOT determination circuit (multi I / O test determination circuit) 7 uses the output data read from the predetermined number of memory cells 1a selected by the predecoder 3 and the matrix decoders 4a and 4b to set the predetermined number of memory cells 1a. A defect is determined. For example, the same value, “L” or “H”, is written to a plurality of DQ pins in one set in the multi-I / O test of each memory cell 1a to be tested, and a plurality of DQ (data I / O ) Pins are taken as a set, and the exclusive OR (XOR) of the output data is taken, and if they match, it is judged as good (PASS), and if they do not match, it is judged as bad (FAIL). In this example, XOR is performed with 4DQ as one set in a x16 configuration, and the output is MIOT <0-3>.
In addition, the MIOT determination circuit 7 receives an external defect determination timing control signal Ext. It is configured to perform defect determination according to the STRB input. This is a signal for controlling the timing of defect determination, and this pin may be a DU (Don't use) pin.
The detailed configuration of the MIOT determination circuit 7 will be described with reference to FIG.

The redundancy memory circuit 8 stores, as defective address information, a decoded signal to be remedied generated by the predecoder 3 and the matrix decoders 4a and 4b when a defect is determined by the MIOT determination circuit 7.
The redundancy memory circuit 8 is composed of a redundancy latch circuit 8a for temporarily latching a repair enable signal and a defective address decode signal (defective address information), and a repair memory latched by the redundancy latch circuit 8a. The redundancy flash memory 8b stores an enable signal and a defective address decode signal, and the redundancy latch circuit 8a and the redundancy control circuit 8c for controlling the redundancy flash memory 8b. These correspond to the main memory portion and page buffer portion of the conventional flash memory, and control of erasing / reading / writing, etc. to the redundant flash memory 8b may be performed using a general flash memory circuit.
The detailed configuration of the redundancy latch circuit 8a is shown in FIG. 3, the detailed configuration of the redundancy flash memory 8b is shown in FIG. 2, and the detailed configuration of the redundancy control circuit 8c is shown in FIGS. 8 will be described.

The redundant circuit 9 collates the decode signal generated by the predecoder 3 and the matrix decoders 4a and 4b with the defective address decode signal stored by the redundancy storage circuit 8 at power-on, and selects a spare cell if they match. A signal is generated and supplied to the matrix decoders 4a and 4b. On the side of the matrix decoders 4a and 4b to which the spare cell selection signal is input, the matrix decoder for switching the memory cell 1a to the matrix decoder for selecting the spare cell 1b is switched, and the matrix decoder in which the internal address signal is decoded by the switched matrix decoder. The spare cell 1b of the redundant block is selected in place of the memory cell 1a in the redundant block selected by the predecode signal, and the defective memory cell 1a is replaced with the spare cell 1b to rescue. is there.
Redundant circuit 9 also includes a spare use selection signal Ext. Whether or not to replace the spare cell 1b is controlled in accordance with ZSP, and this pin may be a DU (Don't use) pin.
The detailed configuration of the redundant circuit 9 will be described with reference to FIG.

Hereinafter, the details of each configuration will be described.
FIG. 2 is a circuit diagram showing a detailed configuration of the redundancy flash memory. The redundancy flash memory 8b is a repair enable signal and a defective address decode signal held in the redundancy latch circuit 8a during the multi-I / O test. Is memorized. When the memory cell array 1 is used, the stored repair enable signal and defective address decode signal are read out and held in the redundancy latch circuit 8a.

  In the figure, the redundancy flash memory 8b is composed of a flash memory 11 for storing a repair enable signal and a defective address decode signal, and a redundancy sense amplifier 12 for reading it. The word line selection signal of the redundancy flash memory 8b, that is, the redundancy block selection signal FWL <i> is a signal generated by the predecode signal from the predecoder 3. Here, <i> represents a block number. The defective address decode signal ZXE <a> of the redundancy flash memory 8b is a decode signal generated by the matrix decoders 4a and 4b, that is, an address selection signal for replacement with the spare cell 1b, and stores “L”. The spare cell 1b is selected at the address that has been set. Here, <a> represents an address number. This defective address decode signal ZXE <a> is a signal for selecting the bit line of the redundant flash memory 8b. The repair enable signal ZSRE becomes “L” when the redundant set of the redundant block is selected. Here, the redundant set is a set of repair enable signals and defective address decode signals. In FIG. 2, a repair enable signal ZSRE selected (stored) by one redundant block selection signal FWL <i>. And defective address decode signal ZXE <a>. The repair enable signal ZSRE is also a signal for selecting the bit line of the redundancy flash memory 8b.

  FIG. 3 is a circuit diagram showing a detailed configuration of the redundancy latch circuit. The redundancy latch circuit 8a is connected to the repair enable signal ZSRE from the redundancy control circuit 8c shown in FIG. The address decode signal ZXE <a> is held and stored in the redundancy flash memory 8b. Further, when the memory cell array 1 is used, the repair enable signal ZSRE and the defective address decode signal ZXE <a> are read from the redundancy flash memory 8b, held, and output to the redundancy control circuit 8c shown in FIG.

In the figure, the redundancy latch circuit 8a includes an SRAM 21 for holding a repair enable signal ZSRE and a defective address decode signal ZXE <a>, and a latch circuit sense amplifier / write driver 22 for reading and writing. . The bit line of the redundant flash memory 8b is connected.
The redundancy block selection signal SWL <i> of the redundancy latch circuit 8a is a signal generated by a predecode signal from the predecoder 3. One of the signals for selecting the bit line pair of the redundancy latch circuit 8a is the defective address decode signal ZXE <a> of the redundancy flash memory 8b, and the other is its inverted signal. Further, as a signal for selecting the bit line pair of the redundancy latch circuit 8a, one is a repair enable signal ZSRE of the redundancy flash memory 8b, and the other is an inverted signal thereof. These bit line pairs are connected to a latch circuit sense amplifier / write driver 22.

  FIG. 4 is a circuit diagram showing a detailed configuration of the word line drive circuit of the redundancy flash memory and redundancy latch circuit provided in the redundancy control circuit. The word line drive circuit in the redundancy control circuit 8c is shown in FIG. In the multi I / O test, in response to the input of the failure signal SWLNG <m> from the redundancy control circuit 8c shown in FIG. 8, a redundancy block selection signal SWL <m> is output to the redundancy latch circuit 8a. A clocked inverter open / close control signal ZSWLD <m> is output to the redundancy control circuit 8c shown in FIG. When the memory cell array 1 is used, the redundant block selection signal FWL <m> is supplied to the redundant flash memory 8b and the redundant block selection signal SWL <m> is supplied to the redundant latch circuit 8a according to the operation of the counter 32. The clocked inverter open / close control signal ZSWLD <m> is sequentially output to the redundancy control circuit 8c shown in FIG.

  In the figure, a control circuit 31 operates a counter 32 when power is turned on, and the counter 32 activates a redundancy flash memory word line activation signal FWLC <m> and a redundancy latch circuit word line activation according to the count operation. Generates a signal SWLC <m>. The inverter circuits 34 and 35 in the logic circuit 33 receive the redundancy flash memory word line activation signal FWLC <m> and sequentially generate the redundancy block selection signal FWL <m> in the redundancy flash memory 8b. . Here, <m> represents a block number. Further, a NOR circuit 36 in the logic circuit 33 takes NOR with the redundancy latch circuit word line activation signal SWLC <m> and the failure signal SWLNG <m> from the redundancy control circuit 8c shown in FIG. The clocked inverter open / close control signal ZSWLD <m> is output to the redundancy control circuit 8c shown in FIG. Further, the inverter circuit 37 in the logic circuit 33 inverts the output of the NOR circuit 36 and outputs the redundant block selection signal SWL <m> to the redundant latch circuit 8a.

  FIG. 5 is a circuit diagram showing a detailed configuration of the redundant address generating circuit provided in the redundant control circuit. The redundant address generating circuit in the redundant control circuit 8c is determined to be defective during the multi I / O test. In this case, the matrix decode signals from the matrix decoders 4a and 4b are input as defective address decode signals ZXE <ma> and output to the redundancy latch circuit 8a, and the repair enable signal ZSRE <m> is supplied to the redundancy latch circuit 8a. Is output. Further, when the memory cell array 1 is used, the defective address decode signal ZXE <ma> held in the redundancy latch circuit 8a is input and output to the redundancy circuit 9 shown in FIG.

In the figure, a clocked inverter circuit 41 is controlled to open and close by a clocked inverter open / close control signal ZSWLD <m> input from the redundancy control circuit 8c shown in FIG. 4b or the defective address decode signal ZXE <ma> input from the redundancy latch circuit 8a is passed, and the latch circuit 43 inverts and holds the defective address decode signal ZXE <ma> that has passed through the clocked inverter circuit 41. Thus, the data is output to the redundancy latch circuit 8a or the redundancy circuit 9.
The NAND circuit 44 takes a NAND of a signal obtained by inverting the defective signal SWLNG <m> from the redundancy control circuit 8c shown in FIG. 8 through the inverter circuit 45 and the repair enable signal ZSRE <m>, and outputs a clock signal. The inverter circuit 46 is controlled to open / close by the clocked inverter open / close control signal ZSWLD <m> input from the redundancy control circuit 8c and the signal through the inverter circuit 42, and passes the signal obtained by taking the NAND. The inverter circuit 47 inverts the signal through the clocked inverter circuit 46 and outputs a repair enable signal SRE <m> to the redundancy control circuit 8c shown in FIG. The latch circuit 48 inverts and holds the signal through the inverter circuit 47 and outputs the inverted repair enable signal ZSRE <m> to the redundancy latch circuit 8a.

  FIG. 6 is a circuit diagram showing a detailed configuration of the redundant circuit. This redundant circuit is connected to the spare use selection signal Ext. In accordance with ZSP, output of spare cell selection signal ZSPE <m> is disabled. When the memory cell array 1 is used, the defective address decode signal ZXE <ma> input from the redundancy control circuit 8c shown in FIG. 5 is compared with the matrix decode signal X <ma> by the matrix decoders 4a and 4b. If there is a match, spare cell selection signal ZSPE <m> is output to matrix decoders 4a and 4b.

In the figure, a Pch transistor 51 is connected between a power supply and a node N1, and operates in response to a one-shot pulse ZSRPRE. The Pch transistor 52 is connected between the power supply and the node N1, and operates according to the output of the inverter circuit 53 that inverts the potential of the node N1.
One end of the Nch transistor 54 is connected to the node N1, and operates according to the defective address decode signal ZXE <ma> input from the redundancy control circuit 8c shown in FIG. The Nch transistor 55 is connected between the other end of the Nch transistor 54 and the ground, and operates according to the matrix decode signal X <ma> by the matrix decoders 4a and 4b shown in FIG.
The inverter circuit 56 is connected to the output of the inverter circuit 53, and the NAND circuit 57 is connected to the output of the inverter circuit 56 and the predecode signal from the predecoder 3 shown in FIG. The redundant block selection signal SRB <m> for selecting the redundant block is NANDed. The inverter circuit 58 is connected to the output of the NAND circuit 57 and outputs the redundancy activation signal SRF <m> by being inverted.
The NOR circuit 59 receives the power-on signal ZPOR and the spare use selection signal Ext. The inverter circuit 60 is connected to the output of the NOR circuit 59, and its output is connected to the node N2. The Nch transistor 61 is connected between the nodes N2 and N3 and operates according to the redundancy activation signal SRF <m>. The Nch transistor 62 is connected between the power supply and the node N3, and operates according to the operation start signal ZSRPRE. The Nch transistor 63 is connected between the power supply and the node N3, and operates according to the potential of the node N4 obtained by inverting the potential of the node N3 by the inverter circuit 64. The NAND circuit 65 takes the NAND of the potential of the node N4 and the decoder operation start signal DECE, and this output is output to the matrix decoders 4a and 4b as the spare cell selection signal ZSPE <m>.
The redundant circuit shown here is an example, and the redundant circuit is not limited to this circuit, and a logic equivalent to that obtained by cutting the fuse by the logic of the defective address decode signal ZXE <ma> can be obtained. Any redundant circuit may be used as long as it is such a circuit.

  FIG. 7 is a circuit diagram showing a detailed configuration of the MIOT determination circuit. The MIOT determination circuit 7 determines whether or not the result of the test of the memory cell 1a is defective during the multi-I / O test. The determination result signal CHK indicating the failure determination timing control signal Ext. In response to the STRB, it is output to the redundancy control circuit 8c shown in FIG. Further, when the memory cell array 1 is used, the operation is disabled according to the test mode activation signal TMRE.

  In the figure, the NAND circuit 71 includes a failure determination timing control signal Ext. The STRB and the test mode activation signal TMRE are NANDed, and the inverter circuit 72 is connected to the output of the NAND circuit 71. The NOR circuit 73 takes the NOR of the MIOT determination signals MIOT <0> and MIOT <1>, and the NOR circuit 74 takes the NOR of the MIOT determination signals MIOT <2> and MIOT <3>. The NAND circuit 75 takes NAND of outputs of the NOR circuits 73 and 74. The NAND circuit 76 takes NAND of the output of the inverter circuit 72 and the output of the NAND circuit 75, and the NAND circuit 77 outputs the output of the NAND circuit 76 and the output of the NAND circuit 76 through the delay circuit 78. NAND is taken and a determination result signal CHK is output.

  FIG. 8 is a circuit diagram showing a detailed configuration of the failure signal generation circuit provided in the redundancy control circuit. The failure signal generation circuit in the redundancy control circuit 8c is subjected to MIOT determination during the multi I / O test. In response to the determination result signal CHK from the circuit 7, the defect signal SWLNG <m> is output to the redundancy control circuit 8c shown in FIGS.

  In the figure, the NAND circuit 81 takes NAND of the repair enable signal SRE <m> from the redundancy control circuit 8c shown in FIG. 5 and the repair enable signal SRE <m> through the delay circuit 82, and repair enable inversion. The signal SRED <m> is output. The NAND circuit 83 selects the determination result signal CHK from the MIOT determination circuit 7 and the predecode signal from the predecoder 3 shown in FIG. 1, that is, a redundant block selection for selecting any one of the redundant blocks. The NAND of the signal SRB <m> and the repair enable inversion signal SRED <m> output from the NAND circuit 81 is taken. The NOR circuit 84 takes a NOR between the output of the NAND circuit 83 and the redundant activation signal SRF <m> from the redundant circuit 9 and outputs a failure signal SWLNG <m>.

Next, the operation will be described.
First, the operation in the case where a test is performed and a failure occurs after entering this test mode will be described.
When entering this test mode, a multi I / O test is performed. First, the same value, “L” or “H”, is written to a plurality of DQ pins that form one set in the multi-I / O test of each memory cell 1a to be tested in FIG. Next, the external address signal Ext. In response to An, the predecoder 3 generates a predecode signal for selecting any one of the plurality of redundant blocks, and the matrix decoders 4a and 4b determine the redundancy block selected by the predecode signal. A matrix decode signal for selecting a corresponding memory cell 1a is generated, output data from the memory cell 1a corresponding to the generated decode signal is read, and a match or mismatch of a plurality of read data is determined. It is.

The MIOT determination circuit 7 shown in FIG. 7 is a circuit that determines the result of the test of the memory cell 1a and generates a determination result signal CHK indicating whether or not the memory cell 1a is defective. In the MIOT determination circuit 7, MIOT determination signals MIOT <0-3> are input to NOR circuits 73 and 74, respectively. In the MIOT determination signal MIOT <0-3>, when a failure occurs, the MIOT determination signal MIOT <0-3> corresponding to the defective data becomes “H”, and the output is input to the NAND circuit 75. The output is input to the NAND circuit 76. That is, the output of the NAND circuit 75 is an OR of the MIOT determination signal MIOT <0-3>, and if any of the MIOT determination signals MIOT <0-3> is defective. The output of the NAND circuit 76 becomes “H”.
In addition, when the MIOT test mode is entered and the test mode is entered, the test mode activation signal TMRE becomes “H”, and the “H” pulse is defective at the timing at which it is desired to determine the test result from the outside. Determination timing control signal Ext. STRB is input. At this time, the output of the NAND circuit 71 changes from “H” to “L”, the “L” output is inverted by the inverter circuit 72, and “H” is input to the NAND circuit 76.
Further, the output of the NAND circuit 76 is input to the NAND circuit 77 directly or through the delay circuit 78, and the determination result signal CHK is output. In other words, when a defect occurs, the MIOT determination signal MIOT <0-3> corresponding to the defective data becomes “H”, and the defect determination timing control signal Ext. The determination result signal CHK of the “H” pulse is output at the STRB timing. The determination result signal CHK activates the redundancy latch circuit 8a. The delay time of the delay circuit 78 is the word of the redundancy latch circuit 8a for writing defective address information to the redundancy latch circuit 8a. What is necessary is just to set to the time equivalent to the time which activates a line. The determination result signal CHK is output to the redundancy control circuit 8c shown in FIG.

The defective signal generation circuit in the redundancy control circuit 8 c shown in FIG. 8 is “H” through the NAND circuit 83 and the NOR circuit 84 in response to the input of the determination result signal CHK of the “H” pulse from the MIOT determination circuit 7. A defect signal SWLNG <m> of a pulse (defective at “H”) is output to the redundancy control circuit 8c shown in FIGS.
At this time, the redundant block selection signal SRB <m> is set to “H” by the predecoder 3 and the redundant set of the redundant latch circuit 8a shown in FIG. 3 is not used yet, so the “L” repair enable signal SRE <M> is input, and is delayed by the NAND circuit 81 and the delay circuit 82, whereby the “H” repair enable inversion signal SRED <m> is input. Further, the redundancy activation signal SRF <m> of “L” is input from the redundancy circuit 9 of FIG.
Other than the above signal values, the defective signal SWLNG <m> of the “H” pulse is not generated. In particular, when the redundancy set of the redundancy latch circuit 8a shown in FIG. 3 is used, the repair enable signal ZSRE <m> input to the redundancy control circuit 8c shown in FIG. Therefore, the “H” repair enable signal SRE <m> is input to the redundancy control circuit 8 c shown in FIG. 8, and therefore the “H” pulse defect signal SWLNG <m> will be generated.

In the word line driving circuit of the redundancy latch circuit 8a in the redundancy control circuit 8c shown in FIG. 4, the redundancy block selection of the redundancy latch circuit 8a is performed by the defective signal SWLNG <m> of the “H” pulse from FIG. Signal SWL <m> is activated (“H”) to drive the word line of redundancy latch circuit 8a shown in FIG. The clocked inverter open / close control signal ZSWLD <m> is also activated (“L”). This signal is output in FIG.
In the redundant address generation circuit in the redundancy control circuit 8c shown in FIG. 5, the clocked inverter circuit 41 is opened by the “L” clocked inverter open / close control signal ZSWLD <m> input from FIG. The defective address decode signal ZXE <ma> input from the decoders 4a and 4b is passed, held in the latch circuit 43, output to the redundancy latch circuit 8a, and the redundancy block selection of the redundancy latch circuit 8a from FIG. 4 is selected. The redundancy set activated by the signal SWL <m> is held by the latch circuit sense amplifier / write driver 22. At this time, the clocked inverter circuit 46 is also opened, and the “L” repair enable signal ZSRE <m> is output to the redundancy latch circuit 8a and held in the redundancy latch circuit 8a. The retention of the “L” repair enable signal ZSRE <m> indicates that the redundant set in the block number <m> has been used. In the first embodiment, the redundant block and the redundant set are in one-to-one correspondence, and when one redundant set is used, the redundant set can no longer be used in the redundant block. In the circuit diagram of FIG. 8, the repair enable signal SRE <m> from FIG. 5 is input, and the repair enable signal SRE <m> becomes “H”, so that the defect signal SWLNG <m> is “L” (defective signal). This is forbidden to use any more redundant sets.

In the redundant circuit 9 shown in FIG. 6, the defective address decode signal ZXE <ma> from the redundant control circuit 8c shown in FIG. 5 is inputted to the Nch transistor 54, and the Nch transistor 55 shown in FIG. Since the matrix decode signals X <ma> from the matrix decoders 4a and 4b are input and they match, the redundant activation signal SRF <m> is set to “H”. However, in the multi I / O test, spare use selection is performed. Signal Ext. Due to the “H” input of ZSP, the output of spare cell selection signal ZSPE <m> remains (“H” invalid).
In FIG. 3, if the defective address decode signal ZXE <ma> and the repair enable signal ZSRE <m> are held in the redundancy latch circuit 8a, then the redundancy latch circuit is activated by a command before turning off the power. If the defective address decode signal ZXE <ma> and the repair enable signal ZSRE <m> held in 8a are written into the redundant flash memory 8b in FIG. 2, the defective address decode is performed when the power is turned on next time. The signal ZXE <ma> and the repair enable signal ZSRE <m> can be restored.

An operation when the memory cell array 1 is used will be described.
In the word line drive circuit of the redundancy latch circuit 8a in the redundancy control circuit 8c shown in FIG. 4, when the power is turned on, the control circuit 31 operates the counter 32, and periodically starts “H” in order from the counter 32. "Redundancy flash memory word line activation signal FWLC <m>" and redundancy latch circuit word line activation signal SWLC <m> are generated. These signals become “H” redundant block selection signals FWL <m> and SWL <m> through the logic circuit 33. The redundant block selection signal FWL <m> sequentially drives the word lines of the redundancy flash memory 8b shown in FIG. 2, and the redundancy sense amplifier 11 writes the defective address written in the redundancy flash memory 8b. Decode signal ZXE <ma> is read in order. Next, the word lines of the redundancy latch circuit 8a shown in FIG. 3 for selecting the same redundancy block are sequentially driven by the redundancy block selection signal SWL <m>, and these defective address decode signals are sent to the redundancy latch circuit 8a. ZXE <ma> is written in order. The clocked inverter open / close control signal ZSWLD <m> is also activated ("L") in order. This signal is output to the circuit of FIG.

  In the redundant address generation circuit in the redundancy control circuit 8c shown in FIG. 5, the clocked inverter circuit 41 is opened by the “L” clocked inverter open / close control signal ZSWLD <m> input from FIG. The defective address decode signal ZXE <ma> read from the redundancy latch circuit 8a shown in FIG. 3 is passed and held in the latch circuit 43. The defective address decode signal ZXE <ma> is stored in the redundancy circuit shown in FIG. The address to be relieved is determined by this logic.

In the redundant circuit 9 shown in FIG. 6, at the start of operation, an “L” one-shot pulse ZSRPRE is input to the Pch transistor 51, and the node N1 is precharged to “H”. Further, when the potential of the node N1 is “H”, the Pch transistor 52 is continuously turned on according to the output of the inverter circuit 53, so that the Nch transistors 54 and 55 are turned off. This prevents the potential of the node N1 from becoming “L” due to the leakage of the current.
Defective address decode signal ZXE <ma> from redundancy control circuit 8c shown in FIG. In FIG. 1, the input external address signal Ext. In response to An, the predecoder 3 generates a predecode signal for selecting any one of the plurality of redundant blocks, and the matrix decoders 4a and 4b determine the redundancy block selected by the predecode signal. The matrix decode signal X <ma> for selecting the corresponding memory cell 1a is generated, and the matrix decode signal X <ma> is input to the Nch transistor 55.
Since the circuit diagram shown in FIG. 6 is provided for the number of blocks <m>, a defective address decode signal ZXE <ma> corresponding to each block number <m> is supplied to the Nch transistor 54 of each circuit as shown in FIG. 1 and the Nch transistors 55 of all the circuits are supplied to the external address signal Ext. The matrix decode signals X <ma> by the An matrix decoders 4a and 4b are sequentially input. By connecting these Nch transistors 54 and 55 in series, the decoded signal of the currently input address is collated with the defective address information that has previously failed due to the multi I / O test. Here, if the result of collation between the defective input decode signal ZXE <ma> that is held and input and the matrix decode signal X <ma> that is sequentially input do not match, at least one of the number of bits <a>. Since the two Nch transistors 54 and 55 are both turned on, the potential of the node N1 becomes “L”. At this time, the operation is performed so that the normal memory cell 1a is selected. On the other hand, in the case of coincidence, all the Nch transistors 54 and 55 in the bit number <a> are not both turned on, and the potential of the node N1 is maintained at “H”. This is the same state as the fuse being blown in the redundant circuit. At this time, the operation is performed so that the spare cell 1b is selected.

The potential of the node N1 is input to the NAND circuit 57 through the inverter circuits 53 and 56, and the other NAND circuit 57 has a predecode signal from the predecoder 3 shown in FIG. A redundant block selection signal SRB <m> for selecting any redundant block is input. In the Nch transistors 54 and 55, defective address information, that is, a redundant set is collated, but here, a redundant block is collated.
When the defective address information matches and the redundant block matches, the Nch transistor 61 outputs the “H” redundancy activation signal SRF <m>, and otherwise, the “L” redundancy activation signal. Signal SRF <m> is output.

The Nch transistor 62 is supplied with the “L” operation start signal ZSRPRE and precharges the potential of the node N3 to “H”. Further, when the potential of the node N3 is “H”, the Pch transistor 63 is continuously turned on according to the output of the inverter circuit 64, so that the Nch transistor 61 is turned off even though the Nch transistor 61 is turned off. This prevents the potential of the node N3 from becoming “L”. The power-on signal ZPOR is “L” when the power is turned on, and the spare use selection signal Ext. ZSP is a signal for selecting whether or not the replacement to the spare cell 1b is performed at the time of the test, and is a signal that becomes “L” when the replacement to the spare cell 1b is performed. Therefore, the power is turned on and the spare use selection signal Ext. When the replacement to the spare cell 1b is selected by ZSP, the potential of the node N2 becomes “L”.
Therefore, when the redundancy activation signal SRF <m> is “H”, the Nch transistor 61 is turned on, the node N2 becomes “L” due to “L” of the node N2, and the node N4 becomes “L” via the inverter circuit 64. H ”.
The decoder operation start signal DECE is an external address signal Ext. This signal is “H” before An is switched and the predecoder 3 and the matrix decoders 4a and 4b operate. Therefore, when the decoder operation start signal DECE becomes “H”, the spare cell selection signal ZSPE <m> becomes “L” (replaced with a spare cell by “L”).

  The spare cell selection signal ZSPE <m> is output to the matrix decoders 4a and 4b shown in FIG. 1, and on the side of the matrix decoders 4a and 4b to which the “L” spare cell selection signal ZSPE <m> is input, The matrix decoder that selects 1a is switched to the matrix decoder that selects spare cell 1b. The switched matrix decoder decodes the internal address signal again, and the matrix decoded signal causes the redundant block selected by the predecode signal to be decoded. The spare cell 1b of the redundant block is selected instead of the internal memory cell 1a, and the defective memory cell 1a is replaced with the spare cell 1b to be rescued.

As described above, according to the first embodiment, failure determination of a predetermined number of memory cells 1a based on output data read from a predetermined number of memory cells 1a selected by predecoder 3 and matrix decoders 4a and 4b. Since the MIOT determination circuit 7 is provided, the failure determination is performed by the semiconductor memory device itself, so that it is not necessary to perform redundancy analysis such as testing the memory cell array by a memory tester or the like in the pretest process as in the prior art. It is possible to reduce the labor of the device test.
Further, even after assembly, the spare cell 1b can be replaced and repaired, so that the yield can be improved.
Further, the MIOT determination circuit 7 is connected to an external defect determination timing control signal Ext. Since the defect determination is performed in accordance with the STRB input, the timing of the defect determination can be controlled by an external signal.
Further, redundant circuit 9 receives spare use selection signal Ext. Since whether or not to replace spare cell 1b is controlled according to ZSP, whether or not to perform redundancy can be controlled by an external signal.

Embodiment 2. FIG.
In the first embodiment described above, one redundant set is provided for one redundant block, but in this second embodiment, a plurality of redundant sets are provided for one redundant block. The configuration will be described.
FIG. 9 is a circuit diagram showing a detailed configuration of the failure signal generation circuit provided in the redundancy control circuit according to the second embodiment of the present invention, and instead of the circuit diagram shown in FIG. 8 in the first embodiment. Is provided. In this signal name, R is a row redundant signal name, the redundant block in the row direction is divided into <m> pieces, and one redundant block has i redundant sets. .
The defective signal generation circuit in the redundancy control circuit 8c checks an unused redundant set among the i redundant sets according to the determination result signal CHK from the MIOT determination circuit 7 during the multi I / O test. The defective signals SWL1 <m> to SWLi <m> are sequentially output using unused redundant sets, and further, the redundancy disabled signal ZSRNG is output when there is no unused redundant set.

In the figure, a NAND circuit 91 includes a determination result signal CHK from the MIOT determination circuit 7 shown in FIG. 7 and a predecode signal from the predecoder 3 shown in FIG. 1, that is, any one of a plurality of redundant blocks. This is a NAND of a redundant block selection signal SRB <m> for selecting a redundant block and a repair enable inverted signal SRED <m> obtained by delaying the repair enable signal SRE <m>. The NOR circuit 920 takes a NOR between the output signal of the NAND circuit 91 and the redundant activation signal SRF <m> from the redundant circuit 9, and outputs a redundant signal GSWL <m>. NAND circuit 931 takes NAND of redundant signal GSWL <m> and repair enable signal ZSRE1 <m>, and inverter circuit 941 inverts the output of NAND circuit 931 and outputs defective signal SWL1 <m>. It is.
The NOR circuits 921 to 92i-1 output SWLF1 <m> to SWLFi-1 <m> obtained by inverting the outputs of the NAND circuits 931 to 93i-1 by the inverter circuits 951 to 95i-1, and the repair enable signal ZSRE1 <m>. ~ ZSREi-1 <m> is taken, and the NAND circuits 932-93i are the outputs of the NOR circuits 921-92i-1, the redundant signal GSWL <m>, and the repair enable signals ZSRE2-ZSREi <m>. Taking the NAND, the inverter circuits 942 to 94i invert the outputs of the NAND circuits 932 to 93i and output defective signals SWL2 to SWLi <m>. The NAND circuit 96 takes the NAND of the output of the NAND circuit 93i and the redundancy signal GSWL <m> and outputs the redundancy disable signal ZSRNG.
In other circuits, for example, in the redundancy flash memory shown in FIG. 2 and the redundancy latch circuit shown in FIG. 3, a plurality of redundancy sets can be used for one redundancy block. It is assumed that a plurality of redundant sets are provided for one redundant block.

Next, the operation will be described.
As in FIG. 8, the NAND circuit 91 receives the determination result signal CHK, the redundant block selection signal SRB <m>, and the repair enable inversion signal SRED <m>, and the NOR circuit 920 receives the redundant circuit 9 from the redundant circuit 9. Redundant activation signal SRF <m>. The output of the NOR circuit 920 is a redundancy signal GSWL <m>, which indicates that redundancy must be performed with “H”, and this redundancy signal GSWL <m> is output to the NAND circuits 931 to 93i. . The other inputs of the NAND circuits 931 to 93i are repair enable signals ZSRE1 to ZSREi <m>. Therefore, when the redundancy signal GSWL <m> is “H” and the repair enable signal ZSRE1 <m> is “H”, that is, when the redundancy set 1 is not yet used, the failure signal SWL1 <m> is It becomes “H”, and redundancy is performed by the redundancy set 1.
Conversely, when the repair enable signal ZSRE1 <m> is “L”, that is, when the redundant set 1 is already in use, the signal SWLF1 <m> through the inverter circuit 951 becomes “L”. The signal SWLF1 <m> is input to the NOR circuit 921, and the other input of the NOR circuit 921 is a repair enable signal ZSRE1 <m>. Therefore, when the signal SWLF1 <m> is “L” and the redundant activation signal ZSRE1 <m> is “L” (redundant set 1 is already used), the output of the NOR circuit 921 becomes “H”. This signal is input to the NAND circuit 932, and whether or not redundancy is performed by the redundancy set 2 is determined by the logic of the repair enable signal ZSRE2 <m>. When redundancy is performed, the failure signal SWL2 <m> becomes “H” and redundancy is performed by the redundancy set 2.
In this way, a redundant set that can be redundant in turn is examined. When the i-th redundant set is already used, the repair enable signal ZSREi <m> becomes “L”, so that the NAND circuit 93 i outputs the signal SRNG of “H”. Is output from the redundancy disable signal ZSRNG of “L”, indicating that redundancy cannot be performed anymore.

  As described above, according to the second embodiment, in the redundant memory circuit 8, when a plurality of redundant sets are provided for one redundant block, they are used for the plurality of redundant sets. Since no redundant sets are selected in order and the defective address information is stored, a plurality of redundant sets can be used effectively.

Embodiment 3 FIG.
In a general memory cell array, a plurality of sets of spare cells in the row direction and spare cells in the column direction are provided. When redundancy is not performed in the row direction, redundancy is performed by a spare cell in the column direction. In the third embodiment, a configuration in which redundancy is performed in the row direction when redundancy is performed in the row priority and the redundancy cannot be performed in the row direction will be described.
FIG. 10 is a circuit diagram showing a detailed configuration of a defective signal generation circuit provided in the redundancy control circuit according to the third embodiment of the present invention. In FIG. 10, the signal name C is a column redundancy signal name. The redundant blocks in the column direction are divided into n, and one redundant block has j redundant sets. This circuit tries to use the redundant set in the column direction after all the redundant set in the row direction is used. The difference from FIG. 9 is that the NOR circuit 920 has three inputs, and the remaining one input signal is the redundancy disable signal ZSRNG in FIG. That is, the defective address is not yet redundant in the column direction, the redundancy activation signal SCF <n> is “L”, and all the row redundancy sets are used, and the redundancy disable signal ZSRNG is “L”. Then, the redundancy signal GSCWL <n> becomes “H” depending on the use status of the column redundancy set. A redundant set in the column direction is selected by the same logic as in FIG.

Depending on the test item, it may be better to perform redundancy with column priority. In such a case, it may be possible to select which row / column is prioritized for redundancy by using a circuit as shown in FIG.
FIG. 11 is a circuit diagram showing a detailed configuration of a row / column priority redundancy selection circuit provided in the redundancy control circuit according to the third embodiment of the present invention. In the figure, NAND circuit 111 is a column redundancy redundancy circuit. NAND of the disabling signal ZSCNG and the row priority selection signal ZTMSRF is taken, and the inverter circuit 112 outputs a row redundancy circuit activation signal ZSCNGD with its output inverted. The NAND circuit 113 takes the NAND of the row redundancy redundancy disable signal ZSRNG and the column priority selection signal ZTMSCF, and the inverter circuit 114 outputs a column redundancy circuit activation signal ZSRNGD in which the output is inverted. .

A case will be described in which repair with row priority or column priority is selected according to the test mode.
In this case, the redundancy disable signal ZSRNG input to the column priority defective signal generation circuit of FIG. 10 is replaced with the column redundancy circuit activation signal ZSRNGD generated in FIG. To make the column-priority defect signal generation circuit of FIG. 10 a row-priority defect signal generation circuit, the signal names shown in FIG. 10 are changed from C → R, n → m, j → i, ZSRNG (ZSRNGD) → ZSCNGD. What should I do?
When a mode for repairing with column priority is selected in the test mode, a column priority selection signal ZTMSCF is input instead of ZSRNG in FIG. At this time, the logic of the NOR circuit 920 in FIG. 10 is equivalent to the logic of the NOR circuit 920 in FIG. 9, and the column redundancy set is selected according to the use situation by the same logic as described in FIG. When all the column redundancy sets are used and redundancy in the column direction can no longer be performed, the column redundancy redundancy disable signal ZSCNG becomes “L”. When the column redundancy redundancy disable signal ZSCNG becomes "L", the row redundancy circuit activation signal ZSCNGD becomes "L" by the circuit of FIG. This signal is input to the row-priority defective signal generation circuit in which the signal name is replaced in the circuit of FIG. 10, and the row redundancy set is selected according to the use situation by the same logic as described in FIG. . As described above, the column priority selection signal ZTMSCF is set to “L” in the mode in which the column priority is repaired in the test mode, and redundancy is performed with the column priority. Further, the row priority selection signal ZTMSRF is set to “L” in the mode in which the repair is performed with the row priority in the test mode, and the redundancy is performed with the column priority.

  When the row priority redundancy disable signal ZSRNG and the column priority redundancy disable signal ZSCNG are both "L", that is, a plurality of redundant sets are all used, and newly generated defective address information is stored. Therefore, specific data may be output from the DU pin or the DQ pin that is not used as the input / output DU pin in the multi I / O test mode.

As described above, according to the third embodiment, the memory cell array 1 is provided with a plurality of spare cells in the row direction and a plurality of spare cells in the column direction. In the redundancy memory circuit 8, row priority redundancy or column priority redundancy is selected in accordance with a row / column priority selection signal when the column priority redundancy using the spare cells in the column direction can be selected. Therefore, the spare cell can be used effectively and conveniently.
In addition, in the redundancy memory circuit 8, when all of the plurality of redundancy sets are used and the newly generated defective address information cannot be stored, a redundancy disable signal is output to the outside. By outputting the failure signal, it is possible to determine that the newly generated defective address information cannot be stored, that is, a defective product.

Embodiment 4 FIG.
In the first to third embodiments, when a failure is determined by the multi I / O test, the defective address decode signal is stored in the redundant storage circuit 8. In the fourth embodiment, the failure determination is performed from the outside. A signal (command) to be input is input, and an address decode signal by the matrix decoders 4a and 4b when the defect determination signal is input is stored as defect address information.
An external CHK signal pin and an input buffer are provided so that a signal corresponding to the determination result signal CHK shown in FIG. 8 can be input from the outside so that the signal can be input as CHK in FIG. By doing so, the address decode signal inputted at this time is written into the redundancy latch circuit 8a. At this time, if the redundant set is already used up, the repair cannot be performed as in the second and third embodiments. At this time, the determination may be made by outputting specific data from the DU pin or the DQ pin which is not used in the multi I / O test mode. Further, by releasing this command to the user, it may be possible to relieve the memory cell 1a which has become defective after being mounted on the actual machine.

  As described above, according to the fourth embodiment, the redundancy memory circuit 8 receives a signal corresponding to a defect determination from the outside, and is generated by the matrix decoders 4a and 4b when the defect determination signal is input. Since the decoded address decode signal is stored as defective address information, any address can be replaced with the spare cell 1b by inputting a defect determination signal from the outside.

Embodiment 5. FIG.
In the fifth embodiment, the redundant circuit 9 outputs a defect collation signal in the case of a defective address to the outside in accordance with the collation between the decode signal generated by the matrix decoders 4a and 4b and the defect address decode signal. It is.
In this case, when the test mode is entered, a failure verification signal obtained by ORing a signal corresponding to the redundancy activation signal SRF <m> shown in FIG. 6 may be output from the DQ pin. The expected value of this output is set to “L” and a test is performed for determination. When the address replaced with the spare cell 1b is selected, the redundancy activation signal SRF <m> becomes “H”. Therefore, it can be seen that the address which has become defective in the test is the address replaced with the spare cell 1b.
The defect verification signal may be output when the memory cell 1a is replaced with the spare cell 1b during normal use, not in the test mode. In this case as well, the redundancy shown in FIG. A defect verification signal obtained by ORing a signal corresponding to the activation signal SRF <m> may be output from the DQ pin.

  As described above, according to the fifth embodiment, in redundant circuit 9, in accordance with the collation between the decode signal generated by matrix decoders 4a and 4b and the defect address decode signal, the defect verification in the case of a defective address. Since the signal is output to the outside, it can be determined that the address input when the defect verification signal is output is the address replaced with the spare cell 1b.

Embodiment 6 FIG.
In the sixth embodiment, the access to the memory cell array 1 is performed after the power is turned on, after the defective address decode signal is read from the redundancy memory circuit 8, verified in the redundancy circuit 9, and replaced with the spare cell 1b. It is allowed after the passage.
In general, after power is turned on, it takes some time until data is read from the redundant memory circuit 8 and the redundant circuit 9 can be replaced with the spare cell 1b. Therefore, it is necessary to access after a sufficient time has passed after the power is turned on. A counter is provided to output a signal indicating that the logic of the redundant circuit 9 has been determined and the data can be accessed since the last word line for driving the redundant memory circuit 8 is driven. Also good. For example, a method of outputting specific data from the R / B pin or DQ pin, which is performed after erasing / programming in a general flash memory, may be performed.

  As described above, according to the sixth embodiment, after the power is turned on, the defective address decode signal is read from the redundant memory circuit 8 and verified in the redundant circuit 9 to access the spare cell 1b. Since it is permitted after the time when the replacement becomes possible, malfunction due to early access after power-on can be prevented.

Embodiment 7 FIG.
In the seventh embodiment, the MIOT determination circuit 7 uses the logic of the higher address that is not used as the column address in the address multiplex product for applying the DQ combination, and performs the test using the DQ combination. It is a thing.
When a test using a DQ combination is to be performed, in a normal multi I / O test, since a failure is determined by XOR of 4DQ data, the DQ combination cannot be applied. There are the following techniques for applying a DQ combination in a multi I / O test. In an address multiplex product such as a DRAM, the logic of an upper address that is not used as a column address is used for applying a DQ combination to invert the logic of an internal signal of a specific DQ. When writing, the logic of the input DQ is inverted by the write data bus and written to the memory cell. At the time of reading, it is inverted by the read data bus and XORed with 4DQ. By doing so, the DQ combination can be applied even in the multi I / O test. For products that are not address multiplexed, such as OE and LB / UB, a signal that can be tested from the outside even if it is fixed to “L”. L ”is activated and the external signal is used to apply the DQ combination to invert the logic of the internal signal of a specific DQ. By using in combination with such a technique, it is possible to detect a defect and perform replacement with a spare memory cell even in a test in which a DQ combination is applied.

  As described above, according to the seventh embodiment, since the MIOT determination circuit 7 performs the test with the DQ combination, it is possible to determine the defect of the memory cell even in the test with the DQ combination. it can.

Embodiment 8 FIG.
In the eighth embodiment, in the redundant memory circuit 8, the stored repair enable signal and defective address decode signal are erased in response to the defective address information erase signal input from the outside.
In this way, a function that can clear redundant information may be provided by a command. The command enables the data in the redundant flash memory 8b to be erased. Since the flash memory cannot be set to “H” unless it is erased once “L” is written, this function may be provided when it is desired to rewrite redundant information.

  As described above, according to the eighth embodiment, the redundancy memory circuit 8 erases the stored repair enable signal and defective address decode signal in accordance with the defective address information erase signal input from the outside. Therefore, when it is desired to rewrite defective address information, the stored defective address information can be erased and rewritten.

1 is a circuit diagram showing a semiconductor memory device according to a first embodiment of the present invention. It is a circuit diagram which shows the detailed structure of the flash memory for redundancy. FIG. 3 is a circuit diagram showing a detailed configuration of a redundancy latch circuit. FIG. 3 is a circuit diagram showing a detailed configuration of a word line driving circuit of a redundancy flash memory and a redundancy latch circuit provided in the redundancy control circuit. FIG. 3 is a circuit diagram showing a detailed configuration of a redundant address generation circuit provided in a redundancy control circuit. It is a circuit diagram which shows the detailed structure of a redundant circuit. It is a circuit diagram which shows the detailed structure of a MIOT determination circuit. It is a circuit diagram which shows the detailed structure of the defect signal generation circuit provided in the control circuit for redundancy. It is a circuit diagram which shows the detailed structure of the defect signal generation circuit provided in the redundancy control circuit by Embodiment 2 of this invention. It is a circuit diagram which shows the detailed structure of the defect signal generation circuit provided in the control circuit for redundancy by Embodiment 3 of this invention. It is a circuit diagram which shows the detailed structure of the row / column priority redundancy selection circuit provided in the redundancy control circuit by Embodiment 3 of this invention.

Explanation of symbols

  1 memory cell array, 1a memory cell, 1b spare cell, 2 address input buffer, 3 predecoder (decoder), 4a row decoder (decoder), 4b column decoder (decoder), 5 data input / output buffer, 6 sense amplifier / write driver, 7 MIOT determination circuit (multi I / O test determination circuit), 8 redundancy memory circuit, 8a redundancy latch circuit, 8b redundancy flash memory, 8c redundancy control circuit, 9 redundancy circuit, 11 flash memory, 12 redundancy sense Amplifier, 21 SRAM, 22 Sense amplifier / write driver for latch circuit, 31 Control circuit, 32 Counter, 33 Logic circuit, 34, 35, 37, 42, 45, 47, 53, 56, 58, 60, 64, 72, 112, 114, 941-94i, 951, 952 Barter circuit, 36, 59, 73, 74, 84, 920 to 92i-1 NOR circuit, 41, 46 clocked inverter circuit, 43, 48 latch circuit, 44, 57, 65, 71, 75 to 77, 81, 83 , 91, 96, 111, 113, 931 to 93i NAND circuit, 51, 52, 62, 63 Pch transistor, 54, 55, 61 Nch transistor, 78, 82 delay circuit.

Claims (10)

A memory cell array comprising a plurality of memory cells and spare cells for relieving the plurality of memory cells;
A decoder that decodes an address signal and selects a memory cell in the memory cell array according to the decoded signal;
A multi I / O test determination circuit for determining a failure of the predetermined number of memory cells based on data read from the predetermined number of memory cells selected by the decoder;
A redundancy memory circuit comprising a non-volatile memory, and storing a decode signal generated by the decoder when a failure is determined by the multi I / O test determination circuit as defective address information;
A redundant circuit that generates a spare cell selection signal in response to collation between the decoded signal generated by the decoder and the defective address information stored by the redundant memory circuit when the power is turned on;
The decoder includes selecting a spare cell in the memory cell array according to the decode signal when the spare cell selection signal is generated by the redundancy circuit, and replacing the defective memory cell with a spare cell to rescue the spare cell. Semiconductor memory device. The multi I / O test judgment circuit
2. The semiconductor memory device according to claim 1, wherein the defect determination is performed in response to an input of an external defect determination timing control signal. The redundant circuit
3. The semiconductor memory device according to claim 1, wherein whether or not to replace a spare cell is controlled in accordance with a spare use selection signal input from the outside. Memory cell array
Divided into a plurality of redundant blocks consisting of a plurality of memory cells and spare cells for relieving the plurality of memory cells,
Redundant memory circuit
In the case where a plurality of redundant sets are provided for one redundant block, a redundant set that is not used for the plurality of redundant sets is sequentially selected and defective address information is stored. The semiconductor memory device according to claim 1. Memory cell array
When a plurality of spare cells in the row direction and a plurality of spare cells in the column direction are provided, and row-priority redundancy that preferentially uses the spare cells in the row direction and column-priority redundancy that preferentially uses the spare cells in the column direction can be selected In addition,
Redundant memory circuit
5. The semiconductor memory device according to claim 1, wherein row priority redundancy or column priority redundancy is selected according to a row / column priority selection signal. Redundant memory circuit
5. The semiconductor memory device according to claim 4, wherein when the plurality of redundant sets are all used and newly generated defective address information cannot be stored, a redundancy disable signal is output to the outside. Redundant memory circuit
7. A signal corresponding to a defect determination is input from the outside, and a decode signal generated by a decoder when the defect determination signal is input is stored as defect address information. The semiconductor memory device according to any one of the above. The redundant circuit
8. A defect collation signal for a defective address is output to the outside in accordance with a collation between a decode signal generated by a decoder and defect address information. A semiconductor memory device according to item. Access to the memory cell array
9. The defective address information is read from the redundant memory circuit after the power is turned on, verified in the redundant circuit, and permitted after a time that allows replacement with a spare cell. The semiconductor memory device according to any one of the above. Redundant memory circuit
10. The semiconductor memory device according to claim 1, wherein the stored defective address information is erased in response to an externally input defective address information erasing signal.

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