JP2016213286A - Semiconductor device and method of testing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of measuring a leakage current for each chip.SOLUTION: A semiconductor device comprises: a P-type semiconductor substrate SB; N-type well regions W1 and W2 provided on the semiconductor substrate SB; power supply wiring VL1 for supplying a power supply potential VDD to the well region W1; power supply wiring VL2 for supplying the power supply potential VDD to the well region W2; power supply wiring VL3 supplied with a ground potential VSS, and capacitively coupled with the power supply wirings VL1 and VL2; and a switching circuit 53 that supplies a testing potential different from the power supply potential VDD to the power supply wiring VL1, in response to a testing signal TEST. Thereby, a leakage current generated between the well regions W1 and W2 can be measured.SELECTED DRAWING: Figure 5

Description

  The present invention relates to a semiconductor device and a test method thereof, and more particularly to a semiconductor device capable of measuring a leakage current flowing between well regions and a test method thereof.

  Various unintended leakage currents may flow inside the semiconductor device. For example, Patent Document 1 focuses on a leakage current flowing between well regions, and a semiconductor device capable of reducing the leakage current has been proposed.

  Here, as a method of measuring the leakage current flowing between the well regions, a method of providing a TEG pattern on the scribe region of the semiconductor wafer can be considered. However, since the TEG pattern is provided on a scribe region different from the actual chip region, the leak current generated in the actual chip cannot be measured correctly. For this reason, when there is a variation in the amount of leakage current in each chip on the semiconductor wafer, the leakage current cannot be measured correctly.

Japanese Patent Laid-Open No. 2002-313907 JP 2012-134238 A JP 2011-233765 A

  In order to enable measurement of leakage current for each chip, it is necessary to form a measurement pattern on each chip, not on the scribe region. However, if a dedicated area is allocated for the measurement pattern, the chip area increases.

  On the other hand, a semiconductor device may be provided with a compensation capacitor for stabilizing the power supply potential (see Patent Documents 2 and 3). The present inventor has intensively studied a semiconductor device capable of measuring the leakage current for each chip without increasing the chip area by measuring the leakage current using a region in which a compensation capacitor is provided.

  A semiconductor device according to an aspect of the present invention includes a first conductivity type semiconductor substrate, first and second well regions of a second conductivity type provided on the semiconductor substrate, and first in the first well region. A first power supply wiring for supplying a first power supply potential, a second power supply wiring for supplying the first power supply potential to the second well region, and a second power supply potential are supplied. A third power supply line that is capacitively coupled to the second power supply line, a first switching circuit that supplies a test potential different from the first power supply potential to the first power supply line in response to a test signal; It is characterized by providing.

  A semiconductor device according to another aspect of the present invention includes a first conductive type semiconductor substrate, second conductive type first and second well regions provided on the semiconductor substrate, and an upper portion of the first well region. A first capacitive element having first and second electrodes, a second capacitive element having a third and fourth electrode provided on an upper portion of the second well region, and the first capacitive element. A first power supply wiring connected to one electrode; a second power supply wiring connected to the third electrode; a third power supply wiring connected to the second and fourth electrodes; In response to a test signal, a first contact conductor connecting the first electrode and the first well region, a second contact conductor connecting the third electrode and the second well region, A first switching circuit that switches a potential supplied to the first power supply wiring. It is characterized in.

  According to another aspect of the present invention, there is provided a method for testing a semiconductor device, wherein different potentials are supplied to first and second well regions of a second conductivity type, which are provided on a first conductivity type semiconductor substrate and adjacent to each other. A leakage current flowing between the region and the second well region is measured.

  According to the present invention, it is possible to measure the leakage current for each chip without increasing the chip area.

1 is a block diagram showing an overall configuration of a semiconductor device 10 according to a preferred embodiment of the present invention. 1 is a schematic plan view showing a layout of a semiconductor device 10. It is a schematic plan view showing a part of an array region 11A and a compensation capacitance region CA in an enlarged manner. It is a schematic plan view for explaining the structure of the compensation capacitor in more detail. It is a schematic sectional view for explaining the structure of the compensation capacitor in more detail. It is a schematic sectional drawing which expands and shows compensation capacity C11. 2 is a block diagram showing a configuration of a test circuit 50 according to a first example. FIG. It is a figure for demonstrating the test method using the test circuit 50 by a 1st example. FIG. 6 is a circuit diagram for explaining the operation of switching circuits 53 and 54 during normal operation and during a leakage current measurement test. It is a block diagram which shows the structure of the test circuit 50 by a 2nd example. It is a figure for demonstrating the test method using the test circuit 50 by a 2nd example. It is a schematic sectional drawing which shows the pattern for measuring the relationship between the distance between well regions, and leakage current. It is a figure for demonstrating the method to measure the leakage current between well area | regions W1 and W2. It is a figure for demonstrating the method to measure the leakage current between well area | regions W1 and W3. It is another schematic plan view for demonstrating in detail the structure of a compensation capacity | capacitance.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a block diagram showing the overall configuration of a semiconductor device 10 according to a preferred embodiment of the present invention.

  The semiconductor device 10 according to the present embodiment is a DRAM (Dynamic Random Access Memory) and includes a memory cell array 11 as shown in FIG. The memory cell array 11 is provided with a plurality of sub-word lines SWL and a plurality of bit lines BL that intersect with each other, and memory cells MC are arranged at the intersections thereof. Selection of the sub word line SWL is performed by the row decoder 12, and selection of the bit line BL is performed by the column decoder 13. The bit line BL is connected to the sense amplifier SA in the memory cell array 11, and the bit line BL selected by the column decoder 13 is connected to the main amplifier 14 via the sense amplifier SA.

  The operations of the row decoder 12, the column decoder 13 and the main amplifier 14 are controlled by the access control circuit 20. The access control circuit 20 is supplied with an address signal ADD through an address terminal 21 and a command signal CMD through a command terminal 22. The access control circuit 20 controls operations of the row decoder 12, the column decoder 13, the main amplifier 14, and the data input / output circuit 30 based on the address signal ADD and the command signal CMD.

  Specifically, when the command signal CMD indicates an active command, the address signal ADD is supplied to the row decoder 12. In response to this, the row decoder 12 selects the sub word line SWL indicated by the address signal ADD, whereby the corresponding memory cell MC is connected to the bit line BL. On the other hand, when the command signal CMD indicates a read command or a write command, the address signal ADD is supplied to the column decoder 13. In response to this, the column decoder 13 connects the bit line BL indicated by the address signal ADD to the main amplifier 14.

  Thereby, during the read operation, the read data DQ read from the memory cell array 11 via the sense amplifier SA is output from the data terminal 31 to the outside via the main amplifier 14 and the data input / output circuit 30. In the write operation, write data DQ supplied from the outside via the data terminal 31 and the data input / output circuit 30 is written into the memory cell MC via the main amplifier 14 and the sense amplifier SA.

  Each of these circuit blocks operates based on a predetermined internal power supply. These internal power supplies are generated by the power supply circuit 40 shown in FIG. The power supply circuit 40 receives the power supply potential VDD and the ground potential VSS supplied through the power supply terminals 41 and 42, and generates various internal potentials VINT based on these. The internal potential VINT is stabilized by the compensation capacitor C0. Further, the power supply potential VDD and the ground potential VSS inside the semiconductor device 10 are stabilized by the compensation capacitor C1.

  The power supply potential VDD and the ground potential VSS are also supplied to the test circuit 50. The test circuit 50 is a circuit used for measuring a leak current flowing between well regions, and is controlled by a test signal TEST. The test circuit 50 is connected to the test terminal 51, and the leakage current can be measured by connecting an external ammeter 52 to the test terminal 51. The leak current measurement test will be described later.

  FIG. 2 is a schematic plan view showing the layout of the semiconductor device 10.

  As shown in FIG. 2, the planar shape of the semiconductor device 10 is a rectangle, and includes a plurality of array regions 11 </ b> A arranged in a matrix in the X direction and the Y direction. The array region 11A is a region where the memory cell array 11 shown in FIG. 1 is arranged. A plurality of external terminals P are arranged in the X direction in the central region of the semiconductor device 10 in the Y direction. The external terminals P include the address terminal 21, command terminal 22, data terminal 31, power supply terminals 41 and 42, and test terminal 51 shown in FIG. Furthermore, a compensation capacitance region CA is provided between the edge of the semiconductor device 10 in the X direction and the external terminal P. In the compensation capacitance area CA, at least the compensation capacitance C1 shown in FIG. 1 is arranged.

  FIG. 3 is a schematic plan view showing a part of the array region 11A and the compensation capacitor region CA in an enlarged manner.

  As shown in FIG. 3, a large number of cylindrical lower electrodes EL are regularly arranged in the array region 11A. The cylindrical lower electrode EL constitutes a lower electrode of a cell capacitor included in the memory cell MC shown in FIG. The upper electrode EH of the cell capacitor is formed on almost the entire surface so as to fill the space between the lower electrodes EL via a capacitance insulating film (not shown).

  The above structure in the array region 11A is also adopted in the compensation capacitance region CA. That is, a large number of cylindrical lower electrodes EL are regularly arranged in the compensation capacitor area CA, and the upper electrode EH is formed on almost the entire surface so as to fill the space between the lower electrodes EL via a capacitor insulating film (not shown). The compensation electrode C1 shown in FIG. 1 is configured by the lower electrode EL and the upper electrode EH in the compensation capacitance region CA.

  FIG. 4 is a schematic plan view for explaining the structure of the compensation capacitor in more detail, and FIG. 5 is a schematic cross-sectional view thereof.

  As shown in FIGS. 4 and 5, in this embodiment, two N-type well regions W1 and W2 are provided adjacent to each other on the surface of a P-type semiconductor substrate SB. A ground potential VSS is applied to the semiconductor substrate SB by the sub-con region 60. The ground potential VSS is supplied by the power supply wiring VL3, and the ground potential VSS is supplied to the sub-con region 60 through the through-hole conductor 90, the tungsten wiring 80, and the contact conductor 70.

  On the other hand, the power supply potential VDD is applied to the well regions W1 and W2 through the well-con regions 61 and 62, respectively. The power supply potential VDD is supplied by the power supply wirings VL1 and VL2. Among these, the power supply wiring VL1 is connected to the well-con region 61 through the through-hole conductor 91, the tungsten wiring 81, and the contact conductor 71, whereby the power supply potential VDD is supplied to the well region W1. The power supply wiring VL2 is connected to the well contact region 62 through the through-hole conductor 93, the tungsten wiring 83, and the contact conductor 72, whereby the power supply potential VDD is supplied to the well region W2.

  As shown in FIGS. 4 and 5, compensation capacitors C11 and C12 are arranged above the well regions W1 and W2. The compensation capacitors C11 and C12 are a part of the compensation capacitor C1 described above, and include a plurality of cylindrical lower electrodes EL as described with reference to FIG. One electrode of the compensation capacitor C11 is connected to the tungsten wiring 81, whereby the power supply potential VDD is supplied during normal operation. Similarly, one electrode of the compensation capacitor C12 is connected to the tungsten wiring 83, whereby the power supply potential VDD is supplied during normal operation.

  On the other hand, the other electrode of the compensation capacitor C <b> 11 is connected to the tungsten wiring 82. The tungsten wiring 82 is connected to the power supply wiring VL3 through the through-hole conductor 92, whereby the ground potential VSS is always supplied to the other electrode of the compensation capacitor C11. Similarly, the other electrode of the compensation capacitor C12 is connected to the tungsten wiring 84. The tungsten wiring 84 is connected to the power supply wiring VL3 through the through-hole conductor 94, whereby the ground potential VSS is always supplied to the other electrode of the compensation capacitor C12.

  With this configuration, the compensation capacitors C11 and C12 are both connected between the power supply potential VDD and the ground potential VSS, and play a role of stabilizing these potentials.

  Here, the power supply wirings VL1 to VL3 are wirings located in an upper layer than the tungsten wirings 80 to 84. Therefore, as shown in FIG. 15, a large number of wirings are arranged in the wiring layer, and as a result, even when the planar positions of the power supply wirings VL1 and VL2 are separated from the compensation capacitors C11 and C12 to some extent, By deforming the planar shape of the lower tungsten wirings 81 and 83, both can be connected. That is, even in a region where wiring is congested, a circuit similar to that in FIG. 5 can be realized without increasing the chip area.

  FIG. 6 is a schematic cross-sectional view showing the compensation capacitor C11 in an enlarged manner.

  As shown in FIG. 6, the compensation capacitor C <b> 11 includes a cylindrical lower electrode EL <b> 1 connected to the tungsten wiring 81 and a cylindrical lower electrode EL <b> 2 connected to the tungsten wiring 82. The surfaces of the lower electrodes EL1, EL2 are both covered with a capacitive insulating film D, and an upper electrode EH is provided so as to fill the inside of the cylinder and between adjacent cylinders. Thus, since the two capacitors are connected in series, the voltage applied to the capacitive insulating film D can be reduced to half the power supply potential VDD, and the withstand voltage of the capacitive insulating film D can be secured. It becomes.

  Therefore, when it is necessary to lower the voltage applied to the capacitive insulating film D, three or more capacitors may be connected in series. However, it is not essential to connect a plurality of capacitors in series, and the compensation capacitor C11 may be configured by one capacitor as long as the withstand voltage of the capacitor insulating film D is ensured.

  6 denotes a support film that connects adjacent lower electrodes EL so that the cylindrical lower electrode EL having a large aspect ratio does not collapse in the manufacturing process.

  FIG. 7 is a block diagram showing a configuration of the test circuit 50 according to the first example.

  As shown in FIG. 7, the test circuit 50 according to the first example tests the switching circuit 53 for switching the potential applied to the compensation capacitors C11 and C12 to be tested, one of the monitor power supply potential VM and the current monitor signal IM. And a switching circuit 54 connected to the terminal 51. The monitor power supply potential VM is one of internal potentials VINT generated by the power supply circuit 40, for example. The switching circuits 53 and 54 are both controlled by a test signal TEST. Next, how the voltages applied to the compensation capacitors C11 and C12 to be tested are switched by the test signal TEST will be described.

  First, when the test signal TEST is at an inactive level, that is, during normal operation, the power supply potential VDD is supplied to the power supply wirings VL1 and VL2 and the ground potential VSS is supplied to the power supply wiring VL3 as described with reference to FIG. Is supplied. Thereby, since the voltage VDD-VSS is applied to both ends of the compensation capacitors C11 and C12, the power supply potential VDD and the ground potential VSS are stabilized. At this time, since the power supply potential VDD is applied to both the well regions W1 and W2, both have the same potential. Therefore, no leakage current is generated between the well regions W1 and W2.

  On the other hand, when the test signal TEST is at the active level, that is, during the leak current measurement test, the power supply line VL2 is connected to the test terminal 51, and the ground potential VSS is supplied to the power supply lines VL1 and VL3. Accordingly, as shown in FIG. 8, since the ground potential VSS is applied to the well region W1, if a predetermined level (for example, the power supply potential VDD) is applied to the test terminal 51 from the outside, the well region W1 is connected to the well regions W1 and W2. Causes a predetermined potential difference, and a leak current IL flows. Since the leak current IL flows as the current monitor signal IM through the test terminal 51, if the amount of current is measured by the ammeter 52, the leak current generated between the well regions W1 and W2 is directly measured. It becomes possible.

  FIG. 9 is a circuit diagram for explaining the operation of the switching circuits 53 and 54 during normal operation and during a leakage current measurement test.

  As shown in FIG. 9, the switching circuits 53 and 54 include switch circuits SW1 to SW4. When the test signal TEST is at an inactive level, that is, during normal operation, the switch circuits SW1 and SW3 are turned on. Then, the switch circuits SW2 and SW4 are turned off. As a result, a voltage of VDD-VSS is applied to both ends of the compensation capacitors C11 and C12. On the other hand, when the test signal TEST is at the active level, that is, during the leakage current test operation, the switch circuits SW2 and SW4 are turned on and the switch circuits SW1 and SW3 are turned off. As a result, a leak current IL is generated. By monitoring this with the ammeter 52, the leak current between the well regions W1, W2 can be measured.

  The leakage current measurement test in this embodiment uses well regions W1 and W2 that are actually used in the semiconductor device 10, and therefore correctly measures the leakage current flowing between the well regions for each chip. Is possible. In addition, these well regions W1 and W2 are regions for the compensation capacitors C11 and C12 arranged above them, and are not dedicated regions provided for measuring the leakage current, so that the chip area increases. I don't have to.

  In the above example, the ground potential VSS is supplied as the test potential to the power supply wiring VL1 during the leak current measurement test. However, as long as a different potential is supplied between the well regions W1 and W2, the power supply wiring VL1 is used. May be supplied with a test potential different from the ground potential VSS.

  FIG. 10 is a block diagram showing a configuration of the test circuit 50 according to the second example.

  As shown in FIG. 10, the test circuit 50 according to the second example includes a switching circuit 55 that switches the potential applied to the compensation capacitors C11 and C12 to be tested. The switching circuit 55 is controlled by a test signal TEST.

  First, when the test signal TEST is at an inactive level, that is, during normal operation, the power supply potential VDD is supplied to the power supply wirings VL1 and VL2 and the ground potential VSS is supplied to the power supply wiring VL3 as described with reference to FIG. Is supplied. Thereby, since the voltage VDD-VSS is applied to both ends of the compensation capacitors C11 and C12, the power supply potential VDD and the ground potential VSS are stabilized. At this time, since the power supply potential VDD is applied to both the well regions W1 and W2, both have the same potential. Therefore, no leakage current is generated between the well regions W1 and W2.

  On the other hand, when the test signal TEST is at the active level, that is, during the leak current measurement test, as shown in FIG. VSS is supplied. As a result, since the ground potential VSS is applied to the well region W1 and the power supply potential VDD is applied to the well region W2, a potential difference of VDD−VSS is generated between the well regions W1 and W2, and the leakage current IL flows. Since the leakage current IL increases the consumption current of the semiconductor device 10, if the consumption current during standby during normal operation is compared with the consumption current during standby during the leakage current measurement test, the well region W1, It becomes possible to indirectly measure the leakage current generated between W2.

  FIG. 12 is a schematic cross-sectional view showing a pattern for measuring the relationship between the distance between the well regions and the leakage current.

  In the example shown in FIG. 12, three N-type well regions W1 to W3 are provided in the semiconductor substrate SB. The well region W1 is disposed between the well region W2 and the well region W2. Here, the distance between the well regions W1 and W2 is L1, and the distance between the well regions W1 and W3 is L2 (<L1). Here, the power supply potential VDD is applied to the well region W3 by the well-con region 63. The power supply potential VDD is supplied through the power supply wiring VL4. The power supply wiring VL4 is connected to the well-con region 63 through the through-hole conductor 95, the tungsten wiring 86, and the contact conductor 73, whereby the power supply potential VDD is supplied to the well region W3.

  As shown in FIG. 12, a compensation capacitor C13 is disposed above the well region W3. The compensation capacitor C13 is a part of the compensation capacitor C1 described above. One electrode of the compensation capacitor C13 is connected to the tungsten wiring 85, whereby the power supply potential VDD is supplied. On the other hand, the other electrode of the compensation capacitor C13 is connected to the tungsten wiring 86. The tungsten wiring 86 is connected to the power supply wiring VL3 through the through-hole conductor 96, whereby the ground potential VSS is supplied to the other electrode of the compensation capacitor C13.

  When measuring the leakage current between the well regions W1 and W2, as shown in FIG. 13, the power supply wiring VL2 is connected to the test terminal 51, and the ground potential VSS is supplied to the power supply wirings VL1 and VL3. The power supply potential VDD is supplied to the wiring VL4. Thereby, since the ground potential VSS is applied to the well region W1, if a predetermined level (for example, the power supply potential VDD) is applied to the test terminal 51 from the outside, a predetermined potential difference is generated between the well regions W1 and W2, and leakage occurs. Current IL flows. Since the leak current IL flows as the current monitor signal IM through the test terminal 51, if the amount of current is measured by the ammeter 52, the leak current generated between the well regions W1 and W2 is directly measured. It becomes possible.

  On the other hand, when measuring the leakage current between the well regions W1 and W3, as shown in FIG. 14, the power supply wiring VL4 is connected to the test terminal 51, and the ground potential VSS is supplied to the power supply wirings VL2 and VL3. The power supply potential VDD is supplied to the wiring VL1. Accordingly, since the ground potential VSS is applied to the well region W1, if a predetermined level (for example, the power supply potential VDD) is applied to the test terminal 51 from the outside, a predetermined potential difference is generated between the well regions W1 and W3, and leakage occurs. Current IL flows. Since the leak current IL flows as the current monitor signal IM through the test terminal 51, if the amount of current is measured by the ammeter 52, the leak current generated between the well regions W1 and W3 is directly measured. It becomes possible.

  As described above, when the leakage current measurement test is performed using the three well regions W1 to W3, the relationship between the distance between the well regions and the leakage current can be clarified.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

DESCRIPTION OF SYMBOLS 10 Semiconductor device 11 Memory cell array 11A Array area | region 12 Row decoder 13 Column decoder 14 Main amplifier 20 Access control circuit 21 Address terminal 22 Command terminal 30 Data input / output circuit 31 Data terminal 40 Power supply circuit 41, 42 Power supply terminal 50 Test circuit 51 Test terminal 52 Ammeter 53, 54 Switching circuit 60 Subcon region 61-63 Wellcon region 70-73 Contact conductor 80-86 Tungsten wiring 90-96 Through-hole conductor BL Bit line C0, C1, C11-C13 Compensation capacitance CA Compensation capacitance region D Capacity Insulating film EH Upper electrode EL, EL1, EL2 Lower electrode MC Memory cell P External terminal S Support film SA Sense amplifier SB Semiconductor substrate SW1-SW4 Switch circuit SWL Sub word lines VL1-VL4 Power supply wiring W1 W3 well region

Claims (15)

A first conductivity type semiconductor substrate;
First and second well regions of a second conductivity type provided on the semiconductor substrate;
A first power supply wiring for supplying a first power supply potential to the first well region;
A second power supply wiring for supplying the first power supply potential to the second well region;
A third power supply line supplied with a second power supply potential and capacitively coupled to the first and second power supply lines;
A semiconductor device comprising: a first switching circuit that supplies a test potential different from the first power supply potential to the first power supply wiring in response to a test signal.   2. The semiconductor device according to claim 1, wherein the first well region and the second well region are disposed adjacent to each other. A first capacitive element disposed on top of the first well region;
A second capacitive element disposed above the second well region,
One electrode of the first capacitive element is connected to the first power supply wiring, the other electrode of the first capacitive element is connected to the third power supply wiring,
The one electrode of the second capacitor element is connected to the second power supply line, and the other electrode of the second capacitor element is connected to the third power supply line. 3. The semiconductor device according to 1 or 2.   4. The semiconductor device according to claim 3, wherein the one or the other electrode of the first and second capacitor elements has a cylindrical shape. 5.   The semiconductor device according to claim 1, wherein the test potential is the same potential as the second power supply potential. An external terminal,
The semiconductor device according to claim 1, further comprising a second switching circuit that connects the second power supply wiring to the external terminal in response to the test signal.   The semiconductor device according to claim 1, wherein the first conductivity type is a P-type, and the second conductivity type is an N-type. A first conductivity type semiconductor substrate;
First and second well regions of a second conductivity type provided on the semiconductor substrate;
A first capacitive element provided on top of the first well region and having first and second electrodes;
A second capacitive element provided on the second well region and having third and fourth electrodes;
A first power supply line connected to the first electrode;
A second power supply wiring connected to the third electrode;
A third power supply line connected to the second and fourth electrodes;
A first contact conductor connecting the first electrode and the first well region;
A second contact conductor connecting the third electrode and the second well region;
A semiconductor device comprising: a first switching circuit that switches a potential supplied to the first power supply wiring in response to a test signal.   The first switching circuit supplies a first power supply potential to the first power supply wiring when the test signal is in the first state, and when the test signal is in the second state. The semiconductor device according to claim 8, wherein a second power supply potential different from the first power supply potential is supplied to the first power supply wiring.   The semiconductor device according to claim 9, wherein the second power supply potential is supplied to the third power supply wiring regardless of the state of the test signal.   11. The device according to claim 9, further comprising: a second switching circuit that supplies the first power supply potential to the second power supply wiring when the test signal is in the first state. Semiconductor device.   The semiconductor device according to claim 11, wherein the second switching circuit connects the second power supply wiring to a predetermined external terminal when the test signal is in the second state.   The semiconductor device according to claim 8, wherein the first well region and the second well region are disposed adjacent to each other.   The semiconductor device according to claim 8, wherein the first conductivity type is a P-type, and the second conductivity type is an N-type. Different potentials are supplied to the first and second well regions of the second conductivity type that are provided on the first conductivity type semiconductor substrate and are adjacent to each other;
A method for testing a semiconductor device, comprising: measuring a leakage current flowing between the first well region and the second well region.

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