JPS63144560A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To obtain stable write and read characteristics without the variation of a manufacturing process and the lowering of the degree of integration by changing the channel width of a transistor selecting memory cells and compensating electrical characteristics in an electrodes generated by the difference of the physical positions of each memory cell. CONSTITUTION:Width is widened toward the central direction of N<+> diffusion layers 14 and gate polysilicon 13 in order to change the channel width W of each selecting transistor. When voltage is applied to the gate polysilicon 13d, a plurality of memory cells through an aluminum wiring 18d are selected. When high voltage is applied to either of word-line polysilicons 21, one memory cell in memory cells of interest is selected. Since the channel width of a selecting TR with the gate polysilicon 13d is increased, an internal resistance value at the time of the conduction of said selecting TR is reduced. Consequently, the increasing section of the source potential of the selected memory cell is compensated by the rise of the drain potential of said memory cell though the source potential of the selected memory cell is elevated. Accordingly, write currents equal to a memory cell 26 near to contact holes 22, 23 can be supplied.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device having a configuration in which a plurality of memory cells share one electrode due to higher integration density.

[Conventional technology]

An example of a semiconductor memory device in which a plurality of memory cells share one electrode is an F' AMOS type EFROM as shown in the pattern circuit diagram of FIG. There is a circuit diagram shown in FIG. 3 that illustrates this principle.

In the figure, 1 is a memory power supply (15
21 V), 2 is an N-channel transistor that is conductive during writing (hereinafter referred to as [!i-write transistor]), and 3 is an Nfw channel transistor that is conductive during read-out (hereinafter referred to as [read transistor]). ), a power supply (not shown) of approximately 5V, which is separate from the write power supply 1, is connected. .

4 (4a, 4b, . . . ) are N-channel transistors for selecting the first bit line of the memory (hereinafter referred to as "first bit selection transistors") r, which divide the memory cell array to be described later into a plurality of regions. 5 (5a, 5b...
) is an N+-Yarnell transistor for selecting the second bit line of the memory (
Hereinafter, it will be referred to as "second bit selection transistor." ) to select a bit line in the corresponding memory cell array area. 6 (611, 61□, 613...) are N-channel A7-channel FAMO8 type memories (hereinafter referred to as "memory hill 1") connected to each second bit selection transistor 5, which are arranged in a matrix and serve as memories. It forms one area of the cell array. 7 to 11 are internal signals, read signals, and first bit line selection signals (9a) that determine whether transistors 2 to 6 are conductive or 8 nonconductive, respectively.

9b...), second bit line selection signal (10a, 10b...), second bit line selection signal (10a, 10b...)
-), word line selection signals (11a, 1lb,
11G...).

In the above configuration, the operation during writing will be explained. First, the write transistor 2 becomes conductive by the write signal 7, thereby entering the write state, and the first bit selection transistor 4 of all C is set for writing. A high voltage (approximately 15 to 21 cm) is applied from a power source 1.

Next, the first bit line selection signal 9 causes one of the first bit selection transistors 4 (temporarily 48) to become conductive and selects it, and the second bit line selection signal @10 causes the second bit selection transistor 5 to become conductive. In any case, 5
a) is selected, and a high voltage for writing is applied to the drains of all η memory cells 6 connected to the selected bit line selection transistor 5a. on the other hand,
One of the word line selection signals 11 (temporarily assumed to be 11a) is applied to the corresponding memory cell 6 (in this case, 6 6 .
A high voltage is applied to the gate of...).

11° 21 As a result, the memory cell 611 to which a high voltage is applied to the drain and gate is selected, and predetermined data is written into this memory cell 611 in blue. In the above process, the read transistor 3 is in a non-conductive state. Further, during reading, the read signal 8 causes the successive transistor 3 to be in a conductive state (the write transistor 2 is in a non-conductive state), and a read voltage (approximately 5 V) is applied to the first bit selection transistor 4. Below, each signal 9 to 1 as in writing
The data of the memory cell 6 selected by 1 is not read.

FIG. 2 is a pattern circuit diagram of a part of the circuit shown in FIG. 3 when it is integrated into an integrated circuit, and FIG. 2 will be explained below with reference to FIG. 3.

12 is an aluminum wiring corresponding to the connection line between the first bit selection transistor 4 and the second bit selection transistor 5; 13;
(13a to 13h) are second bit selection signals 10 (1
0a, 10b...), and 14 (14a to 14d) is the gate polysilicon of the transistor corresponding to the second bit selection transistor 5 (5a.

5b...) are arranged as the base of the selection transistor section 17, and 15 (15a-156) is the second
Contact holes 16 (16a to 16h) correspond to the input part of the bit selection transistor 5, and contact holes 16 (16a to 16h) correspond to the output part of the second bit selection transistor 5. In the selection transistor section 17, for example, the gate polysilicon 13b, the N+ diffusion layer 14a, and the contact hole /lz 15 a .

One second bit selection transistor 5 is configured by the contact hole 16b. 18 (18a-18h)
is aluminum wiring 19 (19, 19, 2...) corresponding to the connection line between the second bit selection transistor 5 and the memory cell 6.
・) is a contact hole corresponding to the input part (drain in FAMO8 type) of memory cell 6, and 20 is an N+ diffusion layer that is the base for forming two rows of memory cells 611, 621, and 6.6. , 21 (21a, 21
b) H'7-t m3t! Word line polysilicon corresponding to selection signals 11a and 11b (gate for FAMO8 type)
, 22.23 are two columns of memory cells 6, 1, 621...
and 612, 622... all output parts (1:ΔM
In the O8 type, this is a contact hole corresponding to the source. Of these = 1 contact hole 22 has aluminum wiring 188
~18d (6.6.66 according to the array symbol in Figure 3, but 6
11 21 31° 41 31.641 is a common output electrode (not shown in Fig. 3), and the two l contact holes 23 are made of aluminum wiring.
4 memory cells connected to 18h (6.6.6 according to the array symbol in FIG. 3).

681, but these are the common output electrodes of ff13 (see figure 13), and the GND aluminum wiring 24°25
It is connected to the. Also, GND aluminum wiring 24.25
are each grounded. 26 is two rows of memory cells 6.6
... and 6.6 ... is arrangement 1 21
12 22 is a memory cell section arranged in columns, for example, the memory cell part 6 has a contact hole 19 and a word line polysilicon 21a.
, a contact hole 22, and the memory cell 622 includes a contact hole 1922, a word line polysilicon 21b, and a TI contact hole 22.

In the following configuration, during writing, one of the first bit selection transistors 4 is made conductive by the first bit line selection signal 9, a high voltage is applied to the aluminum wiring 12, and the contact holes 15a to 15d are in a high voltage state. becomes. moreover,
The second bit selection transistors 5 arranged in the transistor section 17 are configured so that any one of the second bit line selection signals 10 is applied and the corresponding selection signal is applied to the gate polysilicon 138 to 13h. When one of the transistors becomes conductive, the drain of the memory cell 6 connected to the conductive second bit selection transistor 5 (for example, contact holes 19, 1912, . . . in FIG. 2) becomes conductive.
A high voltage (such as ') is applied.

Then, by applying a high voltage to one of the word line polysilicon 21 by the word line selection signal 11,
One memory cell 6 is selected.

At this time, the selected memory cell 6 becomes conductive,
Writing is performed using high-energy electrons, so-called hot electrons, generated by an avalanche phenomenon. Further, at the time of reading, a read voltage is applied to the word line polysilicon 21, and data is subsequently read from the selected memory cell 6 in the same way as at the time of writing described above.

[Problem that the invention seeks to solve]

As explained above, in the conventional semiconductor memory device, the contact holes 22 and 23 for connecting each memory cell to the GND aluminum wiring 24 and 25 to provide a ground level to each memory cell are usually formed in the memory cell section 26. One memory cell exists for every plurality (eight in FIG. 2) of memory cells. This is to increase the degree of integration of the semiconductor memory device, but for this reason, in memory buildings far from the contact holes 22 and 23 (for example, memory cells connected to the aluminum wiring 186 and 18e), the length of the N1 diffusion layer 20 is A resistance component corresponding to the amount of time is inserted into the memory cell. In other words, the resistance value R8G determined by R3o=(N diffusion length/N+diffusion width)XN+diffusion sheet resistance is inserted into the memory cell.

As a result, the selected memory cell becomes conductive, and if the write current at this time is ■, then vSG"" P R8
The source potential of the selected memory cell increases by the voltage determined by G. Since the gate voltage applied to the memory cell is constant, the occurrence of such a substrate bias effect reduces the effective gate voltage of the selected memory cell. For this reason, contact holes 22 and 23
In a memory cell far from the target, the driving ability decreases, the write current decreases, and writing cannot be performed sufficiently, resulting in a write speed of d. Further, there is also a problem in that the read speed becomes slow due to a decrease in the driving ability when the drive is extended.

This invention was made to solve the above-mentioned problems, and is a highly reliable semiconductor that has the same write and read characteristics regardless of the physical location of the memory building. There are fewer changes to the manufacturing process for storage devices,
The aim is to provide a comprehensive service without sacrificing quality.

[Means to solve the problem]

In the semiconductor memory device according to the present invention, in a case where a plurality of memory cells share one electrode, the transistor selector selects the memory cell. By changing the channel width, differences in electrical characteristics of the electrodes caused by differences in the physical positions of the memory cell portions can be corrected.

(Operation) In the present invention, by changing the channel width of the transistor that selects the memory cell portion, differences in electrical characteristics caused by differences in the physical locations of the memory cell portions are avoided.

〔Example〕

FIG. 1 shows a FAMO8 type EP according to an embodiment of the present invention.
FIG. 2 is a pattern circuit diagram showing a selection transistor section and a memory building section of a memory device that is a ROM. In the same figure, the parts except for the gate polysilicon 13 and the N+ diffusion layer 14 are the same as the conventional one, so the explanation will be omitted. ) to change N diffusion! !
The shape of the gate polysilicon 114 and the gate polysilicon 13 is such that the width becomes wider toward the center. This is to compensate for the drop in the effective gate voltage due to the aforementioned substrate bias effect, which occurs because the memory cells in the center are separated from the contact holes 22, 23.

The following will explain the case where gate polysilicon 13 d lfi is selected as an example. Gate polysilicon 13d
When a voltage is applied to , a plurality of memory cells are selected via the aluminum wiring 18d. Here, by applying a high voltage to one of the word line polysilicon 21,
One of the memory cells is selected. In this case, as described above, since the memory cell in the center of the figure is away from the contact holes 22 and 23, a relatively large substrate bias effect occurs. However, since the selection transistor having the gate polysilicon 13d has a large channel width, the internal resistance value of the selection transistor becomes small. As a result, even though the source potential of the selected memory cell increases, the increase can be compensated for by increasing the drain potential of the memory cell. As a result, it becomes possible to flow a write current equivalent to that of the memory cell 26 near the 21 contact holes 22 and 23 without reducing the effective gate voltage.

By configuring the selection transistor section 11 as described above, it is possible to generate the same hot electron in all the memory cells arranged in the memory cell section 26, and the write characteristics are determined by the physical characteristics of the memory cells. The target position becomes irrelevant. Similarly, during reading, stable reading characteristics can be obtained regardless of the physical location of the memory cell, and no delay in reading speed is caused. Furthermore, the manufacturing process of the embodiment of the present invention is different from that of the conventional method in that the N1 diffusion layer 14. This can be implemented by changing the shape of the gate polysilicon 13, and the degree of integration will hardly decrease.

Although this embodiment uses a FAMO8 type EPROM as an example, it can be applied to any semiconductor memory device in which a plurality of memory cells share one electrode and there are differences in electrical characteristics between the memory cells. be able to.

〔Effect of the invention〕

As explained above, according to the present invention, the difference in electrical characteristics caused by the difference in physical location between memory cells is corrected by changing the driving ability of the selection transistor based on the physical location of the selected memory cell. By doing so, it is possible to obtain stable write and read characteristics for all memory cells without changing the manufacturing process or reducing the degree of integration.

[Brief explanation of the drawing]

FIG. 1 is a pattern circuit diagram showing a selection transistor section and a memory cell section of a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a pattern circuit diagram of a conventional semiconductor memory device, and FIG. 1 is a circuit diagram showing the principle of a conventional semiconductor memory device. In the figure, 12.18 is aluminum wiring, 13 is gate polysilicon, 14.20 is N+ diffusion layer, 15.16.19
．． 22 and 23 are contact holes, 17 is a selection transistor section, 21 is a word line polysilicon, and 26 is a memory cell section. Note that the same reference numerals in each figure do not indicate the same or equivalent parts. Agent Masuo Oiwa Figure 1 & ---------P Mehrir Figure 3 Mr. Jun E, Commissioner of the Japan Patent Office:
)20 Name of the invention Sergeant-1ib 3. Relationship with the person making the amendment Moriya Shiki, representative of the patent applicant 4, Agent 5, Column for detailed description of the invention in the specification subject to amendment and drawings 6, Amendment Contents (1) Details 1! 21, line 9 “(about 15-21V)”
is corrected to "(approximately 12 to 21V)". (2) On page 2 of the specification, lines 13 and 14, [in the description, the writing power supply 1 is... " is corrected to "is." (3) "About 15 to 21 V" on page 3, line 18 of the specification is corrected to "about 12 to 21 V." (4) "High voltage?" on page 4, line 7 of the specification is corrected to "high voltage." (5) Replace “22” on page 6, line 13 of the specification with “22
is corrected to "mainly". (6) Replace “23” on page 6, line 17 of the specification with “23
is mainly corrected to j. (1) "No" in the third line of page 8 of the specification is corrected to "ni". (8) In Book III, page 10, line 7, "reading characteristics" is corrected to "reading characteristics." (9) In the 9th line of page 12 of the specification, the word ``J'' should be corrected to ``naku''. (10) “Internal” on page 12, line 9 of the specification is corrected to “1 when conducting.” (11) “As a result, the effective gate voltage decreases” on page 12, lines 13 and 14 of the specification. Correct "without doing" to "as a result." (12) In the specification, page 13, lines 5 to 7, "Compared to the conventional method, it is possible to implement it" is corrected to "There is no change compared to the conventional method." (13) Figure 1 of the drawings will be corrected as shown in the attached sheet. (14) Figure 2 of the drawings will be corrected as shown in the attached sheet. Figure 1 above

Claims (2)

[Claims] (1) In a memory device in which a plurality of memory cells share one electrode, by changing the channel width of a transistor that selects the memory cell, the electrodes that are caused by differences in the physical positions of the memory cells can be reduced. What is claimed is: 1. A semiconductor memory device, characterized in that the difference in electrical characteristics of the semiconductor memory device is corrected. (2) The semiconductor memory device according to claim 1, wherein the change in channel width of the transistor that selects the memory cell increases as the distance from the common GND wiring of the memory cell increases.