JP2001195896A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To detect fault between adjacent capacity elements for accumulating information including fault by short circuit by using a simple selective high potential impressing circuit. SOLUTION: This device is a semiconductor device which has plural word lines arranged along the direction of a row in parallel, plural bit lines arranged along the direction of a column intersecting orthogonally to the word lines, and a memory cell array consisting of memory cells provided at parts at which the word lines and the bit lines are intersected, and in which the memory cell is composed of MISFET for selecting a memory cell connected in series to a capacity element for accumulating information of crown constitution and the capacity element for accumulating information, further, the device has a first voltage applying means which can apply voltage being different from memory cells of row direction and column direction being adjacent to each memory cell, and a second voltage applying means which can apply voltage being different from memory cells of oblique direction being adjacent to each memory cell.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
The present invention relates to an integrated circuit device such as a DRAM (Dynamic Random Access Memory) in which a memory cell is composed of an information storage capacitor C having a crown structure and a memory cell selecting MISFET connected in series with the capacitor C. To apply to effective technology.

[0002]

2. Description of the Related Art A DRAM or the like as a semiconductor memory device has a memory cell array in which memory cells are arranged vertically and horizontally. The memory cell is a memory cell selection MI.
SFET (Metal Insulator Semiconductor Field Effe
ct Transistor) and an information storage capacitor (capacitor) connected in series to the ct transistor.

A field effect transistor for selecting a memory cell is formed on a main surface of a semiconductor substrate and mainly functions as a channel forming region, a gate insulating film, a gate electrode integrated with a word line, a source region or a drain region. Having a semiconductor region (impurity diffusion region). The information (charge) storage capacitor is arranged above the memory cell selecting field effect transistor for the purpose of reducing the plane size of the memory cell, and mainly has a lower electrode, a capacitor insulating film, an upper electrode, and the like. It has become. The lower electrode of the information storage capacitor is electrically connected to one of the semiconductor regions of the memory cell selection field effect transistor, and the other semiconductor region of the memory cell selection field effect transistor is electrically connected to the bit line. Have been.

[0004] A COB (Capacitor Over Bitline) in which an information storage capacitor is arranged above a bit line (data line).
The DRAM having the structure is disclosed in Japanese Patent Application Laid-Open No. 7-7084. The DRAM described in this publication is
In order to compensate for the decrease in the amount of stored charge (Cs) of the information storage capacitor due to the miniaturization of the memory cell, the lower electrode of the information storage capacitor is formed in a cylindrical shape, and the lower electrode (storage electrode) and the upper electrode ( (Plate electrode) and the area of the capacitive insulating film interposed therebetween. Further, as the capacitor insulating film, a stacked film of a silicon oxide film and a silicon nitride film or a high dielectric or ferroelectric material is used for the capacitor insulating film.

[0005] The information storage capacitive element (hereinafter simply referred to as a capacitor or a capacitor) has various structures, and a crown structure is known as one of them. Such a structure is described in, for example, "Ultra LSI Memory" published by Baifukan Co., Ltd. on April 10, 1997, pages 14 to 19, and
It is described in No. 0 publication. The latter document discloses a fin-shaped capacitor and a crown-shaped capacitor.

[0006] On the other hand, a semiconductor device is subjected to screening by a burn-in test or the like at the final stage of its manufacture, and a good product and a defective product are selected. As an example of the burn-in test, a technique described in Japanese Patent Application Laid-Open No. 5-54640 is known. This document provides a mode / determination circuit that generates a one-pulse determination signal when a plurality of external control signals have a predetermined level relationship, and all bit lines are connected to data input / output lines by the determination signal. An example in which a collective selection circuit for connection is provided is disclosed.

On the other hand, Japanese Patent Application Laid-Open No. Hei 5-28885 discloses a circuit for collectively selecting a plurality of word lines for selecting a memory cell and a plurality of bit lines for selecting a memory cell. And a memory cell array that includes a circuit that selects every other one at a time and a memory cell array. In this semiconductor memory device, writing of a checkerboard pattern into a memory cell array required for screening of memory cells can be realized by several times of memory accesses, and the efficiency at the time of screening is improved. Even in this configuration, when a specific memory cell is set to the logical level “1”, it is not possible to set all the adjacent memory cells in the row and column directions and the adjacent diagonal memory cells to the logical level “0”. .

[0008]

SUMMARY OF THE INVENTION In the present applicant,
In a burn-in test performed in a wafer state in DRAM manufacturing, stress is applied to a gate oxide film, a gate-drain, a gate-source, a source-drain, etc. of a memory cell. Then, the quality of the product is inspected by a function inspection (function test) performed thereafter.

The present inventor has analyzed and examined the failure contents of the memory cell portion. As a result, in the information storage capacitor having the crown structure, a short-circuit failure may occur between adjacent memory cells in the manufacturing stage. Ascertained.

FIG. 18 is a schematic diagram showing an arrangement state of the capacitative elements C for storing information (charge) having a crown structure in a memory cell. A short-circuit generator 60 that generates a short-circuit failure exists in a portion surrounded by a circle A. This short generator 6
The analysis revealed that 0 was due to adhesion of a residue remaining after etching due to defective etching of the conductor layer at the stage of forming the electrode (lower electrode) at the stage of manufacturing the information storage capacitor element or adhesion of a foreign substance causing a short circuit.

FIG. 19 is a cross-sectional view of a memory cell portion in a state where an unetched portion 61 is present, and FIG. 20 is a cross-sectional view of a memory cell portion in a state where a foreign substance 62 is present. These figures are partial views showing a state in which an information (charge) storage capacitor C is formed adjacent to the interlayer insulating film 16.

That is, the information storage capacitive element C includes a lower electrode 19 formed on the interlayer insulating film 16 and the lower electrode 19.
A capacitor insulating film 22 formed thereon;
And an upper electrode 23 formed thereon. The capacitor insulating film 22 is formed of, for example, an antioxidant film 20 formed on the lower electrode 19 and a polycrystalline oxide dielectric film 21 formed on the antioxidant film 20. The lower electrode 19 is connected to a conductive plug (not shown) via a conductive plug 18 formed through the interlayer insulating film 16. This conductive plug is a field effect transistor (MOSFET: Metal Oxide Semiconductor Fi) for memory cell selection.
It is electrically connected to an n-type semiconductor region functioning as a source region or a drain region of an eld effect transistor (Q). FIG. 19 shows a case where, when the lower electrode 19 is formed, the selective etching of the conductor layer for forming the lower electrode 19 cannot be performed properly, and an unetched portion 61 occurs between the adjacent information storage capacitance elements C. It is.

FIG. 20 shows the lower electrode 1 of the adjacent information storage capacitor C after the selective etching of the conductor layer.
This is generated as a result of the foreign matter 62 adhering between the layers 9 or remaining when the conductive layer is formed by mixing the foreign matter 62 into the conductor layer.

These short-circuit failures cannot be detected by a burn-in test in a normal wafer state. That is, in the burn-in test in the wafer state, voltage stress cannot be applied to the storage node (the electrode connected to the information storage capacitor C of the field effect transistor Q for selecting the memory cell of the storage capacitor). It is not possible to determine the presence or absence of a short circuit due to etching residue or foreign matter adhesion.

Further, the above-described conventional semiconductor device having a burn-in test circuit has a complicated circuit configuration, requires a large number of transistors, increases the size of the semiconductor device, and makes it difficult to reduce the manufacturing cost of the semiconductor device.

An object of the present invention is to provide a semiconductor device which can detect a defect between adjacent information storage capacitance elements C including a short defect using a simple selective high potential applying circuit.

Another object of the present invention is to provide a semiconductor device which is small and inexpensive to manufacture.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0019]

The following is a brief description of an outline of typical inventions disclosed in the present application.

(1) A plurality of word lines arranged in parallel along the row direction, a plurality of bit lines arranged along a column direction orthogonal to the word lines, and the word line and the bit line A memory cell array including a memory cell provided at an intersecting portion, wherein the memory cell includes a crown-structured information storage capacitance element and a memory cell selection MISFET connected in series to the information storage capacitance element A first voltage applying means capable of applying a potential different from that of the memory cells in the row and column directions in which each of the memory cells is adjacent; and a memory cell in an oblique direction in which the memory cells are in an adjacent direction. And a second voltage applying means capable of applying a different potential.

According to the means (1), (a) each memory cell can be set to a different potential from the adjacent memory cells in the row and column directions by applying a voltage using the first voltage applying means. Since each memory cell can be set to a different potential from adjacent memory cells in the oblique direction by applying a voltage using the second voltage applying means, each memory cell can be set to a different potential from all surrounding memory cells. Accordingly, by applying these voltages, a short circuit failure due to an unetched portion or a foreign substance attached to an adjacent memory cell can be reliably detected.

(B) The semiconductor device of the present invention has a simple first
And the second voltage applying means, the number of transistors constituting the means is reduced, and the area of the semiconductor device is reduced. Therefore, in the manufacture of a semiconductor device, the number of semiconductor devices obtained from one wafer increases, and the manufacturing cost of the semiconductor device can be reduced.

[0023]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments of the present invention, components having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

Embodiment 1 FIGS. 1 to 16 show a semiconductor device (DRA) according to an embodiment (Embodiment 1) of the present invention.
FIG. 3M is a diagram relating to pass / fail detection of a memory cell.

Here, the memory cell array of the DRAM in which the external application circuit of the first embodiment is incorporated will be described first.

FIG. 2 is a plan view of a packaged DRAM according to the first embodiment of the present invention, FIG. 3 is a schematic plan view of a DRAM in a semiconductor chip state, and FIG.
FIG. 5 is a partial equivalent circuit diagram of the DRAM, FIG. 6 is a more detailed partial circuit diagram of the DRAM, and FIG. 7 is a schematic sectional view of the DRAM.

The DRAM 50 of this embodiment is as shown in FIG. 3 in the state of the semiconductor chip 51, and is as shown in FIG. 2 in the state of the package. As shown in FIG. 3, pads 55 are provided in a line along the center of the semiconductor chip 51. These pads 55 serve as connection points for wires in a packaged state, and are used as electrode pads at the time of characteristic inspection such as wafer inspection.

As shown in FIG. 3, the present invention is characterized in that pads TEST1, pad TEST2, and pad TEST3 are provided in a row of pads 55, and a circuit connected to these pads TEST1 to TEST3 is provided. It is.

The DRAM 50 shown in FIG. 2 has an external appearance in which leads 58 serving as external electrode terminals are projected from both sides of a rectangular package 57 at regular intervals. FIG. 2 is an example of a 64 MDRAM. Power supply terminals Vcc and Vss and address terminals A0 to A1 are located on the sides of each lead 58.
1, functions such as input terminals I / O0 to I / O7 are shown.
In correspondence with these leads 58, pads 55 (for example, pads A0 to A11, pads Vcc,
Vss). These pads 55 and leads 5
8 is electrically connected in the package 57.

FIG. 4 is a layout diagram schematically showing each circuit portion of the DRAM. As shown in FIG. 4, a configuration is provided in which a large number of memory arrays 25 </ b> A are arranged in a matrix along the X direction and the Y direction and have four memory array groups 25. A sense amplifier circuit SA is arranged between the memory arrays 25A adjacent to each other along the X direction. In an area 26 sandwiched between the memory array groups 25,
A word driver circuit (WD shown in FIG. 5), a control circuit such as a bit line selection circuit, an input / output circuit, pads, and the like are arranged.

As shown in FIG. 5, the memory array 25A includes a plurality of word lines WL arranged in a matrix.
(Extending along the Y direction [row direction]) and the word line W
The configuration includes a bit line BL (data line) extending orthogonally to L (X direction [column direction]), and a plurality of memory cells M and the like arranged at intersections of these. One memory cell M for storing one bit of information has a configuration having one information storage capacitor C and one memory cell selecting field effect transistor Q connected in series to the capacitor C. Field effect transistor Q for memory cell selection
Is electrically connected to the bit line BL, and the other is electrically connected to the charge storage capacitor C. One end of the word line WL is connected to the word driver circuit WD, and one end of the bit line BL is connected to the sense amplifier circuit SA.

This memory cell array has a complementary bit line configuration (BL, / BL), and a pair of bit lines B
L and / BL are connected to an equalizer EQ operated by an equalizing signal EQ1 and a reference precharge voltage VPL.

Next, a specific configuration of the memory cell M will be described with reference to FIG. The field effect transistor Q for selecting a memory cell of the memory cell M is formed in an element formation region on a main surface of a p-type semiconductor substrate 1 made of, for example, single crystal silicon having a specific resistance of about 10 Ωcm. The periphery of the element formation region is defined by an element isolation region on the main surface of the p-type semiconductor substrate 1. An n-type well region 5 and a p-type well region 6 are formed in the element formation region. A groove 2 is formed in the element isolation region, and an insulating film 4 made of, for example, a silicon oxide film is embedded in the groove 2.

Field effect transistor Q for memory cell selection
Is mainly composed of a p-type well region 6 used as a channel formation region, a gate insulating film 7, a gate electrode 8 integrated with a word line WL, and a pair of n-type semiconductor regions functioning as a source region or a drain region ( An impurity diffusion region 10 and a pair of n-type semiconductor regions 12 are provided. The pair of n-type semiconductor regions 10 are formed in self-alignment with the gate electrode 8 and the cap insulating film 9 provided on the gate electrode 8, and the pair of n-type semiconductor regions 12 are provided on side walls of the gate electrode 8. It is formed in self-alignment with the sidewall spacer 11. The pair of n-type semiconductor regions 10 is formed with a lower impurity concentration than the pair of n-type semiconductor regions 12. That is, in the memory cell selection field effect transistor Q, a portion of the drain region on the channel forming region side is set to have a lower impurity concentration than other portions.
It has a DD (Lightly Doped Drain) structure.

The gate insulating film 7 is formed of, for example, a silicon oxide film, and the gate electrode 8 is formed of, for example, a polycrystalline silicon film into which phosphorus (P) is introduced as an impurity for reducing the resistance value. The cap insulating film 9 and the side wall spacer 11 are formed of, for example, a silicon nitride film having selectivity with respect to the insulating film 4.

One n-type semiconductor region 12 of the pair of n-type semiconductor regions 12 is connected via a conductive plug 15 buried in a connection hole 14A reaching the back surface from the surface of the interlayer insulating film 13 on the upper layer. Are electrically connected to a bit line BL extending on the surface of the interlayer insulating film 13.

The charge storage capacitor C of the memory cell M
It is arranged on an interlayer insulating film 16 formed above the bit line BL. That is, the DRAM has a COB structure in which the information storage capacitor C is arranged above the bit line BL.

The information storage capacitive element C includes a lower electrode 19,
The structure has a capacitor insulating film 22, an upper electrode 23, and the like. The lower electrode 19 is formed of, for example, a polycrystalline silicon film into which phosphorus (P) is introduced as an impurity for reducing a resistance value. The upper electrode 23 is formed of, for example, a titanium nitride (TiN) film. The capacitor insulating film 22 is formed of, for example, a stacked film including an antioxidant film 20 formed on the lower electrode 19 and a polycrystalline oxide dielectric film 21 formed on the antioxidant film 20. Antioxidant film 20
Is formed of, for example, a silicon oxynitride (SiON) film. The polycrystalline oxide dielectric film 21 is formed of, for example, a single-layer tantalum oxide (TaxOy) film.

The lower electrode 19 is embedded in a conductive plug 18 buried inside the connection hole 17 reaching the back surface from the surface of the interlayer insulating film 16 and in a connection hole 14B reaching the back surface from the surface of the interlayer insulating film 13. The conductive plug 15 is electrically connected to the other n-type semiconductor region 12 of the pair of n-type semiconductor regions 12.

The read operation of the DRAM is performed by the word line WL
To a high voltage to turn on the memory cell selecting field effect transistor Q and to detect the amount of charge stored in the charge storage capacitor C on the bit line BL.
The write operation is performed by accumulating charge in the charge storage capacitor C on the bit line BL.

In the DRAM of Embodiment 1, FIG.
9 and the foreign matter 6 shown in FIG.
An external application circuit for detecting a short-circuit failure position or the like due to the second circuit 2 is provided so as to be incorporated in the word line selection circuit as shown in FIG.

FIG. 6 is a diagram including the memory cell array 25A, the word line selection circuit 30, the bit line selection circuit 40, and the like. The case of the read operation will be described with reference to FIG.

One word line is selected in the word line selection circuit 30 by a combination of word line selection signals.
High. The memory cell selection field effect transistor Q connected to the selected word line is turned on, the charge stored in the charge storage capacitor C changes the bit line potential, and a potential difference occurs between the pair of bit lines. This potential difference is amplified by the sense amplifier and further increased.

On the other hand, a pair of bit lines is selected in the bit line selection circuit 40 by a combination of the bit line selection signals, and the column switch is turned on. The potential of the selected bit line is transmitted to the common bit line via the ON column switch. The potential of the common bit line is transmitted to an output bus signal (not shown) and input to an output buffer circuit.

In this circuit diagram, bit lines of complementary bit lines are represented by Y ₀ to Y _n (here, n = 3), one of which is represented by T as a data value, and the other is represented by B as its inverted data value. Represent. Also, the word line selection signal is set to X _0B ~
X _nB , X _{0T to} X _nT , and the word line address is X _{0 to} X
Indicated by _n-1 .

As shown in FIG. 1, the word line selection circuit generally includes inverters (I1, I2, I3, and I3) at pads 55 constituting each address A ₀ (X ₀ ) to _An (X _n ). I4)
Are connected in series, and the inverters (I1, I2, I3, I4
) Outputs word line selection signals X _{0T to} X _nT . The node F between the inverter I2 and the inverter I3
Inverter I5 is connected, a word line selection signal X _0B to X _nB is output from the inverter I5 on. These word line selection signal as shown in FIG. 6, is output through the AND of 3 inputs to each word line X ₀ ~X _n-1, is applied to the gate electrode of the MOSFET of the memory cell.

The above circuit configuration is a conventional configuration. In the first embodiment, the pads TEST1, TEST2, and TEST3 are provided as described above. Further, each address A ₀ (
X ₀₎ in ~A _n (X _n), between the inverter I4 and the node H of the output side of the output side of the node G and the inverter I5, connect the configured transfer switch S _T1 in NMOS and PMOS, Inverter I5 and Inverter I
5 between the transfer switch S and the node H on the output side.
The _T2 inserted and connected, PMOS of the transfer switch S _T1
The gate electrode of the NMOS gate electrode and the transfer switch S _T2 is connected at node J, the transfer switch S _T1 of NMOS gate electrode and the transfer switch S
The gate electrode of the PMOS of _T2 is connected at the node K. Further, the coupling an inverter I ₆ between the pad TEST1 ～TEST3 and node J, pads TEST
It has become the connection configuration of the node L and a node K between 1 ～TEST3 and the inverter I _6.

The pad TEST1 has the address A₀ (X₀ ) No
The pad TEST2 is connected to the address A₁ (X
₁ ), And the pad TEST3 is connected to the address A
_Two (X _Two ) To A_n (X_n ) Node L
You.

In such a circuit, during normal operation, the pad
The signals applied to TEST1 to TEST3 are set to a low potential (Low), and only one word line (high potential: High) is selected.

Next, the inspection of the electrical characteristics of the DRAM will be described. The characteristic inspection is performed in the state of the wafer 70 shown in FIG. Each square portion is a DRAM 50. FIG.
FIG. 3 is a plan view schematically showing a part of the wafer 70, in which pads A0 to A11, pads Vcc and Vss, and pads 55 including pads TEST1 to TEST3 are clearly shown as in FIG. In the characteristic inspection, a probe of a measuring device is brought into contact with these pads 55, and an inspection is performed by applying a predetermined potential to each. In the burn-in test, a predetermined potential is applied for a predetermined time.

The inspection of the memory cell failure due to the remaining portion of the etching and the adhesion of the foreign matter according to the first embodiment is performed before the usual burn-in test, and is short-circuited by an acceleration test for selectively applying a high potential "1" to the memory cell. The purpose is to clarify the defective part. That is, the test is performed as shown in FIG.
The test is performed in accordance with the test stage (step: S) shown in the flowchart of FIG. The voltage application in the flowchart shown in FIG. 11 is performed by the first voltage application unit, and the voltage application in the flowchart shown in FIG. 15 is performed by the second voltage application unit.

Here, the defect inspection by the first voltage applying unit and the defect inspection by the second voltage applying unit will be described separately, but the present invention is not limited to this.

The defect inspection by the first voltage applying means is shown in FIG.
As shown in FIG. 1, the process starts with S101. In S101, the wafer 70 shown in FIGS. 8 and 9 is prepared.

Next, in the test mode, the even-numbered word lines (X ₀ , X ₂ ,..., X _m-1 ) are selected (S 102), and the Y address (Y _{0 to} Y _m ) is selected, and a low potential is set. "0" is written (S103). The odd-numbered word lines (X
_{1, X 3, ... X m} ) and select (S104), selects the Y address (Y ₀ to Y _m) writes "1" as the high potential (S105).

In the circuit of FIG. 1, the TEST1 signal is set to Low.
Then, set the TEST2 and TEST3 signals to High. Word line selection
Alternative address A₀ (X₀ ) Is the odd-numbered word line X₀ , X
_Two , X_Four , ... X_m-1 High when selecting
Eye word line X₁ , X_Three , X _Five , ... X_m When selecting
Is Low. At this time, the other address A₁ (X₁)
~ A_m (X_m ) Inputs High and (X_1T, X_1B), (X
_2T, X_2B), ..., (X _mT, X_mB) Is output High
So that

According to S103, the capacitance value of the memory cell becomes
As in the left side of the table of Figure 11 shown at the destination of the arrow, X _0, X
_2, X _4, ... capacitance value in X _m-1 becomes "0", S10
5, the capacitance value of the memory cell is changed to the value shown in FIG.
As one of the left side of the _{table, X 1, X 3, X} 5, ... X capacitance value in _m becomes _{"1", X 0, X} 2, X 4, and ... X _m-1 In "0" maintain.

By applying the high potential in S105, FIG.
In the memory cell portion (the defective memory cell) where the 8 short-circuit generators 60 are located, the failure is accelerated and converted into a failure that can be reliably detected in a subsequent function test.

Next, addresses (X ₀ , Y ₀ ) to (X _m ,
Y _m ), the capacitance value is sequentially read (S106), a determination is made (S107), and the process ends (S108).

In the determination of S107, the capacitance value of the memory cell is as shown in the table on the left side of FIG. In the table above, X ₀ and X ₁ in Y ₀ are both “0”, which indicates that a short circuit has occurred.
This state is a leak path A (short defect) between the same Y address and adjacent X address, a short circuit shown in FIG. 13 in terms of circuit, and a state shown in FIG. 12 in the layout of the memory cell.

In the table below, the leak path B between the memory cell portion of (X ₀ , Y ₀ ) and the memory cell portion of (X ₁ , Y ₁ )
The short circuit shown in FIG.
The layout of the memory cell is as shown in FIGS. The leak path B is a leak (short defect) between the adjacent Y address and the adjacent address.

By the defect inspection by the first voltage applying means, as shown in FIGS. 10 and 12, the detection of the leak path (short defect) in the adjacent row direction and column direction can be achieved. FIGS. 10 and 12 show each potential node in the memory cell as an ellipse or a rectangle with rounded corners. The light black potential node portion is a high potential portion, and the white potential node portion is a low potential portion. The High potential node and the Low potential node are shown in FIG.
Are one lower electrode 19 and the other lower electrode 19 of the information (charge) storage capacitance element C shown side by side. Therefore, the remaining etching portion 61 shown in FIG.
When there are defective memory cells in which the foreign matter 62 shown as 0 exists, these defective memory cells accelerate by the application of a voltage.

Next, the defect inspection by the second voltage applying means will be described with reference to FIGS. S
After the start by 201, every other two word lines (X ₀ , X ₁ , X ₄ , X ₅ ,..., X _m-3 , X
_m-2) select (S202), Y address (Y ₀ to Y
_m ) and write "0" (S203). The remaining word lines (X ₂ , X ₃ , X ₆ , X ₇ ,..., X _m-1 ,
X _m) and select (S204), Y address (Y ₀ to Y
_m ) and write "1" (S205).

In the circuit of FIG. 1, the TEST2 signal is set to Low, and the TEST1 and TEST3 signals are set to High. The word line selection address A ₁ (X ₁ ) corresponds to the word lines X ₀ , X ₁ , X ₄ ,
When selecting X ₅ ,..., X _m-3 , X _m-2 , set High.
When selecting the word lines X ₂ , X ₃ , X ₆ , X ₇ ,..., X _m−1 , X _m , it is set to Low. At this time, the other addresses A ₀ (X ₀ ) _, A ₂ (X ₂ ),..., ~ A _m (X _m )
High is input, and X _0T , X _0B ), (X _2T , X _2B ) _,.
High is output to (X _mT , X _mB ).

According to S203, the capacitance value of the memory cell becomes
As shown in the table on the left side of FIG. 15 at the end of the arrow, every third address X ₀ , X ₁ , X ₄ , X ₅ ,..., X _m-3 ,
At X _{m− 2} , the capacitance value becomes “0”. At S 205, the capacitance values of the remaining addresses become X ₂ , X ₃ , X ₆ , X ₆ as shown in the table on the left side of FIG. ₇ ,…, X _m-1 ,
At _Xm , the capacitance value becomes "1". Therefore, this S205
The high potential application accelerates the defect in the memory cell portion (the defective memory cell) where the short-circuit generator 60 shown in FIG. 18 is located, and converts the defect into a defect that can be reliably detected in a subsequent function test (function test). become.

Next, addresses (X ₀ , Y ₀ ) to (X _m ,
Y _m) sequentially reads the capacitance value from (S206), the determination was carried out (S207), and ends (S208).

In the determination in S207, the capacitance value of the memory cell is as shown in the left table of FIG. In this table, since (X ₂ , Y ₁ ) is supposed to be “1” and is “0”, this is the leak path D (short fault) between (X ₀ , Y ₀ ). )
It can be seen from the layout of the memory cell in FIG. The leak path D is a short circuit shown in FIG. 17 in terms of a circuit, and is a leak path (short circuit) between an adjacent Y address and one sandwiched X address. Therefore, in the inspection by the second voltage applying means, as can be seen from FIG. 16, it is possible to detect a short-circuit failure between adjacent memory cell portions in the oblique direction.

By performing the defect inspection by the first and second voltage applying means, it is possible to detect the presence or absence of short-circuit defects in the row, column, and diagonal directions adjacent to the aligned memory cells. That is, the short generator 60 shown in FIG.
It is possible to reliably detect the presence / absence of a short-circuit failure due to the above-mentioned factors between the entire adjacent memory cells.

After the characteristic inspection by the first and second voltage applying means, a function test is performed, and the inspection of the DRAM is completed.

According to the first embodiment, (1) In the semiconductor device (DRAM 50) of the first embodiment, each memory cell is applied by applying a voltage using the first voltage applying means using a simple external application circuit. Can be set to a different potential from the adjacent memory cells in the row and column directions, and each memory cell can be set to a different potential from the adjacent diagonal memory cells by applying a voltage using the second voltage applying means. The memory cell can be set to a different potential from all the surrounding memory cells. Accordingly, by applying these voltages, a short circuit failure due to an unetched portion or a foreign substance attached to an adjacent memory cell can be reliably detected.

(2) The semiconductor device of the present invention has a simple first
And the second voltage applying means, the number of transistors constituting the means is reduced, and the area of the semiconductor device is reduced. Therefore, in the manufacture of a semiconductor device, the number of semiconductor devices obtained from one wafer increases, and the manufacturing cost of the semiconductor device can be reduced.

The invention made by the inventor has been specifically described based on the embodiment. However, the invention is not limited to the above embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say.

Although the example in which the present invention is applied to a DRAM has been described above, the present invention can be applied to other semiconductor devices and has similar effects. The present invention can be applied to a semiconductor integrated circuit device having a digital circuit or an analog circuit having a circuit configuration including a capacitor. Also,
The present invention can be applied to a semiconductor integrated circuit device having a storage circuit including a capacitor, such as a DRAM, an SRAM, or a flash memory.

[0073]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

(1) Use of a first voltage applying means and a second voltage applying means using a simple selective voltage applying circuit for detecting a defect between adjacent information storage capacitance elements C including a short-circuit defect. Can be easily and accurately detected.

(2) In a semiconductor device with a simple selective voltage application circuit, the number of transistors constituting the voltage application circuit can be reduced, and the area of the semiconductor device can be reduced. Therefore, in the manufacture of a semiconductor device, the number of semiconductor devices obtained from one wafer increases, and the manufacturing cost of the semiconductor device can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a part of a semiconductor device (DRAM) according to an embodiment (Embodiment 1) of the present invention.

FIG. 2 is a plan view showing the DRAM in a package state according to the first embodiment;

FIG. 3 is a schematic plan view showing a DRAM (semiconductor chip) of the first embodiment.

FIG. 4 is a schematic plan view of the semiconductor chip.

FIG. 5 is an equivalent circuit diagram showing a part of the DRAM according to the first embodiment of the present invention;

FIG. 6 is an equivalent circuit diagram showing a part of a DRAM connected to the circuit of FIG. 1;

FIG. 7 is a schematic sectional view of the DRAM according to the first embodiment of the present invention;

FIG. 8 is a schematic plan view showing a wafer on which the semiconductor device of the first embodiment is formed.

FIG. 9 is a schematic plan view showing a semiconductor device portion in the wafer state.

FIG. 10 is a schematic diagram showing the relationship between memory cells that can be tested for pass / fail in the semiconductor device test method according to the first embodiment.

FIG. 11 is a flowchart showing a first half of a test method of the semiconductor device according to the first embodiment and a table showing capacitance values at the time of writing;

FIG. 12 is a schematic diagram showing a memory cell defect that can be detected in the first half of the process.

FIG. 13 is a circuit diagram showing a memory cell defective portion that can be detected in the first half step.

FIG. 14 is a circuit diagram showing a memory cell defective portion that can be detected in the first half step.

FIG. 15 is a flowchart showing the latter half of the test method of the semiconductor device of the first embodiment and a table showing the capacitance value at the time of writing.

FIG. 16 is a schematic diagram showing a memory cell defect that can be detected in the latter half of the process.

FIG. 17 is a circuit diagram showing a memory cell defective portion that can be detected in the first half step.

FIG. 18 is a schematic plan view of a part of a memory cell showing a short-circuit failure state between electrodes of an information storage capacitive element C;

FIG. 19 is a schematic cross-sectional view of a capacitor portion showing a short-circuit failure state due to residual etching.

FIG. 20 is a schematic cross-sectional view of a capacitance portion showing a short-circuit failure state due to foreign matter adhesion.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... p-type semiconductor substrate, 2 ... groove | channel, 3 ... insulating film, 4 ... insulating film, 5 ... n-type well region, 6 ... p-type well region, 7 ... gate insulating film, 8 ... gate electrode, 9 ... cap insulation Membrane, 1
0 ... n-type semiconductor region, 11 ... sidewall spacer,
12 ... n-type semiconductor region, 13 ... interlayer insulating film, 14A, 1
4B: connection hole, 15: conductive plug, 16: interlayer insulating film,
17 connection hole, 18 conductive plug, 19 lower electrode, 2
0: antioxidant film, 21: polycrystalline oxide dielectric film, 22:
Capacitance insulating film, 23: upper electrode, 25: memory array group,
25A: memory array, 26: area, 30: word line selection circuit, 40: bit line selection circuit, 50: DRAM, 5
1: semiconductor chip, 55: pad, 57: package,
58 ... lead, 60 ... short generator, 61 ... etching residue portion, 62 ... foreign body, 70 ... wafer, A ₀ (X ₀₎ ~
_An ( _Xn ) ... address, A, B, D ... leak path, C
... charge storage capacitor, F, G, H, J , K, L ... node, I1, I2, I3, I4 , I 6 ... inverter, M ...
Memory cell, Q ... for memory cell selection field effect transistor, S _T1, S _T2 ... transfer switch, TEST1, TEST
2, TEST3 ... pad, X ₀ ~X _n-1 ... word line _{address, X 0B ~X nB, X 0T} ~X nT ... word line selection signal, Y ₀
~Y _n ... bit line.

 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Toshiyuki Suzuki 64 Nagano Numa, Tenno-cho, Tenno-cho, Minami-Akita-gun Akita Electronics Co., Ltd. MA03 MA06 MA17 MA20 ZA20 5L106 AA01 DD35 EE02 FF01 GG00

Claims (1)

[Claims] 1. A plurality of word lines arranged in a row direction in parallel, a plurality of bit lines arranged in a column direction orthogonal to the word lines, and the word lines and the bit lines intersect. A memory cell array including a memory cell provided at a portion where the information storage capacitor is formed. A first voltage applying means capable of applying each memory cell to a potential different from that of an adjacent memory cell in a row direction and a column direction; and And a second voltage applying means capable of applying different potentials.