JPS60211689A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To enable a quick changeover of an intermediate voltage given to an opposite electrode by providing two terminal for outputting potentials corresponding to active and standby states of memory for a pressure-dividing circuit, by selecting the opposite electrode with the aid of a switching element and by connecting it. CONSTITUTION:A memory cell of one transistor and one capacitor is provided. An intermediate voltage obtained by dividing a supply voltages VCC and VSS is impressed on an opposite electrode OP at the opposite side of the transistor of the capacitor of the memory cell. A high resistance dividing circuit VD for outputting the intermediate voltage is provided with two terminals for generating an output OH at a high level and an output OL at a low level, while the electrode OP is selected by switching transistors Q3 and Q4 and connected to either two terminal. Thus the memory can switch the intermediate voltage given to the electrode OP to high and low levels when it is active and standby.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a semiconductor memory device having a one-transistor, one-capacitor type memory cell in which a counter electrode of the capacitor is at an intermediate potential between a power supply voltage and a ground potential.

Conventional technology and problems The memory cell of a Guinamisoku type semiconductor memory device is generally one
The transistor 1 is a capacitor type, and the capacitor is configured as a MOS type in which the insulating film on the surface of the semiconductor substrate is used as a dielectric, the metal or polycrystalline silicon on the insulating film is used as one electrode, and the semiconductor substrate below it is used as the other electrode. In particular, one electrode (referred to as the counter electrode) is supplied with a power supply voltage +Vcc.
It is widely used to add a p-type semiconductor substrate under the p-type semiconductor substrate to n-inversion and use it as the other electrode. Also, the voltage applied to the counter electrode does not have to be Vcc; if the substrate is made n-type by diffusing n-type impurities, the potential of the counter electrode is set to the power supply voltage Vcc.
It may be an intermediate potential between cc and the ground potential of 0 volts, or it may be the ground potential itself.

As memories become larger and larger, memory cells tend to become smaller and smaller. Miniaturization requires uniform scaling of all parts, and as a result, insulating films and the like must also be made thinner, which poses problems in terms of withstand voltage. Vcc is applied to the opposing electrode of the capacitor, and Vcc is applied to the other electrode, that is, the semiconductor substrate.
When a charge is stored or not stored at c (data “1” or “0” is stored), the potential of the other electrode becomes Vcc or Vs.
s (O volts), a maximum of Vcc is applied to the insulating film of the capacitor. If the film is thin, a strong electric field will be generated, which may cause dielectric breakdown of the insulating film. Therefore, it has been considered to apply an intermediate potential, for example, Vcc/2, to the counter electrode. In this case, the other electrode is V cc, V
The potential difference with the counter electrode for both ss is Vcc/2
This is half of the above value, and the problem of dielectric breakdown is greatly reduced. FIG. 1 shows the main parts of such a dynamic memory.

In FIG. 1, WL is a word line, BL, BL are a pair of human lines,
SA is a sense amplifier, and MC is a memory cell consisting of a transistor Q+ and a capacitor CI. The voltage divider circuit VD connects two resistors R1 and R2 with the same resistance value to Vcc
and Vss, and this intermediate connection point is connected to the cell counter electrode OP. The counter electrode OP is common to many memory cells, and is shown in the figure in the form of a wiring similar to a word line. E is the other electrode, which may be integrated with the source of 1 herange disk Q1.

The connection between this other electrode E and the source of the transistor Q is indicated by a node N1.

By the way, the counter electrode OP has a large area, and the bit lines BL,
It intersects with BL etc. and there is a large R and free capacitance C between them.
As a result of having p1, Cp2, etc., potential fluctuations occur due to capacitive coupling as the potentials of these signal lines change. Therefore, in order to maintain the potential of the counter electrode OP exactly at Vcc/2, the time constant between these stray capacitances and the resistance in the voltage dividing circuit VD becomes a problem. Of course, the smaller this time constant is, the better.

However, since the current flowing through the resistors R1 and R2 continues to flow as long as the memory chip is powered on, R+
.

If R2 is made small, power consumption increases all the time. Therefore, resistors R1 and R2 must have high resistance to avoid an increase in power consumption. However, if the values of the resistors R1 and R2 are large and the counter electrode OP cannot be charged or discharged immediately, the potential of the counter electrode fluctuates due to the coupling with the bin 1- line etc. due to the parasitic capacitance. The details of this variation are quite complicated, but if you dig deeper, they are as follows. That is, in the memory, the sense amplifier SA operates to set one of the pin 1 lines BL and BL to an H (high) level or Vcc, and the other to an L (low) level, i.e., Vcc.
ss, and a standby state in which the sense amplifier SA does not operate and the bit lines BL and BL are charged to the H level Vcc, but if the charging and discharging by the voltage divider circuit is ignored due to the time constant, the opposite When the electrode OP is active, it takes a lower potential than when it is standby by the amount of variation due to capacitive coupling of one of the parasitic capacitances Ml Cp l or Cp.

When active and standby are repeated, the counter electrode potential fluctuates between the above two values, but in reality, this is affected by charging and discharging of parasitic capacitance. That is, OP = Vcc
/ 2, Cp2 is charged with a polarity in which the OP side is + and the BL side is -, and the voltage V cc / 2 of the polarity is b. In this state, when BL=Vcc, OP is pushed up by the voltage of Cp2, and at the same time the parasitic capacitance Cp+, CI)
In step 2, charging and discharging of charges is performed. OP pushed up
When the potential of Cp+ and OP2 is T+ΔvH, the voltage of Cp+ and OP2 is T−ΔVH, and the polarity of the charged charge of Cp2 is opposite to that before.

When BL becomes Vss again in this state, OP is pushed down by Cp2, and at the same time, parasitic capacitances Cp+ and Cp2 are charged and discharged. This depressed OP nature returns to its initial state. If the standby period and the active period are the same length, Δ■H is equal to ΔvL.

When active and standby are repeated in a short period of time, and the active period or standby period becomes long, the OP is given Vcc/2 by the voltage divider circuit VD, so it will not fall to this Vcc/2. become. Vcc
/ 2, for example, what was on standby becomes active and becomes BL=L, a pushdown occurs due to CI) 2, and the potential of OP also changes to -(ΔvL+ΔVH). Become. In the above explanation, this is □2 - ΔVL, but this is because the previous state was at 〒+8 to H, and the fluctuation range is the same AvL+ΔVH. The same thing happens when what has been active until now changes to standby; in this case, it is pushed up to □+ΔVH→-Δ■5.

Such fluctuations in the potential of OP similarly occur when the ratio between the active period and the scan high period changes over a relatively long period of time. As mentioned above, the reason for applying the intermediate potential V cc/2 to the counter electrode is to prevent insulation deterioration of the insulating film, or because the potential of the counter electrode changes significantly as described above, it is not appropriate to use an intermediate potential. The number of seaweed fruits will be reduced. In addition, the potential of the opposing electrode OP affects the potential of the other electrode E, and hence the note N1, and when the potential of OP drops significantly, the potential of I'J+ also drops significantly, causing the sense amplifier SA to malfunction, resulting in data "1" storage state. There is also a possibility that the data "'0" storage state may be erroneously determined.

Therefore, the inventor of the present invention considered switching the output of the voltage divider circuit VD between active and standby states, and previously proposed this (Japanese Patent Application No. 57-211146).

The resistor R3 and MOS) transistor Q2 in Figure 1 are now
By turning on and off transistor Q2 with clock φA, the output level of the voltage dividing circuit is set to H.

Change to L. That is, if the clock φA is set to H1 during active and L during standby, then when active, transistor Q2 is turned on and resistor R3 is connected in parallel to resistor R2, lowering the output of the voltage divider circuit, and during standby, transistor Q2 is turned off and resistor R3 is connected. and increase the output of the voltage divider circuit. To set the average potential of OP to Vcc/2, R
1 and R2 have different resistance values. In other words, the I] level output of the voltage divider circuit VD is the above □10ΔVH, and the L level output is c
If c T ~ Δ■ is selected, even if the active period and the high-speed period become longer, there will be no change because the settling time of the counter electrode potential and the output level of the voltage divider circuit are the same. The counter electrode potential does not change significantly upon restart.

However, this proposed circuit also has drawbacks.

That is, as mentioned above, in order to reduce power consumption, the resistor R
1 and R2 have a high resistance, and the resistor R3 also has a high resistance, but if the resistance is high, it will create a parasitic capacitance and a large time constant. In particular, when a MOS transistor Q2 is used to insert and remove the resistor R3, it has a large source and drain capacitance, so even if the transistor Q2 is turned off, the potential of the node N2 does not rise immediately, and the resistor R3 It will be in the same state as if it were connected. FIG. 2 is a diagram for explaining this, and a curve N2 shows a change in the potential of the node N2. Similarly, the curve φΔ shows the clock ψA, and the curve OP shows the potential change of the counter electrode OP. RA■ is a row address strobe signal, which is applied from the outside, and when it is at L level, the sense amplifier SA of the memory chip becomes active, and when it is at H level, it becomes standby.

As mentioned above, when activated, the bit line BL.

The power of BL becomes H1 and the other becomes L, the potential of the counter electrode OP decreases, and when the bit line BL becomes standby.

Both BL become H, and the potential of the opposing electrode increases. The clock φA is set to H or L in accordance with the potential change of the counter electrode OP, and the output level of the voltage dividing circuit VD is changed. That is, in the active state, φA is set to I], transistor Q2 is turned on, node N2 is dropped to Vss, and resistor R3 is connected in parallel to R2. Since this can be done immediately, the output of the voltage divider circuit quickly becomes L level. However, in standby, the clock φA
Even if the voltage is set to L and the transistor Q2 is turned off, the potential of the node N2 hardly increases as shown in the figure. Note'N
In order to raise the potential of node 2, it is necessary to charge the node through high resistances R1 and R3, but this takes time. If the potential of node N2 does not rise, this will cause resistor R3 to become resistor R2.
The output of the voltage divider circuit VD is L.
level. In this state, the potential of OP is low and Cpl
, CI) 2 is BL.

The BL side is set to 100% and charged to a high voltage, and in this state it becomes active and, for example, when BL becomes Vss, OP is strongly pushed down, which may cause deterioration of the capacitor insulating film and erroneous reading of stored data.

OBJECTS OF THE INVENTION The present invention aims to improve the above points and to make it possible to quickly switch the intermediate potential applied to the opposing electrode between H and L.

Structure of the Invention The present invention comprises a one-transistor, one-capacitor type memory cell, and an intermediate voltage obtained by dividing a voltage of 'fA' by a voltage dividing circuit is connected to a counter electrode of the capacitor of the memory cell on the opposite side from the transistor. In a semiconductor memory device that applies a voltage, the voltage divider circuit is provided with two terminals that output two types of potentials corresponding to when the memory is active and when it is on standby, and a switching element connects the opposing electrode to either of the two terminals. Next, this will be explained with reference to embodiments.

Embodiment of the Invention FIG. 3 shows an embodiment of the present invention, in which the same parts as in FIG. Equipped with two terminals that produce output,
The counter electrode OP is connected to one of these two terminals by the switching transistor Q3. Select in Q4 and connect. Resistors R+ and R2 are for the 111 level output, and resistors R4 and R3 are for the L level.
It is a level output circuit, and N3. Na is its output terminal. When clock φA is at H level, transistor Q4 is turned on and applies L level output OL to counter electrode OP.

Further, when the clock 8 having the opposite phase to the clock φΔ is at the H level, the transistor Q3 is turned on, and the I-ruher output oH is applied to the counter electrode OP. 1-1 of the counter electrode ○P when repeating standby as described above. Select R2 potential. In this way, even if the active and standby periods become longer, there is no change in the potential of the counter electrode. This voltage divider circuit has its output terminal N3. Two voltages, H and R, are always generated at N4, one of which is connected to switching element Q3. Q,
Since the voltage is simply selected by I and applied to the counter electrode OP, the voltage is applied immediately, and there is no problem that the desired potential is not directly reached due to the time constant as in the circuit of FIG.

FIG. 4 is a diagram similar to FIG. 2, or shows a clock φΔ in addition to the clock φA.

Although RAS is not shown, RAS becomes L level and the potential of the counter electrode OP decreases, and RAS becomes 11 and the potential of the counter electrode OP increases. The clock ψA rises after OP falls and falls before OP rises. Similarly, the clock φA is started up after OP goes up and is stopped before OP goes down.

While the potential of OP is changing, both φΔ and 6 are at L, transistors Q:+ and Q4 are off, and the counter electrode OP is in a floating state.

The reason why the counter electrode OP is separated from the voltage dividing circuit while the potential of the counter electrode OP is changing is as follows. Immediately, RAS goes low, the sense amplifier operates, and the potential of OP drops, but this potential change is not sudden. Therefore, OP is sufficiently 1/2Vcc-ΔV
If φA is increased and Q4 is turned on before reaching the potential of L, that is, oL, it will take only a short time or Q4. 'N
4. Current flows out to Vss through R3. Since the resistance of R3 is also high, the amount of outflow at one time is small, but if such a phenomenon is repeated many times, the potential of OP will decrease. Also, when φA falls, a similar problem will occur unless φA is lowered and Q4 is completely turned off before OP rises. This problem also applies to φA. And O
Due to the difference in the amount of current flowing out when the P potential falls and rises, the active and standby states are repeated, and the O
The potential of P will change. In order to avoid this, as shown in FIG. 4, φ4 or φ3 is turned on only when the OP potential is completely OL or OH, and when the OP potential changes, Q4. This is possible by turning off both Q3.

FIG. 5 does not show another embodiment of the invention. R5-R7 is 31
It has a high resistance of 11il and is connected in series between the power supplies Vcc and Vss. The counter electrode OP is the switching transistor Q3. Q4 to node N5. N6, that is, the series connection point of resistors R5 and R6, and the series connection point of resistors R6 and R7. 1-transistor Qg, C; La's G1- is connected to the clock φ, φΔ is added, and the node N5. Since N6 produces H and L level outputs oH and oL (R5-R7
3), the same operation as in FIG. 3 is performed. In terms of power consumption, FIG. 5 is more advantageous than FIG. 3.

It goes without saying that the resistors R1 to R7 may be constructed of transistors or the like in addition to diffused resistors.

DETAILED DESCRIPTION OF THE INVENTION As described in detail, in the present invention, the memory repeats activation and standby of the intermediate potential applied to the counter electrode of the cell capacitor by the high resistance voltage divider circuit, and as a result, the counter electrode becomes H, which is given by its parasitic capacitance. 2 equal to L potential
The voltage dividing circuit always outputs the two types of potential at the same time, and one of them is selected and applied to the opposite electrode, so the voltage is applied to the opposite electrode at the same time as the selection. Therefore, the voltage application is not delayed due to a time constant associated with a high resistance circuit.

[Brief explanation of drawings]

Figure 1 is a circuit diagram explaining the proposed method, Figure 2 is a waveform diagram explaining its operation, Figure 3 is a circuit diagram showing an embodiment of the present invention, Figure 4 is a diagram explaining its operation, and Figure 5 is a diagram explaining its operation. 7 is a circuit showing another embodiment. In the drawing, MC is a memory cell, Ql is its transistor,
C+ is a capacitor, OP is a counter electrode, and Cpl. CI)2 is a parasitic capacitance, VD is a voltage dividing circuit, N3. N4 is the output terminal, Vcc is the power supply voltage, and Vss is the ground potential.Applicant: Minoru Aoyagi, Patent Attorney, Fujitsu Ltd., Figure 5, VCC Ss Procedural Amendment (Spontaneous), March 23, 1985, Commissioner of the Japan Patent Office, Shiga Gakuden 1, Indication of the case, Patent Application No. 67221 filed in 1982, 2, Name of the invention, semiconductor storage device 3, Person making the amendment, Relationship to the case Patent applicant address: 1015 Kamiodanaka, Nakahara-ku, Yozaki City, Kanagawa Prefecture Name (665) Fujitsu Limited Representative Takashi Yamamoto 4, Agent 101 6, Number of inventions increased due to amendment None 7, Subject of amendment Detailed explanation of the invention in the specification column 8, Amendment Contents (1) "Voltage divider circuit" on page 11, line 5 of the specification is corrected to "high resistance voltage divider circuit."

Claims (1)

[Claims] A memory cell having one transistor and one capacitor type is provided, and an intermediate voltage obtained by dividing the power supply voltage by a voltage dividing circuit is applied to the opposite electrode of the capacitor of the memory cell on the opposite side from the transistor. In a semiconductor memory device, the voltage dividing circuit is provided with two terminals that output two types of potentials corresponding to when the memory is active and when it is on standby, and the opposing electrode is selectively connected to one of the two terminals by a switching element. A semiconductor memory device characterized in that it is configured to perform the following steps.