JPH0335493A - Dynamic semiconductor memory device - Google Patents

Abstract

PURPOSE:To reduce stress for the memory cell transistor of a maximum power supply potential and to improve reliability by comparing the second potential with the power supply potential, outputting a control signal when the second potential is higher and reducing the potential of an output terminal. CONSTITUTION:To a first potential Vpp 1 to be boosted in proportion to a power supply potential Vcc, a second potential Vpp 2 lower than this first potential by a fixed value is acquired by a level shift circuit 2. A comparator circuit 3 compares the second potential Vpp 2 with the power supply potential Vcc and when the second potential Vpp 2 is higher, the control signal is outputted. A discharging circuit 4 in an output terminal WKM in a boosting circuit 1 is controlled by the control signal from the comparator circuit 3 and the potential of the output terminal WKM is forcively reduced. Accordingly, when the boosting ratio of a word line is determined so that '1' reading defect can not occur in the minimum potential, the potential of the word line is suppressed with a value for which a prescribed value is added to the power supply potential. Thus, the potential of the word line in the maximum potential is made low and the reliability of an oxide film is secured.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a dynamic semiconductor memory device of a type that boosts a word line.

(Prior technology) Dynamic random access memory (DRAM)
), the degree of integration has increased with advances in microfabrication technology, and as device characteristics have improved due to miniaturization, large capacity and high speed devices have been developed one after another. DRAM currently commercialized
As shown in FIG. 6, the memory cell capacitor 0M consists of a memory cell capacitor 0M and a memory cell transistor 20M connected between the bit line BL and the memory cell capacitor 0M and selectively turned on by the voltage of the word line WL. It has a transistor/one capacitor memory cell structure.

The memory cell transistor 20M is formed of an N-channel transistor. This is because an N-channel transistor is less affected by the short channel effect up to a shorter gate length than a P-channel transistor, which is advantageous for miniaturization.

However, if the memory cell transistor is an N-channel transistor, the potential of the word line becomes approximately Vc
In the same case as c, the potential Vcc of the bit line cannot be directly written to the memory cell when writing "1" data to the memory cell, and the potential actually written to the memory cell varies from Vcc to the voltage of the memory cell transistor QM. It is the value after subtracting the threshold value. In this way, when the write potential of "1" data decreases due to a drop in the threshold of the memory cell transistor, in a DRAM that precharges the bit line to 1/2 Vcc, the bit line when reading data from the memory cell The potential difference between them is smaller when reading "1" data than when reading "O" data, making it more likely that a "1" reading failure will occur. In addition, memory pause characteristics and soft error resistance deteriorate.

For the reasons mentioned above, the current rlE + method uses a method of boosting the word line and directly writing the power supply voltage Vcc into the memory cell.

Next, the potential of the boosted word line will be explained based on FIG. 4. In the figure, VccIlin and Vccmax are the minimum power supply potentials that guarantee the performance of DRAM under normal usage conditions.
This is the maximum power supply potential. In addition, the - dotted chain line (c) is the power supply potential V
It is a straight line whose slope is 1 with respect to cc. Conventionally, in order to facilitate control, the potential VWL of the word line has been boosted at a constant rate (for example, 1.5 V c c ) with respect to the R potential, as shown by the broken line (a) in the figure. The step-up ratio of the word line is determined with a margin so that even at the minimum voltage vccmtn, the difference between the word line potential and the power supply potential is always larger than the threshold of the memory cell transistor.

Since the step-up ratio is constant, the larger the power supply potential,
The potential difference between the word line potential and the power supply potential becomes large, and the potential written in "1", especially the cell, is always equal to the power supply voltage.

However, as DRAMs become smaller and the thickness of the gate oxide film of a MOS transistor becomes thinner, the reliability of the oxide film becomes a problem. Previous reports have stated that in order to ensure the reliability of a thermal oxide film of small crystal silicon, the electric field strength of the oxide film must be suppressed to 4 MV/(7) or less.

However, if the word line potential is boosted at a constant boost ratio, for example, in a 16M DRAM, the maximum potential vcc■a
At X, the electric field strength of the gate oxide film exceeds 4MV/c11.

(Problems to be Solved by the Invention) As described above, in the large ffiDRAM, if the potential of the word line is boosted at a constant boost ratio, the maximum potential Vccsa
There was a problem in that the reliability of the gate oxide film could not be ensured in x. Moreover, at the maximum potential Vccmax,
If the step-up ratio of the word line is lowered to ensure the reliability of the oxide film, there is a problem that a failure occurs when reading "1" data at the minimum potential Vccs I n.

The present invention eliminates the above-mentioned drawbacks and reduces the minimum potential Vccal to
An object of the present invention is to provide a DRAM that can eliminate "1" read failures in n and at the same time ensure reliability of gate oxide films of memory cell transistors at the maximum potential vecsax.

[Structure of the Invention] (Means for Solving the Three Problems) This invention provides a DI? In AM,
A control circuit is provided that forcibly lowers the output terminal potential when the output potential of the booster circuit becomes higher than a value obtained by adding a predetermined value to the power supply potential Vcc. Specifically, this control circuit includes a level shift circuit that is provided at the output terminal of the booster circuit and obtains a second potential that is lower by a predetermined value than the first potential obtained at the output terminal; The booster circuit is comprised of a comparator circuit that compares the two potentials and outputs a control signal when the second potential becomes high, and a discharge circuit that is controlled by the control signal and lowers the potential of the output terminal of the booster circuit.

(Function) According to the present invention, “1” at the minimum potential vccmln
If the step-up ratio of the word line is determined so as not to cause a reading failure, the potential of the word line can be suppressed to a value obtained by adding a predetermined value to the power supply potential at a power supply potential equal to or higher than the minimum potential vccaln. Therefore, the word line potential at the maximum potential Vccsax is lower than in the conventional case, and the reliability of the oxide film can be ensured.

Also in the present invention, the potential of the word line temporarily becomes higher than the power supply potential plus a predetermined value due to the control delay when boosting the word line. However, since the period is much shorter than in the conventional method, the average value of the electric field strength is reduced, the stress applied to the oxide film is reduced, and reliability is improved.

(Embodiment) FIG. 1 shows the configuration of a word line booster circuit 1 and its output potential control circuit section in a DRAM according to an embodiment of the present invention. A level shift circuit 2 is provided at the output terminal WKM of the word line booster circuit 1 .

This level shift circuit 2 provides a second potential Vpp2 that is lower by a certain value than the first potential Vpp1, which is boosted in proportion to the power supply potential Vcc. Comparison circuit 3
is the second potential V obtained from this level shift circuit 2
pp2 and the power supply potential Vcc are compared to determine the second potential Vp.
This circuit outputs a control signal when p2 is higher.

A discharge circuit 4 is provided at the output terminal WKM of the booster circuit 1, and this is controlled by a control signal from the comparator circuit 3 to force the potential of the output terminal WKM when the second potential Vpp2 is higher than the power supply potential Vcc. It is designed to be lowered.

FIG. 2 shows a specific example of the configuration of the circuit portion for controlling the potential shown in FIG. Comparison circuit 3 is a current mirror type CMOS
It is composed of differential circuits 3, 3, CMOS gate circuits 32, 33, and the like.

That is, P channel transistor Q1. Q2, N-channel transistor Q3. Q4 constitutes a current mirror type CMO9 differential circuit 3. Terminal N1 is a reference potential input terminal of this differential circuit 31, and P-channel transistor Q8
．． It is connected to a common drain terminal of a CMOS gate circuit 3□ consisting of an N-channel transistor Q9. Two P-channel transistors Q6., which are diode-connected between the power supply terminal and the source terminal of the transistor Q8. Q7
are connected in series. The terminal N2 is an input terminal of the differential circuit 3, which is a CMOS gate circuit 3 consisting of a P-channel transistor Q12 and an N-channel transistor Q13.
3 common drain terminal.

Two diode-connected P-channel transistors Q11°Q10 and one N-channel transistor Q14 are connected in series to the source terminal of the transistor Q12. An N-channel transistor Q14 constitutes the level shift circuit 2 shown in FIG. 1, and the drain terminal of the transistor Q14 is connected to the output terminal WKM of the word line booster circuit.

This N-channel transistor Q14 is actually a plurality of transistors connected in parallel, each having the same gate length, the same gate width, and the same well potential as the memory cell transistor. That is, this transistor Q14 has a threshold value (VTI+) of the memory cell transistor with respect to the first potential Vpp1 of the booster circuit output terminal WKM.
The second potential Vpp2 is lower by that amount. Further, the terminals Nl and N2 are grounded via resistors R1 and R2. The terminal N3 is an output terminal of the differential circuit 3□, and is connected to the drain terminal of the N-channel transistor Q15 and the input of the inverter INVI. The two-stage inverters INVI and INV2 are drivers that control the gate of the N-channel transistor Q16 that constitutes the discharge circuit 4 and is connected to the output terminal WKM of the word line booster circuit. The source of N-channel transistor QlB is connected to ground potential Vss in this embodiment. Differential circuit 31
The transistor Q1. A gate terminal of a P-channel transistor Q5 connecting between the common source terminal of Q2 and the power supply, and a CMOS gate circuit 32. The gate terminal of 33 is controlled by a control signal RINT synchronized with a row address strobe signal (RAS) to activate this comparison circuit. Note that transistor Q
7. Q8. Back gate bias is not applied to QIO1Qll and Q12°.

Next, the operation of the circuit having the above configuration will be explained with reference to the timing chart of FIG.

In the initial state, the control signal RINT is the power supply voltage Vcc, the transistor Q5 is off, and the differential circuit 31 is in an inactive state. Also, transistor Q8゜Q12 is off Q
9. Q13. Since Q15 is on, terminals Nl and N
2. N3. N4 is the ground voltage Vss. Further, the booster circuit output terminal VKM is precharged to Vcc, but the transistor Q16 of the discharge circuit is turned off.

In the initial state, no through current flows through this circuit.

When the row address strobe signal RAS changes from a high level to a low level, the control signal RINT changes from Vcc to Vss. Then transistor Q8. Q12 is on Q9. Q13 turns off and transistors Q6. Q7
．． Q8, a current 11 from the 1i source Vcc through resistor R1 and transistor Q14. QIO, Q11. Q12,
Current I2 flows from output terminal WKM through resistor R2. The values of resistors R1 and R2 are equal, and the current 11 is 10μ.
If the value of the resistor R1 is determined to be about A, the terminal N
1 is changed from the power supply potential Vcc to the transistor Q6.1. Q7
It becomes a level-shifted potential.

In other words, from Vcc to 2
The potential is obtained by subtracting the multiplied value. Since the output terminal WKM of the word line booster circuit is precharged to Vcc and there is a level shift by the transistor Q14, the potential of the terminal N2 becomes a potential that is further lower than the potential of the terminal N1 by the threshold value of the memory cell transistor. . Therefore, transistor Q5 is turned on and Q15 is turned off, and the differential circuit 3
, is activated, the potential of its output terminal N3 remains at Vss.

As the word line booster circuit operates and the potential of the terminal WKM rises, the potential of the terminal N2 rises.

When the potential of the output terminal WKM becomes higher than the value obtained by adding the threshold value of the memory cell transistor to the power supply potential Vcc, the potential of the input terminal N2 of the differential circuit 31 becomes the reference potential terminal N.
1, and the output terminal N3 of the differential circuit 31
The potential of the terminal and terminal N4 becomes Vcc. As a result, transistor Q16 turns off, and the potential of output terminal WKM begins to be forcibly lowered.

If the potential of the output terminal WKM is slightly lower than the sum of the power supply potential Vcc and the threshold of the memory cell transistor,
The output terminal N3 of the differential circuit 31 becomes the ground voltage again, the transistor Q16 is turned off, and the discharge is stopped.

When the row address strobe signal RAS changes from low level to high level, the potential of the control signal RINT also decreases to Vcc.
The circuit then returns to its initial state.

According to this embodiment, when the power supply potential Vcc becomes high, the output potential of the word line booster circuit is forcibly lowered, and the solid line (b) is compared to the broken line (a) in FIG. ) can be obtained. Thereby, while ensuring the correct operation of the memory cell when the power supply potential is vecsln, it is possible to sufficiently ensure the reliability of the memory cell transistor even when the electric/line potential becomes Vccsax.

FIG. 5 shows the change in word line potential over time. The broken line (a) corresponds to (a) of the conventional example in FIG. 4, and the solid line (b)
also corresponds to the solid line (b) in the embodiment of FIG. As shown in the figure, also in this embodiment, the power supply potential Vc
When c rises, a high potential is temporarily applied to the word line, but this is only temporary, and the word line potential is lowered by the control described above. Therefore, the stress is sufficiently small compared to the conventional example.

The present invention is not limited to the above embodiments.

In the embodiment, a circuit for discharging the charge of the output terminal WKM of the word line booster circuit to the ground voltage Vss has been described, but the present invention is also applicable to the case of discharging the charge to the power supply potential Vcc. Further, in the embodiment, the control circuit is activated by manual input of the control signal, but the control circuit may be configured to be activated at all times when a power supply potential is applied.

In addition, in the embodiment, level shift transistors Q6゜Q7
．． Although QIO and Qll are P-channel transistors, they can of course be changed to N-channel transistors. The pond water invention can be implemented with various modifications without departing from the spirit thereof.

[Effects of the Invention] As explained above, according to the present invention, the minimum power supply potential v
It is possible to obtain a DRAM with improved reliability by reducing the stress applied to the gate oxide film of the memory cell transistor at the maximum power supply potential Vcca+ax compared to the conventional method while ensuring normal operation at cesln.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of a DRAM word line booster circuit and its control circuit section according to an embodiment of the present invention, FIG. 2 is a diagram showing a specific configuration example of the control circuit section, and FIG. 3 is a diagram showing the configuration of the control circuit section. 4 is a diagram showing the relationship between the word line potential and the power supply potential according to this embodiment. FIG. 5 is a diagram also showing the time change of the word line potential. FIG. 6 is a diagram showing the DRAM.
FIG. 2 is a diagram showing a memory cell configuration of FIG. 1... Word line booster circuit, 2... Level shift circuit, 3... Comparison circuit, 31... Current mirror type CM
OS differential circuit, 32, 33...CMOS gate, 4.
.../ik electric circuit, Q14...n channel transistor (level shift circuit), Q16... n channel transistor (discharge circuit).

Claims (4)

[Claims] (1) In a dynamic semiconductor memory device that has a memory cell structure of one transistor/one capacitor and has a word line booster circuit that obtains a boosted potential proportional to the power supply potential, the word line booster is provided at the output terminal of the word line booster circuit. A level shift circuit that obtains a second potential that is a predetermined value lower than the first potential obtained at the output terminal; and a comparison between the second potential obtained by the level shift circuit and the power supply potential, and the second potential is higher than the first potential obtained at the output terminal. A dynamic semiconductor comprising: a comparator circuit that outputs a control signal from time to time; and a discharge circuit that is provided at the output terminal of the word line booster circuit and is controlled by the control signal to lower the potential of the output terminal. Storage device. (2) The dynamic semiconductor according to claim 1, wherein the level shift circuit is configured by connecting the gate and drain of a MOS transistor having the same threshold as that of the memory cell transistor to the output terminal of the word line booster circuit. Storage device. (3) The comparison circuit includes a current mirror type CMOS differential circuit, and the differential circuit is controlled by an external control signal to convert the power supply potential and the second potential obtained by the level shift circuit into a reference signal and a second potential, respectively. 2. The dynamic semiconductor memory device according to claim 1, further comprising a gate circuit for supplying an input signal. (4) The dynamic semiconductor memory device according to claim 1, wherein the discharge circuit is a MOS transistor whose gate is controlled by the control signal.