JP2686130B2 - Semiconductor memory device - Google Patents

Description

The present invention relates to a semiconductor memory device that boosts a word line at the time of data writing, and suppresses excessive boosting of the word line even when a high power supply voltage is used, and a voltage applied to a gate of a memory cell transistor. For the purpose of avoiding the excessive rise of the memory cell transistor and preventing the deterioration of the memory cell transistor, the word line boosting means that is supplied with the voltage power supply and outputs the output voltage higher than the power supply voltage on the word line according to the row address strobe signal. Is connected between the output terminal of the word line boosting means and the reference voltage source, and when the output voltage is less than or equal to a threshold voltage value obtained by adding a predetermined voltage to the reference voltage from the reference voltage source, And a variable capacitance means having a second capacitance that is substantially larger than the first capacitance when the output voltage exceeds the threshold voltage. .

[Industrial applications]

The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device such as a dynamic random access memory which boosts a word line when writing data.

[Conventional technology]

 FIG. 7 shows a structure of a main part of a conventional semiconductor memory device.

The memory device is a word driver 10 and a word decoder 11
And a memory cell array 12 including a plurality of memory cells,
The word driver 10 includes a bit line precharge unit 13 and a sense amplifier 14, and the word driver 10 has a row address strobe (RA
Includes transistors T _W1 which is turned on by the falling edge of S) signal, the transistor T _W1 supplies the output signal of the V _th of V _CC -T _W1 to the word decoder 11.

Word decoder 11 comprises a transistor T _D2 is turned on in accordance with the supplied address data, the transistor T _D2 is supplied to the gate of the memory cell transistor T _M1 output signal W _DD than the word driver 10 through the word line W _Ln To do.

The memory cell transistor T _M1 is supplied with one bit of data to be stored from the data buses DB, DB via the bit line BL and stores it in the capacitor C _M1 in the form of electric charge. Supplying a voltage of a value obtained by adding the threshold voltage V _th of the transistor T _M1 to the supply voltage V _CC to connect a bit line BL that time the transistor T _M1 as on the capacitor C _M1 to the gate of the transistor T _M1 since it is necessary, the capacitors C _W potential of the source and drain after a lapse of time specified by the delay circuit I becomes V _CC is provided in the word driver 10, a word by a potential change of the source and the drain of the capacitor C _W The decoder output signal level is _boosted above V _CC .
In other words, the transistor T _M1 and capacitor C _M1
When the power supply voltage is written as data of one logic level in the memory cell composed of and, the word line is boosted beyond the power supply voltage V _CC .

[Problems to be solved by the invention]

By the way, as a result of the miniaturization of memory transistors accompanying the increase in capacity of memory devices, the withstand voltage of memory cell transistors has been decreasing year by year, and there is a demand for a technique that does not boost the word line more than necessary.

Conventionally, when writing a power supply voltage to a memory cell, the voltage of the word line is boosted by, for example, the method of capacitance division of the capacitor C _{W in} FIG. 7, so the voltage applied to the word line is proportional to the power supply voltage V _CC. , For example, 1.5 times the power supply voltage V _CC . On the other hand, the word line voltage actually required to write the power supply voltage to the memory cell is only the power supply voltage plus the threshold voltage of the cell transistor (V _CC + V _th ). Then, the higher the power supply voltage is, the more boosting is performed. As a result, an unnecessarily high voltage is applied to the memory cell transistor via the word line, causing a problem of accelerating its deterioration.

Therefore, the present invention can prevent an excessive boosting of the word line even when a high power supply voltage is used, avoid an excessive increase in the voltage applied to the gate of the memory cell transistor, and reduce the deterioration of the memory cell transistor. It is an object of the present invention to provide a semiconductor memory device that can be used.

[Means for solving the problem]

 FIG. 1 shows the principle of the device of the present invention.

In the figure, the word line boosting means 1 is supplied with power supply voltage V _CC, and outputs the power supply voltage V _CC or more output voltages W _DD on a word line according to a row address strobe signal RAS.

The variable capacitance means 2 is connected between the output terminal of the word line boosting means 1 and the reference voltage source V _ref .

[Action]

The variable capacitance means 2 has a first capacitance when the output voltage W _DD is less than or equal to a threshold voltage obtained by adding a predetermined voltage to the reference voltage from the reference voltage source V _ref , while the output voltage W _DD is It has a second capacitance that is substantially larger than the second capacitance when the threshold voltage is exceeded.

Therefore, it is possible to prevent the output voltage W _DD supplied to the word line from rising excessively, and to prevent the voltage applied to the gate of the memory cell transistor from rising excessively. As a result, deterioration of the memory cell transistor is prevented. It becomes possible to reduce.

〔Example〕

FIG. 2 shows a main part of an embodiment of a semiconductor memory device according to the present invention. In the figure, the word driver 21 has the same structure as the word driver 10 of FIG. 7, and is supplied with the RAS signal and outputs an output voltage W _DD higher than the power supply voltage to the line 22 in response to the falling edge thereof. . Further, a variable capacitance device 23, which is an essential part of the present invention, is connected between the line 22 and the power supply voltage V _CC to control the rise of the voltage W _DD as described later.

The word decoder 24 has the same configuration as the word decoder 11 in FIG. 7, and receives the row address data ADD to supply the power supply W _DD to the word lines WL _n and WL _{n + 1} . This voltage W _DD is further applied to the gates of memory transistors T _M1 and T _{M2 of} a memory cell array 25 similar to the memory cell array 12 of FIG. 7 via word decoders 24 ₁ and 24 ₂ .

The variable capacitance device 23 is composed of a MOS transistor T _r1 whose source and drain are commonly connected and supplied with the power supply voltage V _CC , while the substrate is held at the substrate potential V _BB .

Figure 3 (A) ~ (D) are diagrams for explaining the operation of the variable capacitance device 23 when the transistor T _r1 is an n-channel MOS transistor as an example.

The gate of the transistor T _r1 is connected to the line 22 and supplied with the voltage W _DD, while the n ⁺ -type source and drain are supplied with the power supply voltage V _CC . Further p ^- potential of the substrate in the form is held to the substrate potential V _BB. When the voltage W _DD is lower than the power supply voltage V _CC but higher than the substrate potential V _BB , a depletion layer is formed between the N-type source and drain and the P-type substrate, and carriers are formed in this portion. Deficiency occurs. As a result, as shown in the equivalent circuit diagram of FIG. 3 (B), a state occurs in which the capacitance of the depletion layer C ₃ is inserted in series with the capacitance C ₂ of the gate oxide film. However, in FIG. 3 (B), the capacitor C ₁ represents the capacitance formed between the gate and the source / drain. Thus, the transistor T _r1 acts as a parallel capacitor connected to the line 22, in the capacitance C depletion state of the F diagram (A), versus V _CC C = C ₁ pair V _BB C = 1 / It is given as (1 / C ₂ + 1 / C ₃ ).

By the way, the output voltage W _DD output by the word driver 21
Rises above the power supply voltage V _CC applied to the source and drain of the transistor T _r1 and the difference between the gate voltage and the source and drain voltage is the threshold V _th ′ of the transistor T _r1.
Above open the transistor T _r1 becomes inverted state, so an inversion layer is formed in a portion directly under the gate of the substrate. Figure 3 (C) shows the transistor T _r1 in such a state where the inversion layer is formed. In the region shown as the inversion layer in the figure, electrons emitted from the N-type regions of the source and drain exist due to the action of the strong electric field of the gate supplied with the voltage W _DD .

This electron short-circuits the capacitor due to the depletion layer, that is, the capacitor C ₃ shown in FIG. 3 (B), and the equivalent circuit corresponding to the state of FIG. 3 (C) is as shown in FIG. 3 (D). . As a result, the capacitance C of the transistor T _r1 is C
Change to = C ₁ + C ₂ . Clearly, greater than the capacitance of the transistor T _r1 in the state it is a third view of the capacity of the state (A).

FIG. 4 shows transistor T _r1 connected in parallel to line 22.
FIG. 6 is a schematic diagram showing the change in the capacitance of as a function of the voltage W _DD . In the figure, region I corresponds to the state of FIG. 3 (A), the capacitance C of the transistor T _r by the effect of the depletion layer capacitance C ₃ is small.

On the other hand, in the region II, the voltage W _DD exceeds the power supply voltage V _CC, and it can be seen that the capacitance C of the transistor T _r1 rapidly increases especially in the region where the voltage W _DD exceeds the value V _CC + V _th ′. State capacitance of such transistors T _r1 is increased corresponds to the state of FIG. 3 (C). In region III, the gate voltage W _DD is the substrate potential V _BB
The lower state corresponds to the storage state of the transistor T _r1 . This region is not relevant to the operation of the device according to the invention, since the memory device of FIG. 2 does not consider the case where the word line voltage on line 22 is negative.

Since the transistor T _r1 is connected in parallel to the output line 22 from the word driver 21, when the voltage W _{DD of the} line 22 rises and its capacitance rapidly increases corresponding to the voltage V _CC + V _th ′, the voltage W _{DD DD} rise is suppressed. FIG. 5 is a schematic diagram showing the change of the voltage W _DD of the line 22 depending on the power supply voltage V _CC with respect to the conventional word driver, the word line driving device in the present invention and the ideal word line voltage.

The ideal word line voltage is higher than the power supply voltage V _CC by the threshold voltage V _th of the memory cell transistor,
This is indicated by the broken line in FIG. A percentage conventional word driver to the power supply voltage V _CC contrast, for example because only the word line voltage increases at a rate of 1.5 times can not be outputted, the actual words of the power supply voltage V _CC is increased on the line 22 The difference between the line voltage and the ideal word line voltage is only increasing.

In contrast, the word line voltage for the transistor T _r1 when the word line voltage because it is inserted in parallel with the line 22 exceeds V _CC + V _th 'as a variable capacitance element power supply voltage V _CC is a word line driving device according to the present invention The slope of W _DD decreases sharply and approaches the ideal word line voltage. For example, comparing the word line voltage W _DD for a constant operating power supply voltage, the word line voltage A according to the device of the present invention is significantly lower than the voltage B formed by the conventional word driver, and approaches the ideal word line voltage C. I understand.

FIG. 6 shows such a decrease in the boosted level of the word line as a waveform diagram, and it can be seen that the voltage applied to the gate of the memory cell transistor is substantially decreased.

In the embodiment shown in FIG. 2, the reference voltage V _ref connected to the variable capacitance means 2 in FIG. 1 is the power supply voltage V _CC ,
The voltage V _ref may have other values.

Although the present invention has been described above with reference to the embodiments, the present invention can be variously modified according to the gist of the present invention, and these modifications are not excluded from the present invention.

〔The invention's effect〕

As described above, according to the present invention, since the variable capacitance means for increasing the capacitance when the word line voltage is boosted to a level higher than the corresponding level is provided, excessive boosting of the word line is suppressed even when a high power supply voltage is used. Therefore, it is possible to avoid an excessive increase in the voltage applied to the gate of the memory cell transistor, and it is possible to reduce deterioration of the memory cell transistor.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the principle of the present invention, FIG. 2 is a circuit diagram forming an essential part of an embodiment of the present invention, and FIGS. 3 (A) to 3 (D) are word line driving circuits shown in FIG. FIG. 4 is a cross-sectional view and an equivalent circuit diagram for explaining the operation of the variable capacitance device used in the device, FIG. 4 is a diagram for explaining the capacitance change of the variable capacitance device, and FIG. 5 is a change of the word line voltage by the variable capacitance device. FIG. 6 is a waveform diagram showing a change in word line voltage by a variable capacitance device in comparison with a conventional example, and FIG. 7 is a diagram showing a configuration of a conventional dynamic random access memory. 1 to 6, 1 is a word line boosting means, 2 is a variable capacitance means, 20 is a word line drive device, 21 is a word driver, 22 is a line, 23 is a variable capacitance device, and 24 ₁ and 24 ₂ are Word decoder, 25 is a memory cell, RAS is a row address strobe signal, V _CC is a power supply voltage, V _ref is a reference voltage, T _r1 is a MOS transistor, T _M1 , T _M2
Is a memory cell transistor, T _W1 and T _D1 are transistors,
C _W , C _M1 , C _M2 are capacitors, WL _n , WL _{n + 1} are word lines, D
B and DB are data buses, and BL and BL are bit lines.

Claims (1)

(57) [Claims] 1. A semiconductor memory device for boosting the voltage of a word line at the time of data writing, which is supplied with a voltage power supply (V _CC ) and has a voltage higher than the power supply voltage on the word line in response to a row address strobe signal (RAS). The word line boosting means (1) for outputting the output voltage (W _DD ) is connected between the output terminal of the word line boosting means and the reference voltage source (V _ref ), and the output voltage is supplied from the reference voltage source. When the output voltage exceeds the threshold voltage, it has a first capacitance when it is less than or equal to a threshold voltage value obtained by adding a predetermined voltage to the reference voltage. A device comprising a variable capacitance means (2) having an extremely large second capacitance.