JPH05136376A - Semiconductor nonvolatile storage device and its writing-in method - Google Patents

Abstract

PURPOSE:To achieve high integration by making a memory cell a single of MONOS-type nonvolatile storage element, and connecting all source lines in common. CONSTITUTION:A memory array comprises memory cells 11, 12, 13, and 14 consisting of MONOS-type nonvolatile storage elements connected to word lines 15 and 16, a source line, and bit lines 17 and 18. The writing into the memory cell 11 is performed by implanting electrons from a substrate to the gate insulating film of a MONOS-type nonvolatile storage element 10. The erasure is performed by discharging the electrons accumulated in the gate insulating film of the MONOS-type nonvolatile storage element to the substrate. Hereby, the MOS element for address, which was required in the past, becomes needless. Accordingly, high integration can be achieved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically rewritable semiconductor nonvolatile memory device and its writing method,
In particular, it relates to high integration of semiconductor nonvolatile memory devices.

[0002]

2. Description of the Related Art Conventionally, as an electrically rewritable semiconductor nonvolatile memory element, MNOS (Metal-Ni) has been used.
tride-Oxide-Semiconductor
r) type non-volatile memory element, for example, Japanese Patent Laid-Open No. 2-1
MONOS (Me
tal-Oxide-Nitride-Oxide-S
A known non-volatile memory element is an "emulator" type.

This MONOS type non-volatile memory element is
A barrier sufficient to prevent carrier injection from the gate electrode side by thermally oxidizing the surface of the silicon nitride film that is the second layer gate insulating film of the MNOS type nonvolatile memory element to form a silicon oxide film. It has a third-layer gate insulating film having a height.

A semiconductor non-volatile memory device in the prior art includes a MONOS type or MNOS type non-volatile memory element and a MOS (Metal-Oxid) for address selection.
It has a memory array in which a plurality of memory cells each including an e-Semiconductor element are arranged in a matrix.

A circuit configuration of a memory array of a conventional semiconductor nonvolatile memory device will be described with reference to the circuit diagram of FIG.

As shown in FIG. 3, the memory array has a nonvolatile memory element 31 of MNOS type or MONOS type connected to write word lines 33 and 34, and an address connected to selected word lines 35 and 36. MOS element 3
2 and memory cells 30 and source lines 39, 40
And bit lines 37 and 38.

FIG. 4 is a plan view of the memory array in the circuit configuration of the semiconductor nonvolatile memory device shown in FIG.

In FIG. 4, the memory array has write word lines 43 and 44, selected word lines 45 and 46, and a source line 4 connected to a source 52 through a contact hole 42.
9 and 50, bit lines 47 and 48 connected to the drain 51 through the contact hole 41, and an element isolation region 53.

[0009]

In FIG. 4, the memory cells adjacent in the direction of the write word lines 43 and 44 have their sources 52 individually wired by source lines 49 and 50, and their drains 51 are also individually bit lines. 47, 48
Is wired in.

Therefore, the conventional memory array in which the memory cells are arranged in a matrix form has bit lines 47 and 48.
And the source lines 49 and 50 need to be connected to the element isolation region 53. Therefore, the occupied area of the element isolation region 53 becomes large, which is disadvantageous for high integration of the semiconductor nonvolatile memory device.

Further, since the memory cell requires two word lines, a write word line and a selected word line, the memory cell becomes large, which is disadvantageous for high integration of the semiconductor nonvolatile memory device.

An object of the present invention is to eliminate the above-mentioned problems and provide a semiconductor nonvolatile memory device having a high degree of integration and a writing method thereof.

[0013]

In order to achieve the above object, the present invention employs the following semiconductor nonvolatile memory device and its writing method.

The semiconductor non-volatile memory device of the present invention comprises a first conductivity type semiconductor substrate, a first impurity diffusion layer of a conductivity type opposite to that of the semiconductor substrate, a MONOS type non-volatile memory element, and a semiconductor. A plurality of memory cells each having a substrate and a second impurity diffusion layer of opposite conductivity type sequentially connected in series are arranged in a matrix, and the first impurity diffusion layer is used as a drain and connected to a bit line. , The second impurity diffusion layer is used as a source and is connected to a source line, and this source line is connected to all memory cells.

According to the method for writing to a semiconductor nonvolatile memory device of the present invention, a semiconductor substrate of one conductivity type is provided with a first impurity diffusion layer of a conductivity type opposite to that of the semiconductor substrate, and a MONO.
A plurality of memory cells, each of which is formed by sequentially connecting an S-type non-volatile memory element and a semiconductor substrate and a second impurity diffusion layer of an opposite conductivity type in series, are arranged in a matrix. The diffusion layer is connected to the bit line as the drain, the second impurity diffusion layer is connected to the source line as the source, and this source line is connected to all the memory cells. The bit line potential is lower than the source line potential. Do it.

[0016]

In the semiconductor nonvolatile memory device of the present invention, the memory cell is composed of only one MONOS type nonvolatile memory element, and the source lines are all connected in common to achieve high integration. There is.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of the circuit configuration of a memory array of a semiconductor nonvolatile memory device according to the present invention.
FIG. 2 is a plan view showing an embodiment of the memory array of the semiconductor nonvolatile memory device according to the present invention. In the following description, a 2 × 2 minimum memory array structure is used for explanation, but it is apparent from the following description that the present invention can be extended to a large-scale memory array structure.

First, the structure of the semiconductor nonvolatile memory device of the present invention will be described with reference to FIG.

As shown in FIG. 1, the memory array includes memory cells 11, 12, 13, and 14 each including a MONOS type nonvolatile memory element 10 connected to word lines 15 and 16.
The source line 19 and the bit lines 17 and 18 are included. This source line 19 is used for all memory cells 11, 12, 1
3 and 14 are connected.

Next, a writing method of the semiconductor nonvolatile memory device of the present invention will be described with reference to FIG.

Writing to the memory cell 11 is performed by the word line 1
5 and the source line 19 are applied with a program voltage (hereinafter referred to as Vpp), and the bit line 17 is applied with a voltage of 0 V or lower than Vpp, and the MONOS type nonvolatile memory element 1 is applied.
This is performed by injecting electrons from the substrate into the 0 gate insulating film.

In the memory cell 12 connected to the same word line 15 as the memory cell 11, by applying Vpp to the bit line 18, the MONOS type nonvolatile memory element 10 is formed.
The gate, drain and source of V are all at the same potential
Since it becomes pp, writing is prohibited.

Further, in this state, the word line 16 is set to 0V,
That is, when the potential is the same as that of the substrate, electrons are not injected from the substrate into the gate insulating film of the MONOS type nonvolatile memory element 10, so that writing is prohibited in the memory cells 13 and 14.

By the above-described writing method of the present invention, it is possible to selectively write only the memory cell 11.

In FIG. 1, the erase method is word line 1
5 and 16 are set to 0 V, the substrate is set to Vpp, and the electrons accumulated in the gate insulating film of the MONOS type nonvolatile memory element 10 are discharged to the substrate.

The reading of the memory cell 11 is performed by the word line 1
5 is set to 0 V, the word line 16 is set to a potential at which the nonvolatile memory element does not become conductive in any state of writing and erasing, and writing and erasing does not occur, a read voltage is applied to the source line 19, and a current is applied to the bit line 17. It is performed by determining whether or not it flows.

As described above, according to the present invention, the MOS element for address, which has been conventionally required, becomes unnecessary.

According to the writing method of the present invention, when a MONOS type non-volatile storage element is used as the non-volatile storage element, the semiconductor non-volatile storage device is highly integrated. The reason for this is described below.

Since the MONOS type non-volatile memory element has a third layer gate insulating film having a barrier height sufficient to prevent carrier injection from the gate electrode side, the gate insulating film is thinned to 10 nm or less. Is possible,
Writing is possible with a program voltage of 10 V or less.

When the writing method of the present invention is used, the potential difference between the drain of the nonvolatile memory element and the substrate has the same value as the program voltage. Therefore, in the nonvolatile memory element having a high program voltage, the drain needs to have a high breakdown voltage structure. is there. M
Since the ONOS type non-volatile memory element has a low program voltage, the drain does not need to have a high breakdown voltage structure, which is advantageous for high integration.

FIG. 2 is an example of a plan view of a memory array of a semiconductor nonvolatile memory device according to the present invention.

As shown in FIG. 2, the memory array includes word lines 25 and 26, a source line 29 connected to a source 24 in which the sources of all the memory cells are connected by a second impurity diffusion layer in the contact hole 21. Bit lines 27 and 28 connected to the drain 23 that is the first impurity diffusion layer through the contact hole 20 and the element isolation region 22.

The word lines 25 and 26 serve as the gate electrodes of the MONOS type nonvolatile memory element, and a three-layer gate insulating film composed of a silicon oxide film-a silicon nitride film-a silicon oxide film is formed under the gate electrodes. Prepare

In the semiconductor nonvolatile memory device of the present invention, the number of source lines is reduced as compared with the conventional one, and the bit line 2
It is possible to wire 7 and 28 to regions other than the element isolation region 22.
Therefore, the area occupied by the element isolation region 22 is reduced and the number of wirings of the word lines is reduced, so that the area of the memory array can be reduced. Therefore, a semiconductor nonvolatile memory device having a high degree of integration can be obtained.

[0035]

As is apparent from the above description, in the present invention, the wiring region of the source line, the wiring region of the word line, and the element isolation region in the semiconductor nonvolatile memory device are reduced as compared with the prior art. Is possible. Furthermore, according to the writing method of the present invention, it is possible to selectively write the memory cells in the semiconductor nonvolatile memory device in which the sources of all the memory cells are connected and the memory cells do not have MOS elements for address selection. That is, the semiconductor nonvolatile memory device having a high degree of integration and the writing method thereof can be realized.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a memory array of a semiconductor nonvolatile memory device according to an embodiment of the present invention.

FIG. 2 is a plan view showing a memory array of a semiconductor nonvolatile memory device according to an embodiment of the present invention.

FIG. 3 is a circuit diagram showing a memory array of a semiconductor nonvolatile memory device in a conventional example.

FIG. 4 is a plan view showing a memory array of a semiconductor nonvolatile memory device in a conventional example.

[Explanation of symbols]

 10 MONOS type non-volatile memory element 11 memory cell 15 word line 17 bit line 19 source line 23 drain 24 source

Claims (2)

[Claims] 1. A first impurity diffusion layer having a conductivity type opposite to that of the semiconductor substrate in a surface region of the conductivity substrate, and a MONO.
A plurality of memory cells each of which is formed by sequentially connecting the S-type nonvolatile memory element and the semiconductor substrate and a second impurity diffusion layer of an opposite conductivity type in series are arranged in a matrix,
The impurity diffusion layer is connected to a bit line as a drain, the second impurity diffusion layer is connected to a source line as a source, and the source line is connected to all the memory cells. Sex memory device. 2. A surface region of a semiconductor substrate of one conductivity type, a first impurity diffusion layer of a conductivity type opposite to that of the semiconductor substrate, and a MONO.
A plurality of memory cells each of which is formed by sequentially connecting the S-type nonvolatile memory element and the semiconductor substrate and a second impurity diffusion layer of an opposite conductivity type in series are arranged in a matrix,
In the semiconductor nonvolatile memory device, the impurity diffusion layer is connected to a bit line as a drain, the second impurity diffusion layer is connected to a source line as a source, and the source line is connected to all the memory cells, A writing method for a semiconductor non-volatile memory device, characterized in that writing is performed with a bit line potential lower than a source line potential.