JPS6134481A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS6134481A
JPS6134481A JP15610384A JP15610384A JPS6134481A JP S6134481 A JPS6134481 A JP S6134481A JP 15610384 A JP15610384 A JP 15610384A JP 15610384 A JP15610384 A JP 15610384A JP S6134481 A JPS6134481 A JP S6134481A
Authority
JP
Japan
Prior art keywords
circuit
signal
input
value
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15610384A
Other languages
Japanese (ja)
Inventor
Minoru Toyoda
豊田 實
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP15610384A priority Critical patent/JPS6134481A/en
Publication of JPS6134481A publication Critical patent/JPS6134481A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To enable the implementation of an effective continuity test without use of any costly equipment, by making an internal integrated circuit operate by itself diregarding the state of an input signal from outside only while a oscillation circuit operation signal is applied to a three-value input circuit. CONSTITUTION:In the continuity test, as a DC voltage for operation in applied to an input terminal of a three-value circuit 4, an operation permit signal is provided to a spontaneous oscillation circuit 5 and an operation control circuit 6 from the circuit 4. In this case, the operation voltage value of the three-value input circuit is normally set for than almost doubling the service voltage value. The circuit 6 generates an input switching signal to the input circuit 1 which is controlled only to a signal generated by the circuit 6. Thereafter, the IC stays in operation continually by an operation control signal of a main function section 2 and an output circuit 3 as generated from the circuit 6.

Description

【発明の詳細な説明】 (技術分野) 本発明は半導体集積回路装置にかかり、とくに通電試験
に好適な装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a semiconductor integrated circuit device, and particularly relates to a device suitable for an electrical conduction test.

(従来技術) 半導体集積回路装置′(以下I、C,と記す)は使用時
初期の故障を防止する為に9通常使用に先立って高温雰
囲気下における通電試験t−笑施している。
(Prior Art) Semiconductor integrated circuit devices' (hereinafter referred to as I and C) are subjected to a current conduction test in a high temperature atmosphere prior to normal use in order to prevent failures during initial use.

通電試験は電圧印加の形態の違いによυ以下の2種類の
方法に大別できる。
Current testing can be roughly divided into the following two methods depending on the form of voltage application.

方法1゜ 被試験1.C,の電源端子に所定の電圧を印加し。Method 1゜ Tested 1. Apply a predetermined voltage to the power supply terminal of C.

入出力端子には抵抗等を通じてDC電圧を印加する方法
。以下スタティックバイアス法という。
A method in which DC voltage is applied to the input/output terminals through a resistor, etc. This is hereinafter referred to as the static bias method.

方法2゜ 被試験I、C0の電源端子に所定の電圧を印加し。Method 2゜ Apply a predetermined voltage to the power supply terminals of I and C0 under test.

入力端子には該1.C,t−動作せしめる制御信号を印
加する方法。以下ダイナミックバイアス法という。
The input terminal has 1. C, t - Method of applying control signals for operation. This is hereinafter referred to as the dynamic bias method.

スタティックバイアス法は試験装置及び治具1類が安価
でメタ。試験コストが安い長所がある反面、被試験1.
C,がスイッチング動作を行なわない為1通電試験の効
果が十分ではないという短所がめる。−万、ダイナミッ
クバイアス法は適切な制御信号金印加すれば、被試験1
.C,の全ての内部回路素子を動作せしめ得る為9通電
試験としては非常に有効であるが1反面試験装置及び、
治、工具類の複雑化・高価格化をまねき、また試験装置
は汎用性に乏しくなる為、結果として1.C,の通電試
験コストが高くなるという欠点がめる。
The static bias method is meta because the test equipment and jig type 1 are cheap. Although it has the advantage of low test cost, the test subject 1.
The disadvantage is that the effect of a single energization test is not sufficient because C does not perform a switching operation. - 10,000, the dynamic bias method can be used to
.. It is very effective as a conduction test because it can operate all internal circuit elements of C, but on the other hand, it is a testing device and
As a result, 1. The drawback is that the cost of conducting the current test of C. is high.

(発明の目的) 本発明の目的に通電試験コストの上昇を最小限におさえ
つつ1通電試験の効果も十分期待できるI、C,全提供
することにめる〇 (実施例) 次に本発明の一笑施例會図面會用いて説明テる。
(Objective of the Invention) The purpose of the present invention is to provide I, C, and the like that can be expected to be sufficiently effective in one energization test while minimizing the increase in the cost of the energization test (Example) Next, the present invention I will explain it using an example meeting drawing.

第1−は従来の1.C,の機能ブロック図である。1st is the conventional 1. It is a functional block diagram of C.

第1図で示される従来のI、C,に前記ダイナミックバ
イアス法による通電試験を実施する場合は、入力端子に
所望の信号を印加することにより、入力回路1.主機能
部2.出力回路3が動作する。しかるにダイナミックバ
イアス法による通電試験全同時に大量の1.C,に対し
て実施する場合、印加された制御信号に同期して被試験
1.C,がスイッチング動作を行う友め、スイッチング
ノイズや瞬時電流の著るしい増減に起因する誤動作を防
止する為の対策が重要となる。また制御信号は通常被試
験I、C,の入力端子数と同じ数の種類を必要とし、従
って通電試験装置は複雑・大型化となり、試験コストが
上昇してしまう。
When conducting a current conduction test using the dynamic bias method described above for the conventional I, C shown in FIG. 1, the input circuit 1. Main function section 2. Output circuit 3 operates. However, a large number of 1. When testing 1.C, the test target 1.C. Since C performs a switching operation, it is important to take measures to prevent malfunctions caused by switching noise or significant changes in instantaneous current. Further, the number of control signals usually requires the same number of types as the number of input terminals of I, C, and the like to be tested, and therefore the energization test apparatus becomes complicated and large, and the test cost increases.

第2図は本発明の一実施例にかかるI、C,の機能ブロ
ック図である。同図において、入力回路1゜主機能部2
.出力回路3は従来の1.C,と同様の機能であるが、
三値入力回路4および三値入力回路4の出力信号により
制御される自走発振回路5並びに該I、 C,の動作信
号?発生する動作制御回路6を同一チップ上に新たに設
けている。通電試験時には三値入力回路4に接続されて
いる入力端子に。
FIG. 2 is a functional block diagram of I and C according to an embodiment of the present invention. In the same figure, input circuit 1゜main function section 2
.. The output circuit 3 is the conventional 1. It has the same function as C, but
The three-value input circuit 4, the free-running oscillation circuit 5 controlled by the output signal of the three-value input circuit 4, and the operation signals of the I, C, and the like? The operation control circuit 6 that generates the data is newly provided on the same chip. To the input terminal connected to the three-value input circuit 4 during the energization test.

三値入力回路動作用直流電圧を印加すると、三値入力回
路4からは自走発振回路5並びに動作制御回路1に対し
て動作許可信号が印加される。この場合の三値入力回路
動作電圧値は通常使用電圧値     ”の約2倍の値
に設定することとする。これによシ動作制御回路6は入
力回路1に対して入力切り換え信号を発生し、入力回路
lは動作制御回路6の発生する信号のみに制御される。
When a DC voltage for operating the three-value input circuit is applied, an operation permission signal is applied from the three-value input circuit 4 to the free-running oscillation circuit 5 and the operation control circuit 1. In this case, the three-value input circuit operating voltage value is set to a value approximately twice the normally used voltage value. , the input circuit 1 is controlled only by the signal generated by the operation control circuit 6.

以後は動作制御回路6によ多発生される主機能部2及び
出力回路3の動作制御信号により、骸I、C,は動作状
態を継続する。
Thereafter, the skeletons I, C continue to operate according to the operation control signals of the main function section 2 and the output circuit 3 generated by the operation control circuit 6.

従って本実施例にかかるI、C’、の通電試験において
は接地線の他には電源電圧印力g線及び三値入力回路動
作線の281[類の電気線のみを被試験I、C,に接続
するのみであり、結果として通電試験装置及び治工具類
は安価であるにもかかわらず、効果の高い通電試験を行
うことが可能となる。f7’c本実施例の三値入力画w
rは冥使用時に印加される電圧では動作し得ない為1通
常の動作は従来の1.C,と何ら変わるところはない。
Therefore, in the energization test of I, C' according to this embodiment, in addition to the ground wire, only the power supply voltage input g line and the three-value input circuit operation line 281[class] were tested. As a result, it is possible to perform highly effective current testing even though the current testing equipment and jigs are inexpensive. f7'c Three-value input image of this example w
Since r cannot operate with the voltage applied during normal use, the normal operation is the conventional 1. There is no difference from C.

(効果の説明) 以上述べたごとく9本発明によれば高価な設備を使用す
ることなく、効果的な通電試験を実施可能な半導体集積
回路装置を提供することが可能である。
(Description of Effects) As described above, according to the present invention, it is possible to provide a semiconductor integrated circuit device that can carry out effective energization tests without using expensive equipment.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の半導体集積回路装置の機能ブロック図、
第2図に本発明の一実施例にかかる半導体集積回路装置
の機能ブロック図である。 1・・・入力回路、2・・・主機能部、3・・・出力回
路、4・・・三値入力回路、5・・・自走発振回路、6
・・・動作制御回路
Figure 1 is a functional block diagram of a conventional semiconductor integrated circuit device.
FIG. 2 is a functional block diagram of a semiconductor integrated circuit device according to an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Input circuit, 2... Main function part, 3... Output circuit, 4... Three-value input circuit, 5... Free-running oscillation circuit, 6
...Operation control circuit

Claims (1)

【特許請求の範囲】[Claims] 半導体集積回路装置において、三値入力回路および三値
入力回路の出力信号により制御される発振回路並びに内
部集積回路の動作信号を発生する動作制御回路を有し、
前記三値入力回路に発振回路動作信号が与えられている
期間のみ前記内部集積回路は外部からの入力信号の状態
とは無関係に自己動作し、前記三値入力回路に発振回路
動作用信号が与えられていない場合は、前記外部からの
入力信号の制御に従って動作を行うようにしたことを特
徴とする半導体集積回路装置。
The semiconductor integrated circuit device includes a three-value input circuit, an oscillation circuit controlled by the output signal of the three-value input circuit, and an operation control circuit that generates an operation signal for the internal integrated circuit,
Only during the period when the oscillation circuit operation signal is applied to the three-value input circuit, the internal integrated circuit operates by itself regardless of the state of the external input signal, and the oscillation circuit operation signal is applied to the three-value input circuit. 2. A semiconductor integrated circuit device, wherein the semiconductor integrated circuit device operates according to control of the input signal from the outside when the input signal is not input.
JP15610384A 1984-07-26 1984-07-26 Semiconductor integrated circuit device Pending JPS6134481A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15610384A JPS6134481A (en) 1984-07-26 1984-07-26 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15610384A JPS6134481A (en) 1984-07-26 1984-07-26 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS6134481A true JPS6134481A (en) 1986-02-18

Family

ID=15620371

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15610384A Pending JPS6134481A (en) 1984-07-26 1984-07-26 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS6134481A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8454767B2 (en) 2011-03-01 2013-06-04 Ntn Corporation Heat treatment method, outer joint member, and tripod type constant velocity universal joint

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8454767B2 (en) 2011-03-01 2013-06-04 Ntn Corporation Heat treatment method, outer joint member, and tripod type constant velocity universal joint

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