JP3239864B2 - Test board for power / GND terminal continuity test - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power / GND terminal continuity test board.

[0002]

2. Description of the Related Art In order to perform an LSI test, it is necessary to first confirm the electrical continuity between a device under test (hereinafter referred to as a DUT) and a tester.

The above-described continuity test needs to be performed on all terminals of the DUT. However, since the power supply pin and the GND pin of the LSI tester do not have a continuity test function, a test as shown in FIG. Use a board.

As shown in FIG. 5, in a normal test board, a circuit between the dotted line ab and the dotted line cd is a circuit in the test board. Inside the test board, signal pins D1, D3, D5 and D6 of the DUT are provided. , D7, D9 are connected to the signal pins T1, T2, T3, T4, T5, T6 of the LSI tester on a one-to-one basis, and the power terminals D2, D10 and the GND terminals D4, D8 are respectively connected in the test board. Commonly connected, commonly connected power terminals D2, D10 and commonly connected GN
The D terminals D4 and D8 are connected to the power pin V1 of one LSI tester and the GND pin G1 of the LSI tester, respectively.

[0005]

However, as shown in FIG. 5, inside the test board, the signal pins D1, D3, D5, D6, D7, D9 of the DUT are connected to the signal pins T1, T2, T3 of the LSI tester. , T4, T5, and T6 are connected one-to-one. Therefore, even when a part of the power supply terminal or the GND terminal on the DUT side is not electrically connected to the outside due to poor contact or the like during the test, Power supply terminals D2 and D10 connected in common
If one of the power supply terminals D2 or D10 and the GND terminal D4 or D8 is conductive, the other one of the power supply terminals D2 or D10 and GND is connected.
Even if the D terminal D4 or D8 is not conductive to the outside due to poor contact or the like, it is erroneously determined as good conduction,
There is a problem that it is impossible to conduct a continuity test of the power supply terminal and the GND terminal for each pin.

SUMMARY OF THE INVENTION An object of the present invention is to provide a power / GND terminal continuity test board which enables a normal test of an LSI and a continuity test of a power terminal and a GND terminal on the same test board.

[0007]

In order to achieve the above object, a test board for a power supply / GND terminal continuity test according to the present invention comprises a power supply / GND terminal continuity test for electrically connecting a device under test and an LSI tester. Test board, a switch is provided on the test board, and by switching the switch, a signal pin of the LSI tester is measured.
Connect the test board power supply and GND
Connect the lane to the power supply terminal and GND terminal of the device under test.
The switching between the connected state and the state in which the signal pin of the LSI tester is connected to the power terminal and the GND terminal of the device under test instead of the signal terminal of the device under test.

The switch performs switching by operating a relay based on a relay control signal.

[0009] The relay operates to switch the switches at once.

[0010] Further, the relay operates to switch the switches individually and independently.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a configuration diagram showing a test board for power supply / GND terminal continuity test according to Embodiment 1 of the present invention.

As shown in FIG. 1, the test board is an LSI
Tester signal pins T1, T2, T3, T4, T5, T6, LS
Power pin V1 of I tester, GND pin G1 of LSI tester
And DUT signal pins D1, D3, D5, D6, D7, D9,
This is a device for electrically connecting power terminals D2 and D10 and GND terminals D4 and D8.

The test board shown in FIG. 1 is set on a test head of an LSI tester and contacts pins of the LSI tester. An IC socket is mounted on the test board, and an LSI tester and a DUT are electrically connected by setting an LSI in the IC socket.

A signal pin of the LSI tester has a role of inputting a signal generated by the LSI tester to the DUT, taking in an output signal from the DUT, and connecting to a measurement unit for performing a DC test.

Each signal pin of the LSI tester is connected to a signal pin of the DUT one by one via a test board.

The GND pin G1 of the LSI tester is
D commonly connected to the GND plane g of the test board
The power supply pins V1 of the LSI tester are connected to the GND terminals D4 and D8 of the UT, and the power supply pins D2 and D10 of the DUT commonly connected to the power supply plane v of the test board.

A power / GND terminal continuity test test board according to the first embodiment of the present invention, as shown in FIG.
By switching the signal pins T1, T2, T5, T6 of the tester by switches S1, S2, S3, S4, S5, S6, S7, S8 on the test board, the signal terminals D1, D3,
In addition to D7 and D9, the power supply terminals D2 and D10 and the GND terminals D4 and D8 can be connected. The signal pins T1, T2, T5, and T6 of the LSI tester are separately assigned to the power terminals D2, D10 and the GND terminals D4, D8 of the DUT, so that the power terminals D2, D10, and GN of the DUT.
The continuity test of the D terminals D4 and D8 can be performed for each pin.

Next, a specific example will be described. As shown in FIG. 2, in the power / GND terminal continuity test board according to the first embodiment of the present invention, a dotted line ab and a dotted line cd are used.
The space between the symbols indicates a circuit in the test board.

As shown in FIG. 2, the power / GND terminal continuity test test board according to the first embodiment of the present invention includes a power plane v, a GND plane g, GND terminals D4 and D8 of the DUT, and power terminals D2 and D10. And between the signal pins T1, T2, T5, and T6 of the LSI tester and the signal pins D1, D3, D7, and D9 of the DUT, relays R1, R2, R3, and R4 are provided. Provided, each relay R1, R2, R
Two switches S1, S2, S3, S4, S, 5, S6, S which operate in conjunction with the relay control signal in R3 and R4, respectively.
7 and S8 are provided.

The power supply plane v of the test board, the signal pin T1 of the LSI tester, and the power supply terminal D2 and the signal pin D1 of the DUT are connected via a relay R1.

Further, the GND plane g,
The signal pin T2 of the LSI tester and the GND terminal D of the DUT
4. The connection to the signal pin D3 is made via a relay R2.

Further, the GND plane g,
The signal pin T5 of the LSI tester and the GND terminal D of the DUT
8, the signal pin D7 is connected via a relay R3.

The power planes v and L of the test board
The signal pin T6 of the SI tester and the power terminal D10 of the DUT,
The connection to the signal pin D9 is established via a relay R4.

The signal pins T3 and T4 of the LSI tester
And the DUT signal pins D5 and D6 are directly connected via a test board.

The signal pins T1, T2, T5,
To enable T6 to be connected not only to the signal terminals D1, D3, D7 and D9 of the DUT but also to the power terminals D2 and D10 and the GND terminals D4 and D8, the relay R1 has switches S1 and S2.
The relay R2 includes a pair of switches S3 and S4, the relay R3 includes a pair of switches S5 and S6, and the relay R4 includes a pair of switches S7 and S8.

Each of the relays R1, R2, R3, R4 receives the relay control signal from the relay control signal plane t and switches the switches S1, S2, S3, S4, S5, S6, S7, S8.

The switch S1 in the initial state shown in FIG.
The signal pin T1 of the SI tester is connected between the signal pin D1 of the DUT and the switch S2 is connected between the power plane v of the test board and the power terminal D2 of the DUT.
When a relay control signal is input to the relay control signal plane t, the switch is switched by the relay R1, and as shown in FIG. 2, the switch S1 is switched to the contact of the switch S2, and the signal pin T1 of the LSI tester is connected to the DUT. The signal pin D1 is opened, and the signal pin T1 of the LSI tester and the power supply terminal D2 of the DUT are connected by the switch S1. At the same time, the contact of the switch S2 is opened.

The switch S3 in the initial state shown in FIG.
Are the signal pin T2 of the LSI tester and the signal pin D3 of the DUT.
Switch S4 is connected to the GN of the test board.
Although the connection between the D plane g and the GND terminal D4 of the DUT is performed, when a relay control signal is input to the relay control signal plane t, the switch is switched by the relay R2, and as shown in FIG. S3 is switched to the contact of the switch S4, and the signal pin T2 of the LSI tester is connected to the DU.
The signal pin D3 of the T is opened, and the signal pin T2 of the LSI tester and the GND terminal D4 of the DUT are connected by the switch S3. At the same time, the contact of the switch S4 is opened.

The switch S5 in the initial state shown in FIG.
Are the signal pin T5 of the LSI tester and the signal pin D7 of the DUT.
Switch S6 is connected to the test board GN
Although the D plane g is connected to the GND terminal D8 of the DUT, when a relay control signal is input to the relay control signal plane t, the switch is switched by the relay R3, and the switch is switched as shown in FIG. S5 switches to the contact of the switch S6, and the signal pin T5 and DU of the LSI tester are connected.
The signal pin D7 of T is opened, and the signal pin T5 of the LSI tester is connected to the GND terminal D8 of the DUT by the switch S5. At the same time, the contact of the switch S6 is opened.

The switch S7 in the initial state shown in FIG.
Are the signal pin T6 of the LSI tester and the signal pin D9 of the DUT.
The switch S8 connects between the power plane v of the test board and the power terminal D10 of the DUT. When a relay control signal is input to the relay control signal plane t, the switch R8 is switched by the relay R4. The switch S7 is switched to the contact of the switch S8 as shown in FIG. 2 to open the signal pin T6 of the LSI tester and the signal pin D9 of the DUT, and the signal pin T6 of the LSI tester is opened. And a power supply terminal D10 of the DUT are connected by a switch S7. At the same time, the contact of the switch S8 is opened.

The relays R1, R2, R3 and R4 are commonly connected to a relay control plane t of the test board, and the relay control plane t is connected to a relay control signal pin T11 of the LSI tester. The power plane v is connected to the power pin V1 of the LSI tester, and the GND plane g is connected to the GND pin G1 of the LSI tester.

Next, the operation of the test board for power supply / GND terminal continuity test according to the first embodiment of the present invention shown in FIG. 2 will be described.

In the initial state shown in FIG. 1, the signal pins D1, D3, D7, D9 of the DUT are connected to the switches S1, S3, S5, S7.
Are connected to signal pins T1, T2, T5, and T6 of the LSI tester, respectively.

The power terminals D2 and D10 of the DUT are connected to a power plane v via switches S2 and S8, respectively, and power is supplied from a power pin V1 of the LSI tester.

The GND terminals D4 and D8 of the DUT are connected to the GND plane g via the switches S4 and S6, respectively, and the GND potential is supplied from the GND terminal G1 of the LSI tester.

In the above state, all the tests including the continuity test of the signal terminals of the DUT are performed.

Next, when a relay control signal is input from the relay control signal pin T11 of the LSI tester to the relay control plane t, as shown in FIG. 2, the switches S2, S4, S4
6, S8 is switched to the open state.

In the state shown in FIG. 2, the power supply terminal D of the DUT
2, D10 are connected to signal pins T1, T6 of the LSI tester via switches S1, S7, respectively. DUT
GND terminals D4 and D8 are connected to L level through switches S3 and S5.
It is connected to signal pins T2 and T5 of the SI tester.

If the DUT is normal, the signal pins T1 and T1 of the LSI tester connected to the power terminals D2 and D10 of the DUT.
No. 6 is short-circuited via the internal circuit of the DUT. Utilizing this, a plurality of power terminals D2 and D1 of the DUT are used.
A continuity test is performed for each 0 terminal.

For the plurality of GND terminals D4 and D8 of the DUT, a continuity test is performed for each terminal similarly to the power terminals D2 and D10 of the DUT.

(Embodiment 2) FIG. 3 is a block diagram showing a power / GND terminal continuity test test board according to Embodiment 2 of the present invention.

Relay R used for power / GND terminal continuity test test board according to Embodiment 2 of the present invention shown in FIG.
1, R2, R3 and R4 are the relays R used in the first embodiment.
This is different from the operation of 1, R2, R3 and R4.

The switch S1 in the initial state shown in FIG.
The signal pin T1 of the SI tester is connected to the signal pin D1 of the DUT, and the switch S2 is connected between the power plane v of the test board and the power terminal D2 of the DUT.

As shown in FIG. 4, the switch S1 of the relay R1
Operate according to the relay control signal input from the signal pin T11 of the LSI tester. Signal pin T11 of LSI tester
While the relay control signal is being input, the operation is performed to disconnect the signal terminal D1 of the DUT and the signal pin T1 of the LSI tester.

The switch S2 is a signal pin of the LSI tester.
It operates by the relay control signal input from T1 ,
It operates only when a voltage higher than the maximum applied voltage in the test is input, and opens between the power supply plane v of the test board and the power supply terminal D2 of the DUT.

The voltage higher than the maximum applied voltage in the test is DU
Before inputting a high voltage for operating the switch S2 to prevent the voltage from being applied to T, the switch S
1 is operated to disconnect the signal terminal D1 of the DUT from the signal pin T1 of the LSI tester. The switch S2 keeps its operation until the next voltage is applied even when the applied voltage (excitation current) becomes zero.

The switch S3 in the initial state shown in FIG.
Are the signal pin T2 of the LSI tester and the signal pin D3 of the DUT.
Switch S4 is connected to the GN of the test board.
The connection is made between the D plane g and the GND terminal D4 of the DUT.

As shown in FIG. 4, the switch S3 of the relay R2
Operate according to the relay control signal input from the signal pin T11 of the LSI tester. Signal pin T11 of LSI tester
While the relay control signal is being input, the operation is performed such that the connection between the signal terminal D3 of the DUT and the signal pin T2 of the LSI tester is disconnected.

The switch S4 is a signal pin of the LSI tester.
It operates by the relay control signal input from T2 ,
It operates only when a voltage higher than the maximum applied voltage in the test is input, and the GND plane g of the test board and the DUT
And the GND terminal D4.

The voltage higher than the maximum applied voltage in the test is DU
Before inputting a high voltage for operating the switch S4 to prevent the voltage from being applied to T, the switch S
3 is operated to disconnect the signal terminal D3 of the DUT from the signal pin T2 of the LSI tester. The switch S4 keeps operating even when the applied voltage (excitation current) becomes 0 until the next voltage is applied.

The switch S5 in the initial state shown in FIG.
Are the signal pin T5 of the LSI tester and the signal pin D7 of the DUT.
Switch S6 is connected to the test board GN
The connection is made between the D plane g and the GND terminal D8 of the DUT.

As shown in FIG. 4, the switch S5 of the relay R3
Operate according to the relay control signal input from the signal pin T11 of the LSI tester. Signal pin T11 of LSI tester
While the relay control signal is being input, the operation is performed so as to disconnect the signal terminal D7 of the DUT and the signal pin T5 of the LSI tester.

The switch S6 is a signal pin of the LSI tester.
It operates by the relay control signal input from T5 ,
It operates only when a voltage higher than the maximum applied voltage in the test is input, and the GND plane g of the test board and the DUT
To the GND terminal D8.

The voltage higher than the maximum applied voltage in the test is DU
Before inputting a high voltage for operating the switch S6 to prevent the voltage from being applied to T, the switch S
5 is operated to disconnect the signal terminal D7 of the DUT from the signal pin T5 of the LSI tester. The switch S6 keeps operating even when the applied voltage (excitation current) becomes 0 until the next voltage is applied.

The switch S7 in the initial state shown in FIG.
The signal pin T6 of the SI tester is connected to the signal pin D9 of the DUT, and the switch S8 is connected between the power plane v of the test board and the power terminal D10 of the DUT.

As shown in FIG. 4, the switch S7 of the relay R4
Operate according to the relay control signal input from the signal pin T11 of the LSI tester. Signal pin T11 of LSI tester
While the relay control signal is being input, the operation is performed to disconnect the signal terminal D9 of the DUT and the signal pin T6 of the LSI tester.

The switch S8 is a signal pin of the LSI tester.
It operates by the relay control signal input from T6 ,
It operates only when a voltage higher than the maximum applied voltage in the test is input, and opens between the power supply plane v of the test board and the power supply terminal D10 of the DUT.

The voltage higher than the maximum applied voltage in the test is DU
In order to prevent the voltage from being applied to T, when a high voltage for operating the switch S8 is inputted, the switch S
7 is operated to disconnect the signal terminal D9 of the DUT from the signal pin T6 of the LSI tester. The switch S8 maintains its operation until the next voltage is applied even when the applied voltage (excitation current) becomes zero.

Next, in the test board for power supply / GND terminal continuity test according to the second embodiment of the present invention shown in FIG.
The operation until the continuity test is performed will be described.

First, when a relay control signal is input from the signal pin T11 of the LSI tester, as shown in FIG. 4, the switches S1, S3, S3 of all the relays R1, R2, R3, R4.
5 and S7 operate, and DUT signal terminals D1, D3, D7, D9
And the signal terminals T1, T2, T5 and T6 of the LSI tester are disconnected.

Next, the power supply terminals D2, D10 or G of the DUT
LSI tester signal pin T for testing ND terminals D4 and D8
A voltage higher than the voltage applied in the test of the DUT is applied from 1, T2, T5 or T6 .

FIG. 4 shows a state in which a high voltage is applied from the signal terminal T1 of the LSI tester and the switch S2 of the relay R1 is operating. In this state, the power supply terminal D2 of the DUT and the LSI tester Connected to the signal terminal T1,
The continuity test of the power supply terminal D2 of the DUT is enabled.

In FIG. 4, a high voltage is applied from the signal terminal T6 of the LSI tester, and the switch S of the relay R4 is turned on.
When the power supply terminal 8 is operated, the power supply terminal D10 of the DUT is connected to the signal terminal T6 of the LSI tester, and the continuity test of the power supply terminal D10 of the DUT is enabled.

By performing the above operations, a continuity test is performed on the power supply terminals D2 and D10 or the GND terminals D4 and D8 of the DUT for each pin.

The power / GND terminal continuity test board according to the second embodiment of the present invention shown in FIG.
The difference is that during the continuity test, the potential of the power supply terminal or the GND terminal other than the measurement target is changed to the power supply plane v or GND.
It is possible to keep the potential connected to the D plane g.

Therefore, according to the second embodiment of the present invention,
When the continuity test is performed, there is an advantage that it is not necessary to apply a voltage from the LSI tester to a power supply terminal or a GND terminal other than the measurement target.

[0067]

As described above, according to the present invention, the continuity test of the power supply and the GND terminal, which was impossible with the conventional test board, can be easily performed on a pin-by-pin basis. Performance can be improved.

Furthermore, since the continuity test of all the power supplies and the GND terminals can be performed, it is possible to avoid erroneously determining an LSI in which the power supplies and the GND terminals are not conducting as a non-defective product.

Further, by installing the relay on the test board, the continuity test of all terminals of the DUT can be performed on the same board, so that the continuity test of the power supply and the GND can be realized at low cost.

Since the continuity test of the power supply and the GND terminal can be performed by switching the relay control signal, the test cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram illustrating a test board for a power supply / GND terminal continuity test according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram illustrating an operation state of a test board for a power supply / GND terminal continuity test according to the first embodiment of the present invention.

FIG. 3 is a configuration diagram illustrating a test board for a power supply / GND terminal continuity test according to a second embodiment of the present invention.

FIG. 4 is a configuration diagram illustrating an operation state of a test board for a power supply / GND terminal continuity test according to a second embodiment of the present invention.

FIG. 5 is a configuration diagram showing an operation state of a test board for a power supply / GND terminal continuity test according to a conventional example.

[Explanation of symbols]

D1, D3, D5, D6, D7, D8, D9 DUT signal pin D2, D10 DUT power pin D4, D8 DUT GND pin T1, T2, T3, T4, T5, T6 DUT of LSI tester
Signal pin for T11 LSI control signal pin for LSI tester G1 GND pin for LSI tester V1 Power supply pin for LSI tester R1, R2, R3, R4 Relay S1, S2, S3, S4, S5, S6, S7, S8 Switch d Power supply Plane g GND plane T11 Relay control signal pin T t Relay control plane

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G01R 31/02-31/04 G01R 31/28

Claims (4)

(57) [Claims] 1. A test board for a power / GND terminal continuity test for electrically connecting a device under test and an LSI tester, wherein a switch is provided on the test board, and the switch is switched to provide a signal of the LSI tester. Pin the device under test
Power supply / GND play of test board to signal terminal of chair
To the power supply terminal and GND terminal of the device under test.
And the signal pins of the LSI tester are replaced with the signal terminals of the device under test,
A test board for a power supply / GND terminal continuity test, wherein a state of connection to a D terminal is switched . 2. The test board for a power supply / GND terminal continuity test according to claim 1, wherein the switch performs switching by operating a relay based on a relay control signal. 3. The test board according to claim 2, wherein the relay performs an operation of switching the switches at a time. 4. The test board for power supply / GND terminal continuity test according to claim 2, wherein said relays perform switching operations of said switches individually and independently.