CN103091618B - Electronic test system and related method - Google Patents
Electronic test system and related method Download PDFInfo
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- CN103091618B CN103091618B CN201110344374.1A CN201110344374A CN103091618B CN 103091618 B CN103091618 B CN 103091618B CN 201110344374 A CN201110344374 A CN 201110344374A CN 103091618 B CN103091618 B CN 103091618B
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Abstract
An electronic test system and related method, comprising a first and a second connection terminal, a signal source terminal, a first and a second measurement terminal, a switching circuit, a fifth and a seventh switch; the first and second connection terminals are respectively coupled to two pins of a tested chip; the signal source end is used for coupling a signal generator; the first and second measurement terminals are coupled to a measurement machine; the switching circuit is coupled to the signal source terminal at the first front side terminal and the fourth front side terminal, and coupled to the first connection terminal and the second connection terminal at the first rear side terminal and the fourth rear side terminal, respectively, to control the conduction between the first front side terminal and the first rear side terminal and the conduction between the fourth front side terminal and the fourth rear side terminal; the fifth switch is coupled between the fourth rear side end and the first measurement end, and the seventh switch is coupled between the first connection end and the second measurement end.
Description
Technical field
The present invention has about a kind of comparatron and correlation technique, and relates to comparatron and the correlation technique of the excessively electrical stress (Electrical Over-Stress, EOS) of a kind of test especially.
Background technology
Chip (integrated circuit) is one of most important hardware foundation of advanced information society.Chip can be arranged the pin position of conduction, as power supply pin, grounding leg position and signal pin.Chip couples operating voltage and ground terminal voltage, to draw the electric power needed for running respectively via power supply pin and grounding leg position.Chip also can exchange signal via signal pin and other external circuitry (as circuit board or another chip).
But, because the power supply pin of chip, grounding leg position and signal pin are all conduct electricity, also the disturbance of extraneous electric circumstance can be conducted to chip internal.Excessively electrically stress is exactly the one in electrical disturbance, and the high voltage waveform reasonable time in that it showing as one section of continuity, transfers to another pin position by a pin position of chip, have the potentiality of infringement chip.
For in response to excessive electrically stress, the test of excessively electrically stress need be carried out to chip.The test of excessively electrical stress is the waveform utilizing a signal generator to produce the excessively electrical stress of emulation, and the two ends of signal generator is coupled to respectively the bipod position of chip, with test chip in the reaction of these two pin interdigits to excessively electrical stress.Due to excessive electrically stress may occur in the signal pin of chip to grounding leg position, power supply pin is to signal pin, grounding leg position to signal pin, and signal pin is to power supply pin, therefore excessively electrically the test of stress also will contain these four kinds possible aspects.But chip has the signal pin that multiple needs are tested individually, the two ends of signal generator need be coupled to corresponding signal pin, power supply pin and grounding leg position with manpower by existing known technology one by one separately, very consuming time, also easily make mistakes.
Summary of the invention
For overcoming the shortcoming of known technology, the invention relates to and a kind ofly robotization can carry out comparatron and the correlation technique of excessively electrically stress test.
An object of the present invention is to provide the comparatron of a kind of test one chip, be provided with multiple first link, multiple second link, a news source and one second interrogate source, one first measuring junction and one second measuring junction, a commutation circuit, one the 5th switch, multiple 6th switch and the 7th switch, and interrogate source switch and one second and interrogate source switch, multiple 8th switch, and an ON-OFF control circuit.Each first link is in order to couple one of them of power supply pin and grounding leg position, and each second link is in order to a signal pin of coupling chip.News source and second interrogates source respectively in order to couple the two ends of signal generator.First measuring junction and the second measuring junction are respectively in order to couple the two ends of a measurement board.
Commutation circuit has one first front side end, one second front side end, one the 3rd front side end and one the 4th front side end, and one first rear side end, one second rear side end, one the 3rd rear side end and one the 4th rear side end.Namely news source switch is coupled between news source and the first front side end, and optionally conducting is between news source and the first front side end; First front side end is also coupled to the 4th front side end, makes the first front side end and the 4th front side end all couple news source via interrogating source switch.Similarly, the second news source switch is coupled between the second news source and the second front side end, and optionally conducting is between the second news source and the second front side end; Second front side end is also coupled to the 3rd front side end, makes the second front side end and the 3rd front side end all interrogate source switch via second and couples the second news source.First to fourth switch can be provided with in commutation circuit, first switch is coupled between the first front side end and the first rear side end, second switch is coupled between the second front side end and the second rear side end, 3rd switch is coupled between the 3rd front side end and the 3rd rear side end, and the 4th switch is coupled between the 4th front side end and the 4th rear side end.
5th switch is coupled between the 4th rear side end and the first measuring junction, and optionally conducting is between the 4th rear side end and the first measuring junction.3rd rear side end is also coupled to the 4th rear side end.
Multiple 6th switch and the 7th switch correspond respectively to multiple first link.Each 7th switch is coupled between the second measuring junction with the first corresponding link, and optionally conducting is between the first link that the second measuring junction is corresponding with this.Each 6th switch is coupled between the first rear side end with the first corresponding link, and optionally conducting is between the first link that the first rear side end is corresponding with this.
Multiple 8th switch corresponds respectively to multiple second link, and each 8th switch is coupled between the 3rd rear side end with the second corresponding link, and optionally conducting is between the second link that the 3rd rear side end is corresponding with this.
ON-OFF control circuit couple and control each five to eight switch, news source switch and second interrogates the conducting of source switch, also couples commutation circuit to control its conducting.
Comparatron can operate on the test pattern of a checking mode (as switches channel check pattern), the excessively electrical stress of one second checking mode (as a switch checking mode), one the 3rd checking mode (as a continuity check pattern) and one.
When operating on checking mode (as commutation circuit checking mode), 5th switch, (one or more) the 6th switch and (one or more) the 7th switch all conductings, news source switch and second interrogates source switch not conducting, each 8th switch can not conducting, and commutation circuit then operates on one first switch mode and one second switch mode.When commutation circuit operates on the first switch mode, meeting not conducting between the second front side end and the second rear side end, and not conducting between the 3rd front side end and the 3rd rear side end, to check the first front side end and the first rear side end, whether conducting between the 4th front side end and the 4th rear side end can be normally controlled, namely checks whether the first switch and the 4th switch normally can transport work.When operating on the second switch mode, commutation circuit can not conducting between the first front side end and the first rear side end, and not conducting between the 4th front side end and the 4th rear side end, to check the second front side end and the second rear side end, whether conducting between the 3rd front side end and the 3rd rear side end can be normally controlled, namely checks second switch and the 3rd switch.
When comparatron operates on the second checking mode (as switch checking mode), the 5th switch conduction, news source switch and second interrogates source switch not conducting, each 8th switch not conducting; Commutation circuit is conducting between the first front side end and the first rear side end then, also conducting between the 4th front side end and the 4th rear side end, and not conducting between the 3rd front side end and the 3rd rear side end, also not conducting between the second front side end and the second rear side end.So, the 6th switch corresponding to each first link and the 7th switch can just be checked one by one.
When comparatron operates on the 3rd checking mode (as continuity check pattern), the continuity (continuity) of each signal pin to power supply pin and grounding leg position can be checked one by one via each the second link.When checking the signal pin of its correspondence via a certain second link under the 3rd checking mode, 5th switch conduction, (one or more) the 7th switch conduction, each 6th switch not conducting, the 8th switch conduction that this second link is corresponding, news source switch and second interrogates source switch then not conducting, commutation circuit is neither conducting between first, second, third and fourth front side end and first, second, third and fourth rear side end, and in the first measuring junction feeding negative current, the continuity of this respective signal pin position and grounding leg interdigit so just can be checked.Moreover, if in the first measuring junction feeding positive current, the continuity between this respective signal pin position and power supply pin just can be checked.
When electronic system operates on the test pattern of excessively electrically stress, can via the signal pin of each second link test correspondence.When signal pin corresponding to a certain second link will be tested in test mode, 5th switch and each the 7th switch not conducting, news source switch and second interrogates source switch conducting, to should the 8th switch conduction of the second link, 6th switch conduction of corresponding grounding leg position, commutation circuit is between the 3rd front side end and the 3rd rear side end, conducting between the first front side end and the first rear side end, and not conducting between the second front side end and the second rear side end, also not conducting between the 4th front side end and the 4th rear side end, so just can test the excessively electrically stress of this signal pin to grounding leg interdigit.If make commutation circuit conducting between the second front side end and the second rear side end, conducting be between the 4th front side end and the 4th rear side end, and not conducting between the 3rd front side end and the 3rd rear side end, not conducting between the first front side end and the first rear side end, then can test the excessively electrically stress between grounding leg position to this signal pin.
In test mode, if the 6th switch not conducting of grounding leg position correspondence, change the 6th switch conduction making power supply pin corresponding, then can test the excessively electrically stress between this signal pin and this power supply pin.When commutation circuit between the 3rd front side end and the 3rd rear side end, conducting between the first front side end and the first rear side end, and between the second front side end and the second rear side end, not conducting between the 4th front side end and the 4th rear side end, the excessively electrically stress between this signal pin to this power supply pin can be tested.If make commutation circuit conducting between the second front side end and the second rear side end, conducting be between the 4th front side end and the 4th rear side end, and not conducting between the 3rd front side end and the 3rd rear side end, not conducting between the first front side end and the first rear side end, then can test the excessively electrically stress between this power supply pin to this signal pin.
Another object of the present invention is to provide a kind of method being applied to aforementioned electronic test macro, comprise: with the 5th switch by the first measuring junction conducting to the 4th rear side end, with the 7th switch and (one or more) the 6th switch by the second measuring junction conducting to (one or more) first link and the first rear side end, news source switch is utilized to make not conducting between news source and the first front side end, and utilize the second news source switch to make not conducting between the second news source and the 3rd front side end, to check the function of commutation circuit.
Moreover, with the 5th switch by the first measuring junction conducting to the 4th rear side end, make each 7th switch by each first link conducting to the second measuring junction, each first link and the first rear side end not conducting is made with each 6th switch, with one the 8th switch by the second corresponding for signal pin link conducting to the 4th rear side end, and make commutation circuit between the first front side end and the first rear side end, between the second front side end and the second rear side end, between the 3rd front side end and the 3rd rear side end, neither conducting between the 4th front side end and the 4th rear side end, the continuity of this signal pin to grounding leg position and power supply pin can be checked.
Commutation circuit is used to make the first front side end conducting to the first rear side end, make the 4th front side end conducting to the 4th rear side end, news source and the first front side end not conducting is made to interrogate source switch, the second news source and the second front side end not conducting is made with the second news source switch, make the 5th switch conduction, to check the 7th switch corresponding to each first link and the 6th switch.
When will carry out the test of excessively electrically stress to the signal pin corresponding to a certain second link, the 8th switch conduction that this second link is corresponding can be made, make each 7th switch not conducting, 5th switch not conducting, and use commutation circuit to make the first front side end and the first rear side end not conducting, make the second front side end and the second rear side end conducting, make the 3rd front side end and the 3rd rear side end not conducting, make the 4th front side end and the 4th rear side end conducting.Meanwhile, one the 6th switch is also used to make grounding leg position that one first link is corresponding or power supply pin conducting to the second rear side end.So, interrogate source and second to interrogate source and can be coupled to the signal pin of chip and power supply or grounding leg position via this second link and this first link respectively.Commutation circuit is used to make the 3rd front side end and the 3rd rear side end conducting, make the first front side end and the first rear side end conducting, make the second front side end and the second rear side end not conducting, also make the 4th front side end and the 4th rear side end not conducting, then the second news source can be made to be coupled to signal pin and power supply or grounding leg position via this second link and this first link respectively with news source.
In order to have better understanding, preferred embodiment cited below particularly to above-mentioned and other side of the present invention, and coordinating institute's accompanying drawings, being described in detail below.
Accompanying drawing explanation
What Fig. 1 illustrated is the schematic diagram carrying out excessively electrically stress.
Fig. 2 signal be comparatron according to one embodiment of the invention.
What Fig. 3 illustrated being the flow process of carrying out excessively electrically stress test according to one embodiment of the invention with Fig. 2 comparatron.
What Fig. 4 illustrated is one of flow process checking switch arrays according to one embodiment of the invention.
What Fig. 5 illustrated is the schematic diagram carrying out Fig. 4 flow process with Fig. 2 comparatron.
What Fig. 6 illustrated is one of flow process checking switch arrays according to one embodiment of the invention.
What Fig. 7 illustrated is the schematic diagram carrying out Fig. 6 flow process with Fig. 2 comparatron.
What Fig. 8 illustrated is one of flow process checking switch arrays according to one embodiment of the invention.
What Fig. 9 illustrated is the schematic diagram carrying out Fig. 8 flow process with Fig. 2 comparatron.
What Figure 10 illustrated is signal pin is carried out to one of flow process of continuity check according to one embodiment of the invention.
What Figure 11 illustrated is the schematic diagram carrying out Figure 10 flow process with Fig. 2 comparatron.
What Figure 12 illustrated is signal pin is carried out to one of flow process of continuity check according to one embodiment of the invention.
What Figure 13 illustrated is the schematic diagram carrying out Figure 12 flow process with Fig. 2 comparatron.
What Figure 14 illustrated is one of flow process of signal pin being carried out to excessively electrically stress test according to one embodiment of the invention.
What Figure 15 illustrated is the schematic diagram carrying out Figure 14 flow process with Fig. 2 comparatron.
What Figure 16 illustrated is one of flow process of signal pin being carried out to excessively electrically stress test according to one embodiment of the invention.
What Figure 17 illustrated is the schematic diagram carrying out Figure 16 flow process with Fig. 2 comparatron.
What Figure 18 illustrated is one of flow process of signal pin being carried out to excessively electrically stress test according to one embodiment of the invention.
What Figure 19 illustrated is the schematic diagram carrying out Figure 18 flow process with Fig. 2 comparatron.
What Figure 20 illustrated is one of flow process of signal pin being carried out to excessively electrically stress test according to one embodiment of the invention.
What Figure 21 illustrated is the schematic diagram carrying out Figure 20 flow process with Fig. 2 comparatron.
[main element label declaration]
10: comparatron 12: switch arrays
14: on-off controller 16: circuit board
18: slot 20: chip
22: internal circuit 24: signal generator
26: measure board 28: interface
30: commutation circuit 32a-32b, 34a-34b: aspect
36a-36b: form
100,200,300,400,500,600,700,800,900,1000: flow process
102-118,202-212,302-312,402-416,502-514,602-614,702-712,802-812,902-912,1002-1012: step
Na-nf, ta-tc, n [.], p [.], nx-ny: node
Swa-swb, sw0-sw5, sw6 [.], sw7 [.], sw6b, sw7b, sw8a [.], sw8b [. .]: switch
VDD [.], VSS, S [.]: link Vdd, Vss, sp: pin position
Da, Db: diode ZAP, GND: signal end
CH: channel end GNDt: board ground end
Rc, Rm, Rs1-Rs2: resistance Lr: inductance
Cc: electric capacity U: voltage source
W0: waveform
Embodiment
Please refer to Fig. 1, what it was illustrated is the various test aspects of a chip 20 being carried out to excessively electrically stress test.Chip 20 can be provided with multiple signal pin, one or more power supply pin and one or more grounding leg position, in Fig. 1 respectively with pin position sp, Vdd and Vss representatively.The internal circuit 22 of chip 20 draws electric power (power) by pin position Vdd and Vss, and via pin position sp exchange data signals.Can be provided with protection circuit (as ESD protection circuit) between sp and the Vdd of pin position, between sp and the Vss of pin position, available diode Da and Db represents.Internal circuit 22 can have one or more field of power supplies (powerdomain does not draw), and each field of power supplies can have special power supply pin and/or grounding leg position separately.For example, different operating voltage can be drawn respectively by respective power supply pin in different electrical power field, and/or different electrical power field can couple ground terminal voltage via respective grounding leg position.
When will carry out the test of excessively electrically stress to pin position sp, the voltage waveform of excessively electrically stress can be produced by a signal generator 24; Illustrate a kind of embodiment w0 of voltage waveform in Fig. 1, also illustrate a kind of circuit framework embodiment of signal generator 24.In Fig. 1 embodiment, signal generator 24 is provided with one and provides high-tension voltage source U, resistance Rc, Rm, Rs1 and Rs2, a switch sw0, an an electric capacity Cc and inductance L r, to provide the test voltage waveform w0 of excessively electrically stress between two signal end ZAP and GND.Switch sw0 is coupled between node nx and ny, and resistance Rc is coupled between voltage source U and node nx, and electric capacity Cc is coupled between node nx and signal end GND; Resistance Rm and inductance L r is series between node ny and signal end ZAP, and resistance Rs1 is coupled between node ny and signal end GND, and resistance Rs2 is then coupled between signal end ZAP and GND.Before generation waveform w0, switch sw0 opens a way (not conducting), and voltage source U charges to electric capacity Cc via resistance Rc.Then, switch sw0 closes (conducting), and the electric charge in electric capacity Cc can transfer to node ny, via resistance Rs1, Rs2 and inductance L r effect and form waveform w0.Wherein, resistance Rs1 and Rs2 can control waveform w0 continue time (duration), inductance L r moulds the rise time (rise time) of waveform w0, and resistance Rm is then the resistance of impedance matching.
In the aspect 32a of excessive electrically stress test, what test is forward (positive) the excessively electrically stress that is benchmark with grounding leg position.Under this aspect 32a, all power supply pins (as pin position Vdd) open circuit of chip 20, all grounding leg positions (as pin position Vss) is coupled to signal end GND jointly with ground connection, and tested signal pin sp is then coupled to separately signal end ZAP; So, just can emulate by the excessively electrically stress of signal pin sp to grounding leg position Vss.Negative sense (negative) the excessively electrically stress that what aspect 32b tested is is benchmark with grounding leg position; All power supply pins (as pin position Vdd) open circuit of chip 20, (as pin position Vss) is coupled to signal end ZAP jointly in all grounding leg positions, tested signal pin sp is then coupled to separately signal end GND, to test by the excessively electrically stress of grounding leg position Vss to signal pin sp.
In aspect 34a, what test is then take power supply pin as the forward excessively electrically stress of benchmark.Under this aspect 34a, a power supply pin (as pin position Vdd) of chip 20 is coupled to separately signal end GND, and all grounding leg positions (as pin position Vss) all opens a way, and tested signal pin sp is then coupled to separately signal end ZAP; So, just can emulate by the excessively electrically stress of signal pin sp to power supply pin Vdd.Aspect 34b test is with power supply pin be benchmark negative sense excessively electrically stress test; One power supply pin (as pin position Vdd) of chip 20 is coupled to separately signal end ZAP, open a way in all grounding leg positions (as pin position Vss), tested signal pin sp is then coupled to separately signal end GND, to test by the excessively electrically stress of power supply pin Vdd to signal pin sp.
Please refer to Fig. 2, what it was illustrated is according to the comparatron 10 of one embodiment of the invention, not only automatically can carry out the excessively electrically stress test of various aspect, can also carry out test front and back self-examination.Can arrange in pairs or groups signal generator 24 of comparatron 10 is tested chip 20 with measuring board 26, and it is provided with switch arrays 12, on-off controller 14, circuit board 16 and a slot 18.Switch arrays 12 are provided with a commutation circuit 30, switch swa and swb (news source switch and second interrogates source switch), a switch sw5 (the 5th switch), a Nv switch sw6 [1] to sw6 [Nv] and switch sw6b (the 6th switch), a Nv switch sw7 [1] to sw7 [Nv] and switch sw7b (the 7th switch), a Na switch sw8a [1] to sw8a [Na] and Na*Nb switch sw8b [1,1] to sw8b [Na, Nb] (the 8th switch); Switch sw1 to sw4 (first to fourth switch) is then provided with in commutation circuit 30.
Each switch in switch arrays 12 can be relay (relay) or other can the element of controlled conducting/not conducting or circuit; Namely ON-OFF control circuit 14 is coupled to these switches (couple pass lie in Fig. 2 omit).ON-OFF control circuit 14 accepts automatic test course steering order via interface 28, and controls each switch in (driving) switch arrays 12 according to this, makes each switch can conducting or not conducting independently.
In switch arrays 12, switch swa is coupled between node na and nc, and optionally conducting is between node na and nc; Node na can be considered a news source, in order to couple the signal end GND of signal generator 24.Similarly, switch swb is then coupled between node nb and nd, and node nb can be considered one second news source, in order to couple another signal end ZAP of signal generator 24.
One end of switch sw1 and sw4 is coupled to node nc (being respectively the first front side end and the 4th front side end) jointly, and the other end (the first rear side end and the 4th rear side end) of switch sw1 and sw4 is then respectively coupled to node ne and tc; Conducting between switch sw1 Controlling vertex nc and ne, the conducting of switch sw4 then between Controlling vertex nc and tc.Similarly, one end of switch sw2 and sw3 is coupled to node nd (being respectively the second front side end and the 3rd front side end) jointly, and the other end (the second rear side end and the 3rd rear side end) of switch sw2 and sw3 is then respectively coupled to node ne and tc; Whether conducting between switch sw2 Controlling vertex nd and ne, switch sw3 then whether conducting between Controlling vertex nd and tc.
Switch sw5 is coupled between node ta and tc, and optionally conducting is between node ta and tc; Node ta and tb can be considered the first measuring junction and the second measuring junction, holds GNDt with measuring the channel end CH of board 26 and board respectively in order to couple.
In switch arrays 12, the quantity Nv of switch sw6 [1] to sw6 [Nv] (and switch sw7 [1] to sw7 [Nv]) can be more than or equal to 1; Each switch sw6 [i] is corresponding to one switch sw7 [i] (i equals 1 to Nv).Switch sw6 [i] is coupled between node ne and node n [i], and optionally conducting is between node ne and n [i]; Switch sw7 [i] is then coupled between node n [i] and node tb, the conducting between Controlling vertex n [i] and tb.Switch sw6b and sw7b is corresponding, and switch sw6b is coupled to control this two internodal conducting between node ne and nf, and switch sw7b is then coupled between node nf and tb, and optionally conducting is between node nf and tb.Each node n [1] is mutually insulated to n [Nv] and node nf, and extends to link VDD [1] to VDD [Nv] and link VSS (the first link) respectively.Link VDD [1] to VDD [Nv] can be coupled to each power supply pin of chip 20 respectively via the wiring on circuit board 16 and slot 18; For example, a certain link VDD [i] can be coupled to pin position Vdd.Similarly, link VSS can be coupled to the grounding leg position of chip 20 via the wiring on circuit board 16 and slot 18, as pin position Vss.
In switch arrays 12, the quantity Na of switch sw8a [1] to sw8a [Na] can be more than or equal to 1, each switch sw8a [j] (j equals 1 to Na) is coupled between node tc and p [j], and optionally conducting is between node tc and p [j]; Each node p [1] is mutually insulated to p [Na].Each switch sw8a [j] can corresponding one or more switch sw8b [j, k]; In Fig. 2 embodiment, each switch sw8a [j] equal corresponding Nb switch sw8b [j, 1] is to sw8b [j, Nb].One end of each switch sw8b [j, k] is coupled to node p [j], and the other end then extends to link S [(j-1) * Nb+k] (j equals 1 to Na, and k equals 1 to Nb); Each switch sw8b [i, j] can conducting between Controlling vertex p [j] and link S [(j-1) * Nb+k].Therefore, Na switch sw8a [1] altogether may correspond to Na*Nb link S [1] to S [Na*Nb] (second link) with Na*Nb switch sw8b [1,1] to sw8b [Na, Nb] to sw8a [Na].Each link S [(j-1) * Nb+k] can be coupled to a signal pin of chip 20 via the wiring of circuit board 16, slot 18, such as pin position sp.In another kind of embodiment, switch sw8b [j, k] can omit, direct as link by the node p [j] of switch sw8a [j], therefore Na switch sw8a [1] may correspond to Na link S [1] to S [Na] to sw8a [Na].
In one embodiment of this invention, quantity Nv can equal 10, to provide 10 link VDD [1] to VDD [10] being coupled to 10 kinds of power supply pins respectively.Quantity Na can equal 4, and quantity Nb can equal 64, to provide 256 link S [1] to S [256] that can be coupled to signal pin.
Please refer to Fig. 3, what it was illustrated is the flow process 100 of carrying out excessively electrically stress test according to one embodiment of the invention.Flow process 100 can be implemented in the comparatron 10 of Fig. 2, tests for chip 20.The key step of flow process 100 can be described as follows:
Step 102: start flow process 100.
Step 104: check the conventional switch in switch arrays 12, such as, say it is switch sw1 to sw4, each switch sw6 [1] to sw6 [Nv], switch sw6b, switch sw7 [1] to sw7 [Nv] and switch sw7b.In the subsequent step of flow process 100, these switches will switch continually between conducting and not conducting, therefore can check whether each switch can normal operation in this step in advance.The flow process of carrying out this step with comparatron 10 can further illustrate after a while, such as Fig. 4 to Fig. 9.After confirming the normal operation of switch energy, a time step 106 can be proceeded to.
Step 106: the continuity check of signal pin is carried out in the measured signal pin position all to chip 20, and check result is recorded to data logging (data log).Comparatron 10 automatically can carry out this continuity check, and the flow process of carrying out can further illustrate after a while, such as Figure 10 to Figure 13.The number of measured signal pin position can be less than all signal pin numbers of tested chip; In other words, some signal pin can be tested.
Step 108: excessively electrically stress test is carried out to a certain measured signal pin position of chip 20, such as say it is test aspect 32a in Fig. 2,32b, 32c and/or 32d, to apply the test waveform of excessively electrically stress between this measured signal pin position and grounding leg position and/or a certain power supply pin.To same chip, wherein one or several (being less than four kinds) of four kinds of aspects only can be carried out; In other words, the test of all four kinds of aspects need not be carried out to same chip.In one embodiment, can one species/batch chip in select four chips as tested chip, and respectively flow process 100 is carried out to each tested chip; Each tested chip only accepts the test of single aspect, but different tested chip is tested with different aspects respectively.Comparatron 10 automatically can carry out this excessively electrically stress test, and its flow process can further illustrate, after a while as Figure 14 to Figure 21.
Step 110: the continuity examining all measured signal pin positions again, and check result is recorded to data logging, mutually to compare with the check result of step 106; Whether impairedly because of excessively electrical stress tested chip can be understood by comparative result.
Step 112: because aspect 34a and 34b is the test based on single power supply pin position, if the test that step 108 is carried out comprises aspect 34a and/or 34b, then can repeat step 108 and 110 for each different power supply pin to be measured one by one.If there is no power supply pin to be measured, a time step 114 just can be proceeded to.
Step 114: because step 108 is tested for single signal pin position, therefore step 108 and 110 can be repeated for different measured signal pin positions; If all measured signal pin positions all completing steps 108 test and without other wait test signal pin, just can proceed to step 116.
Step 116: identical with step 104, examines switch arrays again.
Step 118: process ends 100.
The explanation of continuity Fig. 3, please refer to Fig. 4 and Fig. 5; What Fig. 4 illustrated being one of them flow process 200 checking switch arrays 12 according to one embodiment of the invention; When carrying out step 104 and 116 (Fig. 3), comparatron 10 can check switch sw1 and sw4 according to flow process 200.Fig. 5 is then the schematic diagram of flow process 200 when carrying out.The key step of flow process 200 can be described below.
Step 202: make all switch open (not conducting) in switch arrays 12; All switches comprise switch swa, swb, sw1 to sw5, sw6 [1] to sw6 [Nv] and sw6b, sw7 [1] to sw7 [Nv] with sw7b, sw8a [1] to sw8b [Na] and sw8b [1,1] to sw8b [Na, Nb].Then, switch sw5 is made to close conducting.
Step 204: gauge tap sw1, sw4, sw6 [i] and sw7 [i].Step 204 and subsequent step 206,208 can repeat four times, come gauge tap sw1, sw4, sw6 [i] and sw7 [i] when each repetition according to form 36a.For example, when first time carries out step 204, switch sw1, sw4, sw6 [i] and sw7 [i] all closed (i.e. conducting, with " close " representative in form 36a); When second time carries out step 204, then switch sw4 is made to change open circuit (not conducting, with " open ") representative into.Third time, when carrying out step 204, makes switch sw4 change into once again closed; When carrying out step 204 the 4th time, then make switch sw1 change open circuit into by closed, switch sw4 remains closed.Switch sw6 [i] being controlled, for time closed, single one sw6 [i] can be made to close, or, switch sw6 [1] to switch sw6 [Nv] (or wherein certain several) also can be made all closed.Similarly, when making switch sw7 [i] close, can be that single one sw7 [i] is closed, or, may also be and make switch sw7 [1] to switch sw7 [Nv] (or wherein certain several) all closed.Moreover also can make sw6 [i1] and sw7 [i2] conducting, wherein, foot mark i1 and i2 is different.
Step 206: make measurement board 26 be fed to electric current in channel end CH, the electric current (1mA is the per mille of 1 ampere) of such as 1mA.
Step 208: to measure board 26 in channel end CH measuring voltage.Step 204,206 and 208 repeat for each time can whether can correctly operate by Test Switchboard sw1 and sw4; Situation when namely what Fig. 5 illustrated is step 204,206 and 208 first times carried out.Due to switch sw5 conducting, the channel end CH of measurement board 26 is via node ta conducting to node tc, and board ground holds GNDt then because of the closed of switch sw6 [i] and sw7 [i] by node tb conducting to node ne.Because switch sw2 and sw3 all maintains open circuit, channel end CH and board ground hold between GNDt whether can form loop via node tc, nc and ne, will depend on switch sw1 and sw4.When first time carries out step 204, if switch sw1 and sw4 can be normally controlled closed, node tc to nc and node nc to ne will be switched on respectively, and holds between GNDt form low-impedance loop at channel end CH and board; Therefore, the voltage that channel end CH measures should convergence 0 volt (difference with 0 volt be less than preset error), is similar to short circuit.Expected results in form 36a just represents as switch sw1 and sw4 normal operation, the result that channel end CH should measure.When first time carries out step 204, if the voltage not convergence 0 volt that channel end CH measures, that may cannot normal operation with regard to representation switch sw1 and/or sw4.Similarly, when second time repeats step 204, because switch sw4 is by controlled open circuit, channel end CH and board ground are held between GNDt and should be able to cannot be formed low-impedance path because of the not conducting between node tc and nc, therefore the voltage measurement expected results of channel end CH should be open circuit (the non-convergence of voltage 0 volt).
Step 210: if step 204,206 and 208 multiplicity do not reach four times, then get back to step 204; If completed all switch option in form 36a, just step 212 can be proceeded to.
Step 212: whether the actual measured results of comparison channel end CH under each step repeats meets each expected results of form 36a; If so, representation switch sw1 and sw4 can normal operation, can be normally controlled and switch between conducting and not conducting.
The explanation of continuity Fig. 3, please refer to Fig. 6 and Fig. 7; What Fig. 6 illustrated being one of them flow process 300 checking switch arrays 12 according to one embodiment of the invention; When carrying out step 104 and 116 (Fig. 3), comparatron 10 can check switch sw2 and sw3 according to flow process 300.Fig. 7 is then the schematic diagram of flow process 300 when carrying out.The principle of flow process 300 with carry out to be analogized by flow process 200; The key step of flow process 300 can be described below.
Step 302: first make all switch open in switch arrays 12, then make switch sw5 close conducting.
Step 304: gauge tap sw2, sw3, sw6 [i] and sw7 [i].Step 304 and subsequent step 306,308 can repeat four times, come gauge tap sw2, sw3, sw6 [i] and sw7 [i] when each repetition according to form 36b.That is, when first time carries out step 304, switch sw2, sw3, sw6 [i] and sw7 [i] are all closed; When second time carries out step 304, then switch sw3 is made to change open circuit into.Third time, when carrying out step 304, makes switch sw3 change into once again closed; When carrying out step 304 the 4th time, then make switch sw2 change open circuit into by closed, switch sw3 remains closed.
Step 306: make measurement board 26 be fed to electric current in channel end CH, the electric current (1mA is the per mille of 1 ampere) of such as 1mA.
Step 308: to measure board 26 in channel end CH measuring voltage.Step 304,306 and 308 repeat for each time can whether can correctly operate by Test Switchboard sw2 and sw3; Situation when namely what Fig. 7 illustrated is step 304,306 and 308 first times carried out.Closed switch sw5 by measure board 26 channel end CH via node ta conducting to node tc, board ground end GNDt then because of switch sw6 [i] and the closed of sw7 [i] by node tb conducting to node ne.Because switch sw1 and sw4 maintains open circuit, therefore, channel end CH and board ground hold between GNDt whether can form loop via node tc, nd and ne, will depend on switch sw2 and sw3.For example, when first time carries out step 204, if switch sw2 and sw3 can be normally controlled closed, node tc to nd and node nd to ne will be switched on respectively, and hold between GNDt form low-impedance loop at channel end CH and board, make the voltage convergence 0 volt that channel end CH measures.Also the expected results of measurement is listed in form 36b.
Step 310: if step 304,306 and 308 multiplicity do not reach four times, then get back to step 304; If completed all switch option in form 36b, just step 312 can be proceeded to.
Step 312: whether the actual measured results of comparison channel end CH under each step repeats meets each expected results of form 36b; If so, representation switch sw2 and sw3 can normal operation.
The explanation of continuity Fig. 3, please refer to Fig. 8 and Fig. 9; What Fig. 8 illustrated being one of them flow process 400 checking switch arrays 12 according to one embodiment of the invention; Carry out step 104 with 116 time, comparatron 10 can check switch sw6 [i] corresponding to each link VDD [i] and sw7 [i] according to flow process 400, and checks switch sw6b and the sw7b that link VSS is corresponding.Fig. 9 is then the schematic diagram of flow process 400 when carrying out.The key step of flow process 400 can be described below.
Step 402: first make all switch open in switch arrays 12, then make switch sw5 close conducting.
Step 404: to a certain given foot mark i gauge tap sw1, sw4, sw6 [i] and sw7 [i].Mark i for same foot, step 304 and subsequent step 306,308 can repeat four times, come gauge tap sw1, sw4, sw6 [i] and sw7 [i] when each repetition according to form 38.That is, when carrying out step 404 for the first time to same a pair sw6 [i]/sw7 [i], switch sw1, sw4, sw6 [i] and sw7 [i] are all closed; When second time carries out step 404, then switch sw7 [i] is made to change open circuit into.Third time, when carrying out step 404, makes switch sw7 [i] change into closed once again; When carrying out step 404 the 4th time, then make switch sw6 [i] change open circuit into by closed, switch sw7 [i] maintains conducting.
Step 406: make measurement board 26 be fed to electric current in channel end CH, the electric current (1mA is the per mille of 1 ampere) of such as 1mA.
Step 408: to measure board 26 in channel end CH measuring voltage.Step 404,406 and 408 repeat for each time can test certain pair of switches sw6 [i] and sw7 [i] and whether can correctly operate; Situation when namely what Fig. 9 illustrated is step 404,406 and 408 first times carried out.By the closed conducting of switch sw5, sw4 and sw1, the channel end CH measuring board 26 can via node ta conducting to node tc, by node tc conducting to node nc, and by node nc conducting to node ne.So, channel end CH and board ground holds between GNDt and whether can be formed loop via node n [i] and will depend on switch sw6 [i] and sw7 [i].For example, when first time carries out step 404, if switch sw6 [i] can be normally controlled closed with sw7 [i], node ne to n [i] and node n [i] will be switched on to tb, and hold between GNDt form low-impedance loop at channel end CH and board, make the voltage convergence 0 volt that channel end CH measures.Also the expected results of measurement is listed in form 38.
Step 410: to same group of switch sw6 [i]/sw7 [i], if step 404,406 and 408 multiplicity do not reach four times, then repeat to step 404; If completed all switch option in form 38 for same group of switch sw6 [i]/sw7 [i], just step 412 can be proceeded to.
Step 412: for same group of switch sw6 [i]/sw7 [i], whether the actual measured results that comparison each step repeats meets in form 38 each expected results listed; If so, representing this group switch sw6 [i] can normal operation with sw7 [i].
Step 414: proceed to 412 by step 402 and can check a pair sw6 [i] and sw7 [i].Because have Nv in switch arrays 12 to switch sw6 [i] and sw7 [i], therefore step 402 can be carried out respectively to 412 to each pair of switch sw6 [i] with sw7 [i].Certain pair of switches sw6 [i] and sw7 [i] are carried out step 402 to 412 after, if also have other will check switch, then can upgrade the value of foot mark i, repeat to step 402.Except carrying out step 402 respectively to 412 to switch sw6 [1] to sw6 [Nv] and each group of switch sw6 [i] in switch sw7 [1] to sw7 [Nv] with sw7 [i], also step 402 can be carried out to 412 for switch sw6b and sw7b, to check whether switch sw6b and sw7b can normal operation.If all Nv have carried out step 402 to 412 all to switch sw6 [i] and sw7 [i] and switch sw6b and sw7b, just step 414 can be proceeded to.
Step 416: complete flow process 400.
In step 104 (with 116), carry out flow process 200,300 and 400, just can check that each switch sw1 to sw4 in switch arrays 12, sw6 [1] to sw6 [Nv], sw6b, sw7 [1] are to sw7 [Nv] and sw7b.
The explanation of continuity Fig. 3, please refer to Figure 10 and Figure 11; What Figure 10 illustrated is check each signal pin one of them flow process 500 successional according to one embodiment of the invention; When carrying out step 106 and 110, comparatron 10 can check each respective signal pin position of chip 20 via link according to flow process 500, such as say it is via switch sw8a [j] and sw8b [j, k] corresponding link S [(j-1) * Nb+k] checks signal pin sp, as shown in figure 11.The key step of flow process 500 can be described below.
Step 502: make all switch open in switch arrays 12, then make switch sw5 close conducting.
Step 504: make all closed conducting of switch sw7 [1] to sw7 [Nv] and sw7b.
Step 506: because signal pin sp will be checked via link S [(j-1) * Nb+k], therefore the switch sw8a [j] and sw8b [j, the k] conducting that make link S [(j-1) * Nb+k] correspondence.
Step 508: make measurement board 26 be fed to negative current in channel end CH, the electric current of such as-0.1mA.
Step 510: to measure board 26 in channel end CH measuring voltage.Namely what Figure 11 illustrated is the situation of carrying out step 506 and 508 for link S [(j-1) * Nb+k].The channel end CH measuring board 26 can by switch sw5 via node ta conducting to node tc, by switch sw8a [j] by node tc conducting to node p [j], and by switch sw8b [j, k] and by node p [j] conducting to link S [(j-1) * Nb+k], and further conducting is to signal pin sp.In chip 20, the negative current that channel end CH is fed to can via the diode Db of forward bias voltage drop conducting to grounding leg position Vss, and via link VSS conducting to node nf; And even closed switch sw7b then by node nf conducting to node tb board hold GNDt.So, if the diode Db of signal pin sp is normal, the voltage that channel end CH measures and the diode Db anode under forward bias voltage drop should conform to cross-pressure between negative electrode (both difference is less than one and presets tolerance value).Relatively, if the voltage that channel end CH measures does not meet the expection cross-pressure of diode Db, there is problem to the continuity of grounding leg position Vss in representation signal pin position sp.
Step 512: to check another signal pin, then repeat step 506 to 510 to this signal pin.For example, if a certain signal pin sp2 (not being shown in figure) is connected to link S [(j2-1) * Nb+k2], then can make inductive switch sw8a [j2] and sw8b [j2 in step 506, k2] closed, other each switch sw8a [j] (j equals 1 to Na but is not equal to j2) and/or each switch sw8b [j, k] (j equals 1 to Na but is not equal to j2, and k equals 1 to Nb but is not equal to k2) then open a way.Utilize channel end CH to be fed to negative current, and whether the voltage of comparison channel end CH meet diode along inclined expection cross-pressure, just can check the continuity of signal pin sp2 to grounding leg position Vss.If there is no the signal pin that other will check, just step 514 can be proceeded to.
Step 514: process ends 500.
What flow process 500 checked is the signal continuity of each signal pin to grounding leg interdigit.Via a similar flow process, then can check the signal continuity between each signal pin to power supply pin.The explanation of continuity Fig. 3, please refer to Figure 12 and Figure 13; What Figure 12 illustrated is check each signal pin one of them flow process 600 successional according to one embodiment of the invention; When carrying out step 106 and 110, comparatron 10 can check each respective signal pin position of chip 20 via link according to flow process 600, such as say it is via switch sw8a [j] and sw8b [j, k] corresponding link S [(j-1) * Nb+k] checks signal pin sp, as shown in figure 13.
The step 602,604,606,610,612 and 614 of flow process 600 is equal to step 502,504,506,510,512 and 514 respectively; But, when carrying out step 608, be make measurement board 26 be fed to positive current in channel end CH, the electric current of such as 0.1mA.For example, to check the signal pin sp be connected with link S [(j-1) * Nb+k], the positive current that channel end CH is fed to can by closed switch sw5, sw8a [j] and sw8b [j, k] by node ta, node tc, node p [j] with link S [(j-1) * Nb+k] conducting to signal pin sp.In chip 20, the positive current that channel end CH is fed to can via the diode Da of forward bias voltage drop conducting to power supply pin Vdd, and via link VDD [i] conducting corresponding to power supply pin Vdd to node n [i].Closed switch sw7 [i] can by node n [i] and even conducting to node tb board hold GNDt.Therefore, if the diode Da of signal pin sp normally can work and maintain the continuity of signal pin sp to power supply pin Vdd, the voltage that channel end CH measures should meet cross-pressure between the anode of diode Da under forward bias voltage drop and negative electrode.Relatively, if the voltage measured by channel end CH does not meet the expection cross-pressure of diode Da, there is problem in the continuity of representation signal pin position sp to power supply pin Vdd.
The explanation of continuity Fig. 3, please refer to Figure 14 and Figure 15; What Figure 14 illustrated being one of them flow process 700 of according to one embodiment of the invention, each signal pin being carried out to excessively electrically stress test; Carry out step 108 time, comparatron 10 can carry out the excessively electrically stress test of aspect 32a (Fig. 1) to each measured signal pin position of chip 20 according to flow process 700, such as say it is via switch sw8a [j] and sw8b [j, k] test signal pin sp corresponding to link S [(j-1) * Nb+k], as shown in figure 15.The key step of flow process 700 can be described as follows:
Step 702: make all switch open in switch arrays 12, then make switch swa and swb close conducting.
Step 704: make switch sw1 and sw3 close conducting.
Step 706: because will via the excessively electrically stress of link S [(j-1) * Nb+k] test signal pin position sp to grounding leg position Vss, therefore make switch sw8a [j] and the sw8b [j of link S [(j-1) * Nb+k] correspondence, k] conducting, and the switch sw6b conducting making link VSS corresponding.
Step 708: make signal generator 24 be fed to the test waveform of excessively electrically stress between signal end ZAP and GND.Namely what Figure 15 illustrated is the situation of carrying out step 706 and 708 for link S [(j-1) * Nb+k].The signal end ZAP of signal generator 24 can by closed switch swb through node nb conducting to node nd; Closed switch sw3 by node nd conducting to node tc, closed switch sw8a [j] by node tc conducting to node p [j], closed switch sw8b [j, k] then by node p [j] conducting to link S [(j-1) * Nb+1], and then conducting is to signal pin sp.The grounding leg position Vss of chip 20 is coupled to node nf via link VSS, and closed switch sw6b, sw1 and swa are in node nf, conducting between ne, nc and na, make the excessively electrically stress wave between signal end ZAP to GND can put between signal pin sp to grounding leg position Vss, as shown in aspect 32a.
Step 710: to check another signal pin, then repeat step 706 to 708 to this signal pin.For example, if a certain signal pin sp2 (not being shown in figure) is connected to link S [(j2-1) * Nb+k2], then can make inductive switch sw8a [j2] and sw8b [j2 in step 706, k2] closed, other each switch sw8a [j] (j equals 1 to Na but is not equal to j2) and/or each switch sw8b [j, k] (j equals 1 to Na but is not equal to j2, and k equals 1 to Nb but is not equal to k2) then open a way; Switch sw6b also closes.So, just can test for the excessively electrically stress between signal pin sp2 to grounding leg position Vss.If no signal pin position is to be tested, step 712 can be proceeded to.
Step 712: process ends 700.
The explanation of continuity Fig. 3, please refer to Figure 16 and Figure 17; What Figure 16 illustrated being one of them flow process 800 of according to one embodiment of the invention, each signal pin being carried out to excessively electrically stress test; Carry out step 108 time, comparatron 10 can carry out the excessively electrically stress test of aspect 32b (Fig. 1) to each measured signal pin position of chip 20 according to flow process 800, such as say it is via switch sw8a [j] and sw8b [j, k] test signal pin sp corresponding to link S [(j-1) * Nb+k], as shown in figure 17.The key step of flow process 800 can be described as follows:
Step 802: make all switch open in switch arrays 12, then make switch swa and swb close conducting.
Step 804: make switch sw2 and sw4 close conducting.
Step 806: because the excessively electrically stress (aspect 32b) of grounding leg position Vss to signal pin sp will be tested, therefore the switch sw6b conducting making link VSS corresponding, and make switch sw8a [j] and sw8b [j, the k] conducting of link S [(j-1) * Nb+k] correspondence.
Step 808: make signal generator 24 be fed to the test waveform of excessively electrically stress between signal end ZAP and GND.Namely what Figure 17 illustrated is the situation of carrying out step 806 and 808 for link S [(j-1) * Nb+k].The signal end ZAP of signal generator 24 can by closed switch swb and sw2 by node nb, nd conducting to node ne; And even closed switch sw6b then by node ne conducting to node nf link VSS and grounding leg position Vss.The signal pin sp of chip 20 then by closed switch sw8b [j, k] and sw8a [j] from link S [(j-1) * Nb+k] conducting to node p [j] and tc; Closed switch sw4 and swa then between node tc, nc and na conducting to signal end GND.By this, the excessively electrically stress test waveform between signal end ZAP and GND just can put between grounding leg position Vss to signal pin sp, as shown in aspect 32b.
Step 810: to test another signal pin, then repeat step 806 to 808 to this signal pin.If to be tested without other signal pin, then proceed to step 812.
Step 812: process ends 800.
The explanation of continuity Fig. 3, please refer to Figure 18 and Figure 19; What Figure 18 illustrated being one of them flow process 900 of according to one embodiment of the invention, each signal pin being carried out to excessively electrically stress test; Carry out step 108 time, comparatron 10 can carry out the excessively electrically stress test of aspect 34a (Fig. 1) for each measured signal pin position of chip 20 and each power supply pin according to flow process 900, such as say it is the excessively electrically stress of test signal pin position sp to power supply pin Vdd, as shown in figure 19.The key step of flow process 700 can be described as follows:
Step 902: make all switch open in switch arrays 12, then make switch swa and swb close conducting.
Step 904: make switch sw1 and sw3 close conducting.
Step 906: because want the excessively electrically stress of test signal pin position sp to power supply pin Vdd, and signal pin sp and power supply pin Vdd is connected respectively and holds S [(j-1) * Nb+k] and link VDD [i], therefore switch sw8a [j] and the sw8b [j of link S [(j-1) * Nb+k] correspondence can be made, k] conducting, and make switch sw6 [i] conducting that link VDD [i] is corresponding.
Step 908: make signal generator 24 be fed to the test waveform of excessively electrically stress between signal end ZAP and GND.Namely what Figure 19 illustrated is the situation of carrying out step 906 and 908 for the signal pin sp of link S [(j-1) * Nb+k] and the power supply pin Vdd of link VDD [i].Closed switch swb, sw3, sw8a [j] and sw8b [j, k] by the signal end ZAP of signal generator 24 via node nb conducting to node nd, tc, p [j], link S [(j-1) * Nb+k] and even signal pin sp.Closed switch sw6 [i], sw1 and swa then by the power supply pin Vdd of chip 20 via link VDD [i], node n [i], ne, nc and na and conducting to signal end GND.So, the excessively electrically stress wave between signal end ZAP to GND just can be applied between signal pin sp to power supply pin Vdd, as shown in aspect 34a.
Step 912: to carry out excessively electrically stress test for another signal pin and another power supply pin, then step 906 is repeated to 908 to this signal pin and this power supply pin.For example, if a certain signal pin sp2 (not being shown in figure) is connected to link S [(j2-1) * Nb+k2], the power supply pin (not shown) of its correspondence is connected to link VDD [i2], then can make in step 906 inductive switch sw6 [i2], sw8a [j2] and sw8b [j2, k2] closed, other each switch sw6 [i] (i equals 1 to Nv but is not equal to i2), sw8a [j] (j equals 1 to Na but is not equal to j2) and/or each switch sw8b [j, k] (j equals 1 to Na but is not equal to j2, k equals 1 to Nb but is not equal to k2) then open a way, switch sw6b also opens a way.If without signal/power supply pin to be tested, then can step 912 be proceeded to.
Step 912: process ends 900.
The explanation of continuity Fig. 3, please refer to Figure 20 and Figure 21; What Figure 20 illustrated being one of them flow process 1000 of according to one embodiment of the invention, each signal pin being carried out to excessively electrically stress test; Carry out step 108 time, comparatron 10 can carry out the excessively electrically stress test of aspect 34b (Fig. 1) to certain measured signal pin position of chip 20 and certain power supply pin according to flow process 1000, such as say it is that excessively electrically stress for power supply pin Vdd to signal pin sp is tested, as shown in figure 21.The key step of flow process 1000 can be described as follows:
Step 1002: make all switch open in switch arrays 12, then make switch swa and swb close conducting.
Step 1004: make switch sw2 and sw4 close conducting.
Step 1006: because want the excessively electrically stress of testing power supply pin position Vdd to signal pin sp, and signal pin sp and power supply pin Vdd is connected respectively and holds S [(j-1) * Nb+k] and link VDD [i], therefore switch sw8a [j] and the sw8b [j of link S [(j-1) * Nb+k] correspondence can be made, k] conducting, and make switch sw6 [i] conducting that link VDD [i] is corresponding.
Step 10010: make signal generator 24 be fed to the test waveform of excessively electrically stress between signal end ZAP and GND.Namely what Figure 21 illustrated is the situation of carrying out step 1006 and 10010 for the power supply pin Vdd of link VDD [i] and the signal pin sp of link S [(j-1) * Nb+k].Closed switch swb, sw2 and sw6 [i] by signal end ZAP from node nb conducting to node nd, ne, n [i] and even link VDD [i] and power supply pin Vdd.Moreover closed switch sw8b [j, k], then by signal pin sp, from link S [(j-1) * Nb+k], conducting is to node p [j], tc, nc and na, and even signal end GND for sw8a [j], sw4 and swa.Therefore, the excessively electrically stress wave between signal end ZAP to GND just can be applied between power supply pin Vdd to signal pin sp, as shown in aspect 34b.
Step 1010: to test for another group power supply pin/signal pin, then step 1006 and 10010 is repeated to this group power supply pin/signal pin.If without power supply pin/signal pin that other is to be measured, then proceed to step 1012.
Step 1012: process ends 1000.
Because each switch in switch arrays 12 (comprises switch swa, swb, sw1 to sw4, sw6 [1] to sw6 [Nv], sw7 [1] to sw7 [Nv], sw6b, sw7b, sw8a [1] to sw8a [Na], sw8b [1,1] to sw8b [Na, Nb]) conducting and not conducting all can be controlled by on-off controller 14, therefore comparatron 10 automatically can carry out flow process 100 according to process control.In one embodiment, the interface 28 of on-off controller 14 is accepted the process control instruction of numeral by the digital test channel of a tester table (such as saying it is measure board 26), this digital process steering order can be rendered as digital test mode (testpattern).
Equivalence, comparatron 10 is when carrying out flow process 200 and/or 300, and it operates on a switching channel check pattern, to check the switch sw1 to sw4 in commutation circuit 30.When carrying out flow process 400, comparatron 10 operates on switch checking mode, to check that each switch sw6 [1] is to sw6 [Nv], sw6b and sw7 [1] to sw7 [Nv], sw7b.When carrying out flow process 500 and/or 600, comparatron 10 operates on continuity check pattern, checks that each signal pin is to grounding leg position and/or the signal continuity to power supply pin.When comparatron 10 carries out flow process 700,800,900 and/or 1000, it operates on excessively electrically stress test pattern.
In summary, comparatron 10 of the present invention realizes the robotization excessively electrically stress test to chip 20 with switch arrays 12, and switch arrays 12 have the function (as flow process 200,300 and 400) of self-examination still further.Comparatron 10 is also integrated with the current-voltage measurement function measuring board 26.Comparatron 10 also can be recycled and reused for the different types of chip 20 of test; For example, as long as change slot 18 and the circuit board 16 of comparatron 10, the chip of another kind of pin position configuration can just be tested with same switch arrays 12.So, the cost of chip testing can just significantly be reduced.The test that comparatron 10 can carry out variation, can plan for the chip of high pin number (high pin count), to meet different testing requirements.Comparatron 10 of the present invention also can avoid the mistake of manual testing, and effectively reduces the test duration of high pin number chip.The self-examination function of switch arrays 12 can confirm whether each switch can normal operation before and after excessively electrical stress test.Comparatron 10 first can carry out the continuity check (as flow process 500 and/or 600) of current/voltage before excessively electrical stress test to each signal pin, to guarantee that excessively electrically stress test is effective (namely each signal pin is normal before excessively electrical stress test).After excessively electrical stress test, comparatron 10 can carry out continuity check once again, to check whether the continuity of each signal pin goes to pot because of the applying of excessively electrical stress, just can learn that whether each signal pin is by excessively electrical stress test accordingly.The check result of continuity check also can be automatically recorded using the use as analysis.
In sum, although the present invention with preferred embodiment disclose as above, so itself and be not used to limit the present invention.Persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is when being as the criterion depending on the appended right person of defining.
Claims (15)
1. a comparatron, tests a chip; This comparatron comprises:
One first link and one second link, respectively in order to couple the bipod position of this chip;
One news source, in order to couple a signal generator;
One first measuring junction and one second measuring junction, in order to couple a measurement board;
One commutation circuit, there is one first front side end, one the 4th front side end, one first rear side end and one the 4th rear side end, this first front side end and the 4th front side end couple this news source, and this first rear side end and the 4th rear side end couple this first link and this second link respectively; This commutation circuit controls the conducting between this first front side end and this first rear side end, and controls the conducting between the 4th front side end and the 4th rear side end;
One the 5th switch, be coupled between the 4th rear side end and this first measuring junction, optionally conducting is between the 4th rear side end and this first measuring junction; And
One the 7th switch, be coupled between this first link and this second measuring junction, optionally conducting is between this first link and this second measuring junction;
Wherein, this comparatron operates on a checking mode and a test pattern; When this comparatron operates on this checking mode, the 5th switch conduction; When this comparatron operates on this test pattern, the 5th switch and the 7th switch neither conducting.
2. comparatron according to claim 1, also operates on one second checking mode; When this comparatron operates on this checking mode, the 7th switch conduction; When this comparatron operates on this second checking mode, the conducting between this first front side end and this first rear side end of this commutation circuit, and conducting between the 4th front side end and the 4th rear side end.
3. comparatron according to claim 1, also comprises:
One the 6th switch, be coupled between this first rear side end and this first link, optionally conducting is between this first rear side end and this first link.
4. comparatron according to claim 3, also operates on one second checking mode; When this comparatron operates on this checking mode, the 6th switch conduction; When this comparatron operates on this second checking mode, the conducting between the first front side end and the first rear side end of this commutation circuit, and conducting between the 4th front side end and the 4th rear side end.
5. comparatron according to claim 1, also comprises:
One news source switch, be coupled between this news source and this first front side end, optionally conducting is between this news source and this first front side end;
Wherein, this first front side end also couples the 4th front side end; When this comparatron operates on this checking mode, this news source switch not conducting; When this comparatron operates on this test pattern, this news source switch conducting.
6. comparatron according to claim 1, also comprises:
One the 8th switch, is coupled between the 4th rear side end and this second link, and optionally conducting is in the 4th rear side end and this second link;
Wherein, when this comparatron operates on this test pattern, the 8th switch conduction.
7. comparatron according to claim 1, also comprises one second news source, in order to couple this signal generator; Wherein, this commutation circuit also has one second front side end, one the 3rd front side end, one second rear side end and one the 3rd rear side end, this second front side end and the 3rd front side end couple this and second interrogate source, and this second rear side end and the 3rd rear side end couple this first link and this second link respectively; This commutation circuit also controls the conducting between this second front side end and this second rear side end, and controls the conducting between the 3rd front side end and the 3rd rear side end.
8. comparatron according to claim 7, wherein, when this comparatron operates on this checking mode, this commutation circuit operates on one first switch mode and one second switch mode; When this commutation circuit operates on this first switch mode, the not conducting between this second front side end and this second rear side end of this commutation circuit, not conducting between the 3rd front side end and the 3rd rear side end; When this commutation circuit operates on this second switch mode, the not conducting between this first front side end and this first rear side end of this commutation circuit, also not conducting between the 4th front side end and the 4th rear side end.
9. comparatron according to claim 7, also operates on one second checking mode; When this comparatron operates on this second checking mode, the conducting between this first front side end and this first rear side end of this commutation circuit, also conducting between the 4th front side end and the 4th rear side end.
10. comparatron according to claim 7, also operates on one the 3rd checking mode; When this comparatron operates on the 3rd checking mode, this commutation circuit is between this first front side end and this first rear side end, between this second front side end and this second rear side end, between the 3rd front side end and the 3rd rear side end and neither conducting between the 4th front side end and the 4th rear side end.
11. 1 kinds of methods for a comparatron, this comparatron in order to test a chip, and is provided with one first link, one second link, news source, one first measuring junction, one second measuring junction and a commutation circuit; Wherein, this news source is in order to couple a signal generator, this first link and this second link are respectively in order to couple the bipod position of this chip, this first measuring junction and this second measuring junction are in order to couple a measurement board, commutation circuit has one first front side end, one the 4th front side end, one first rear side end and one the 4th rear side end, this first front side end couples the 4th front side end and this news source, and this first rear side end and the 4th rear side end couple this first link and this second link respectively; This commutation circuit controls the conducting between this first front side end and this first rear side end, and controls the conducting between the 4th front side end and the 4th rear side end; And the method comprises:
By this first measuring junction conducting to the 4th rear side end, by this second measuring junction conducting to this first rear side end, and make not conducting between this news source and this first front side end, to check the function of this commutation circuit.
12. methods according to claim 11, also comprise:
Make the not conducting between this first front side end and this first rear side end of this commutation circuit, also not conducting between the 4th front side end and the 4th rear side end, to check the continuity of this bipod interdigit.
13. methods according to claim 11, wherein this comparatron also comprises one the 6th switch and one the 7th switch; 6th switch is coupled between this first rear side end and this first link, and optionally conducting is between this first rear side end and this first link; 7th switch is coupled between this second measuring junction and this first link, and optionally conducting is between this second measuring junction and this first link; And the method also comprises:
Use this commutation circuit to make this first front side end conducting to this first rear side end, make the 4th front side end conducting to the 4th rear side end, and make this news source and this first front side end not conducting, to check the 6th switch and the 7th switch.
14. methods according to claim 13, wherein, this comparatron also has one second news source, couple this signal generator, and this commutation circuit also has one second front side end, one the 3rd front side end, one second rear side end and one the 3rd rear side end, this second front side end and the 3rd front side end couple this and second interrogate source, and this second rear side end and the 3rd rear side end couple this first link and this second link respectively; This commutation circuit also controls the conducting between this second front side end and this second rear side end, and controls the conducting between the 3rd front side end and the 3rd rear side end; And the method also comprises:
Make the 7th switch not conducting, make the 6th switch conduction, this commutation circuit is used to make this first front side end and this first rear side end conducting, make this second front side end and this second rear side end not conducting, make the 4th front side end and the 4th rear side end not conducting, make the 3rd front side end and the 3rd rear side end conducting, with make this news source and this second interrogate source and be coupled to this bipod position via this first link and this second link respectively.
15. methods according to claim 14, also comprise:
Make the 7th switch not conducting, make the 6th switch conduction, this commutation circuit is used to make this first front side end and this first rear side end not conducting, make this second front side end and this second rear side end conducting, make the 4th front side end and the 4th rear side end conducting, make the 3rd front side end and the 3rd rear side end not conducting, with make this news source and this second interrogate source and be coupled to this bipod position via this second link and this first link respectively.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110344374.1A CN103091618B (en) | 2011-11-03 | 2011-11-03 | Electronic test system and related method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201110344374.1A CN103091618B (en) | 2011-11-03 | 2011-11-03 | Electronic test system and related method |
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| CN103091618A CN103091618A (en) | 2013-05-08 |
| CN103091618B true CN103091618B (en) | 2015-03-11 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP3239864B2 (en) * | 1998-12-07 | 2001-12-17 | 日本電気株式会社 | Test board for power / GND terminal continuity test |
| US6392432B1 (en) * | 2000-06-26 | 2002-05-21 | Advanced Micro Devices, Inc. | Automated protection of IC devices from EOS (electro over stress) damage due to an undesired DC transient |
| US6807507B2 (en) * | 2001-11-27 | 2004-10-19 | Vasudevan Seshadhri Kumar | Electrical over stress (EOS) monitor |
| JP3701954B2 (en) * | 2003-07-08 | 2005-10-05 | 松下電器産業株式会社 | Semiconductor integrated circuit, electrostatic withstand voltage test method and apparatus thereof |
| TW200721064A (en) * | 2005-11-29 | 2007-06-01 | Novatek Microelectronics Corp | Timing controller chip |
| TWI304476B (en) * | 2006-08-04 | 2008-12-21 | Asustek Comp Inc | Electrostatic discharge test apparatus and method thereof |
| CN100590439C (en) * | 2006-08-10 | 2010-02-17 | 华硕电脑股份有限公司 | Electrostatic discharge detection device and method |
| JP4853395B2 (en) * | 2007-06-18 | 2012-01-11 | 横河電機株式会社 | Interface circuit for semiconductor test equipment |
| WO2009024172A1 (en) * | 2007-08-22 | 2009-02-26 | Verigy (Singapore) Pte. Ltd. | Chip tester, chip test system, chip test setup, method for identifying an open-line failure and computer program |
| CN101839948B (en) * | 2009-03-20 | 2012-07-18 | 北京京东方光电科技有限公司 | Sharp pulse detection method, sharp pulse detection device and assembling device of LCD panel |
| US8238068B2 (en) * | 2009-04-24 | 2012-08-07 | Silicon Laboratories Inc. | Electrical over-stress detection circuit |
| US8045306B2 (en) * | 2009-10-16 | 2011-10-25 | Himax Technologies Limited | Electrical-overstress protection circuit for an integrated circuit |
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