JP4853395B2 - Interface circuit for semiconductor test equipment - Google Patents

Description

  The present invention relates to an interface circuit of a semiconductor test apparatus, and more particularly to a means for reducing the influence on measurement of an electrostatic discharge protection element.

  An interface circuit for a device under test (hereinafter referred to as a DUT) of a semiconductor test apparatus includes a driver that supplies a test pattern to the DUT, a DC characteristic test unit that performs a DC parametric test, and a connection to the DUT depending on the test item. Consists of output relay, force relay, sense relay, etc. that switch to test unit.

  With the recent increase in the speed of DUT, components used in semiconductor test equipment such as drivers have adopted finer process rules corresponding to the higher speed, and the withstand voltage has decreased. For this reason, it is necessary to mount a circuit for the purpose of protection from electrostatic discharge (hereinafter referred to as ESD) at the device interface portion that is cut off from the outside.

  In addition, as the transmission speed of test patterns becomes several Gbps, switches with excellent frequency characteristics are required for output relays and force relays that are directly connected to test signal lines (hereinafter referred to as signal lines). Due to the recent trend of switches that support high frequency, there is a tendency to use switches (hereinafter referred to as MEMS switches) using MEMS (Micro electro mechanical systems) technology for output relays and force relays.

However, since MEMS switches generally control connection / release of switches by electrostatic force, they are particularly vulnerable to ESD and are liable to cause malfunctions and damage. Therefore, ESD protection circuits protect output relays and force relays. In addition, it is necessary to mount on the interface portion of the printed circuit board closer to the DUT than the output relay.

  FIG. 2 is a circuit diagram showing a first conventional example of an interface circuit of a semiconductor test apparatus using a diode as an ESD protection circuit. In the case of a function test, a test pattern test signal output from the driver 3 is applied to the DUT via the output terminal 2 with the output relay 4 closed and the force relay 6 and the sense relay 7 open.

In the case of a DC parametric test, a test signal is supplied from the DC characteristic test unit 5 to the DUT via the force relay 6 and the output terminal 2 with the output relay 4 open, the force relay 6 and the sense relay 7 closed. Then, the measurement signal from the DUT is detected by the DC characteristic test unit 5 via the output terminal 2, the resistor 8 and the sense relay 7.

  Diodes 9 and 10 are mounted between the signal line and the power supplies Vcc and Vee. By clamping with the power supply voltage, internal circuits such as the MEMS switch (output relay 4 and force relay 6) are protected from ESD. Yes.

FIG. 3 is a circuit diagram showing a second conventional example in which a Zener diode is mounted between a signal line and a ground terminal (hereinafter referred to as GND) to form an ESD protection circuit. The Zener diode 11 suppresses the upper limit of the positive ESD voltage with the Zener voltage, and suppresses the negative ESD voltage to the GND level.

FIG. 4 is a circuit diagram showing a third conventional example in which an ESD protection circuit is formed by mounting a varistor between a signal line and GND. The upper limit of the positive and negative ESD voltages is suppressed to a constant level by the varistor 12.

  Prior art documents related to ESD protection technology for semiconductor test equipment include the following.

JP 2006-329994 A

  However, the test pattern transmitted from the driver also becomes a high-speed signal due to the high-speed DUT, and the capacitance between terminals of the ESD protection element such as a diode lowers the transmission characteristics of the signal line. Even when a Zener diode or varistor having excellent high frequency characteristics is selected, the capacitance between terminals is generally 1 pF or more, and when the transmission characteristics are several hundred MHz to several GHz, the influence on the transmission characteristics cannot be ignored. .

  In recent years, a dedicated ESD protection element whose inter-terminal capacitance is less than 1 pF has been developed in response to the increase in the speed of semiconductors. However, in a semiconductor test apparatus, not only the influence on the transmission characteristics due to the capacitance between terminals of the ESD protection element but also the influence of the leakage current of the ESD protection element on the DC parametric test cannot be ignored.

  An object of the present invention is to solve such a problem. An interface of a semiconductor test apparatus capable of protecting an internal circuit of a semiconductor test apparatus from ESD using an ESD protection element and maintaining the accuracy of a DC parametric test. The purpose is to realize a circuit.

In order to achieve such a problem, the invention according to claim 1 of the present invention is:
A plurality of test signal sources are respectively connected to output terminals via a plurality of relays, and the output terminals are connected to a DUT and an electrostatic discharge protection element is connected between the reference potential and the relays according to test items. In the interface circuit of the semiconductor test apparatus for switching the test signal source and connecting to the output terminal by controlling
A break contact switch connected in series with the electrostatic discharge protection element is provided between the output terminal and the reference potential.

The invention according to claim 2
The interface circuit of the semiconductor test apparatus according to claim 1,
The driver and the output terminal are connected via an output relay,
The DC characteristic test unit and the output terminal are connected via a force relay and a sense relay,
The break contact switch is opened in synchronization with control signals of the force relay and the sense relay.

The invention described in claim 3
In the interface circuit of the semiconductor test apparatus according to claim 1 or 2,
The reference potential is a ground potential.

The invention according to claim 4
In the interface circuit of the semiconductor test apparatus according to claim 1 or 2,
The reference potential is a power supply voltage.

  As is apparent from the above description, according to the present invention, a plurality of test signal sources are connected to output terminals via a plurality of relays, respectively, and the output terminals are connected to the DUT and between the reference potential. In an interface circuit of a semiconductor test apparatus that is connected to the output terminal by switching the test signal source by controlling the relay according to a test item, the electrostatic discharge protection element is connected to the output terminal and the reference potential Is provided with a break contact switch connected in series with the electrostatic discharge protection element, thereby opening the break contact switch and disconnecting the electrostatic discharge protection element. Semiconductor test that protects the internal circuit of semiconductor test equipment from electrostatic discharge and can maintain the accuracy of DC parametric tests It is possible to realize the interface circuit location.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a configuration circuit diagram showing an example of an interface circuit of a semiconductor test apparatus according to an embodiment of the present invention. The same parts as those in FIGS. 2 to 4 are denoted by the same symbols. The driver 3 inputs a test pattern signal from the semiconductor test apparatus main body via the input terminal 1 and outputs the test pattern test signal toward the DUT. The output relay 4 switches connection / disconnection of the signal line between the output terminal of the driver 3 and the output terminal 2 connected to the DUT.

The DC characteristic test unit 5 outputs a test signal for performing a DC parametric test on the DUT, and measures a measurement signal from the corresponding DUT. The force relay 6 is connected between the force line from the DC characteristic test unit 5 and the output terminal 2, and is controlled by a force relay control signal S1. The sense relay 7 is connected between the sense line of the DC characteristic test unit 5 and the output terminal 2 via a sense resistor 8 and is controlled by a sense relay control signal S2.

The ESD protection element 13 includes a Zener diode, a varistor, or a dedicated ESD protection element, and protects an internal circuit (component) of the semiconductor test apparatus from ESD. A series circuit of the ESD protection element 13 and the break contact switch 14 is connected between the output terminal 2 and GND. The break contact switch 14 opens when operated (the current stops flowing), and is opened in a non-energized state. A force relay control signal S1 and a sense relay control signal S2 are input to the OR gate 15, and the opening and closing of the break contact switch 14 is controlled by the OR output of both signals. Here, the GND potential constitutes a reference potential. The driver 3 and the DC characteristic test unit 5 constitute a plurality of test signal sources, and the force relay 6 and the sense relay 7 switch a plurality of test signal sources according to the test item and connect to the output terminal 2. Configure.

Note that the device interface unit of the semiconductor test apparatus constitutes a single system by mounting a plurality of printed circuit boards on which a plurality of the interface circuits are mounted.

Further, the ESD protection circuit is mounted on the interface portion (near the output terminal) of the printed circuit board closer to the DUT than the output relay in order to protect the output relay and the force relay made up of the MEMS switches.

The operation of the apparatus of FIG. 1 will be described below.
Since the break contact switch 14 is closed when no power is supplied, the ESD protection element 13 connected to the signal line is connected to GND, and the ESD received by the signal line from the outside with respect to the GND by the clamp voltage of the ESD protection element 13 The internal circuit of the output relay 4, the force relay 6, and other semiconductor test equipment is protected by clamping.

In the case of a function test, the output relay 4 is closed, the force relay 6 and the sense relay 7 are open, a test pattern signal is given via the input terminal 1, and a test pattern test signal output from the driver 3 is output. The signal is supplied to the DUT through the relay 4 and the output terminal 2. Also in this case, the ESD contact element 13 connected to the signal line is connected to the GND by the break contact switch 14 that is in the connection state at the initial setting, and the ESD received by the signal line from the outside is set to the GND by the clamp voltage of the ESD protection element 13 Clamping is performed to protect the output relay 4, the force relay 6, and other internal circuits of the semiconductor test apparatus, which are MEMS switches.

In the case of the DC parametric test, the output relay 4 is opened, the force relay 6 and the sense relay 7 are closed, and a test signal is supplied from the DC characteristic test unit 5 to the DUT via the force relay 6 and the output terminal 2. A measurement signal from the DUT is detected via the output terminal 2, the resistor 8 and the sense relay 7. The signals output from the OR gate 15 by the force relay control signal S1 and the sense relay control signal S2 for closing the force relay 6 and the sense relay 7 respectively open the break contact switch 14. That is, since the break contact switch 14 is opened in synchronization with the control signal of the force relay or the sense relay, during the DC parametric test, the ESD protection element 13 is disconnected from the GND, and when the break contact switch 14 is closed, the ESD The leakage current flowing from the signal line to the GND by the protection element 13 does not occur. Therefore, accurate DC parametric test results can be obtained without being affected by the leakage current.

According to the interface circuit of the semiconductor test apparatus configured as described above, by opening the break contact switch when the DC parametric test is performed, the leakage current generated by the ESD protection element is cut off and the DC parametric test can be performed with high accuracy. I can do it.

In addition, by using a break contact switch that is closed (connected) in the initial state, the ESD protection element is connected to the GND plane even when there is no power supply, and it also protects against ESD that occurs when the operator touches it. be able to.

Further, by synchronizing the opening control of the break contact switch 14 with the connection control signals S1 and S2 of the force relay 6 and the sense relay 7, it is not necessary to add a new control signal, so that the number of control signal lines can be increased. However, it can be realized with a simple configuration.

In addition to the DUT DC parametric test, the contact test for confirming that the DUT and the semiconductor test apparatus are electrically connected correctly, and the self for confirming whether the DC level of the test pattern supplied by the driver is correct. Even during diagnosis and self-calibration, measurement and calibration can be performed without being affected by leakage current by opening the break contact switch 14 and disconnecting the ESD protection circuit.

Also, not only when blocking leakage to the GND due to the ESD protection element, but also when using a diode with a large leakage current (FIG. 2), a break contact switch is connected between the ESD protection element and the power source. Leakage current may be prevented. In this case, the power supply voltage constitutes the reference potential.

Further, a break contact switch 14 may be connected between the output terminal 2 and the ESD protection element.

1 is a configuration circuit diagram showing an example of an interface circuit of a semiconductor test apparatus according to an embodiment of the present invention. It is a circuit diagram which shows the 1st prior art example of the interface circuit of a semiconductor test apparatus. It is a circuit diagram which shows the 2nd prior art example of the interface circuit of a semiconductor test apparatus. It is a circuit diagram which shows the 3rd prior art example of the interface circuit of a semiconductor test apparatus.

Explanation of symbols

2 Output terminal 3 Driver 4 Output relay 5 DC characteristic test unit 6 Force relay 7 Sense relay 13 Electrostatic discharge protection element 14 Break contact switch

Claims (4)

A plurality of test signal sources are respectively connected to output terminals via a plurality of relays, and the output terminals are connected to a DUT and an electrostatic discharge protection element is connected between the reference potential and the relays according to test items. In the interface circuit of the semiconductor test apparatus for switching the test signal source and connecting to the output terminal by controlling
An interface circuit of a semiconductor test apparatus, comprising a break contact switch connected in series with the electrostatic discharge protection element between the output terminal and the reference potential. The driver and the output terminal are connected via an output relay,
The DC characteristic test unit and the output terminal are connected via a force relay and a sense relay,
2. The interface circuit of the semiconductor test apparatus according to claim 1, wherein the break contact switch is opened in synchronization with control signals of the force relay and the sense relay. 3. The interface circuit of the semiconductor test apparatus according to claim 1, wherein the reference potential is a ground potential. 3. The interface circuit of the semiconductor test apparatus according to claim 1, wherein the reference potential is a power supply voltage.

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