JP2013140075A - Test circuit and tester - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform ESD protection at low cost without deteriorating a signal waveform.SOLUTION: A tester that tests devices under test comprises: pattern generation units that generate test signals which are to be supplied to the devices under test; and test circuits that output the test signals to the devices under test. The test circuits comprise: an interface unit that performs at least either the signal output to the devices under test or the signal input from the devices under test; a transmission line that is connected to the interface unit and performs transmission of signals to/from the devices under test; an electrostatic protection unit that protects the interface unit from static electricity passing through the transmission line; and a normally-off semiconductor switch that is connected between the transmission line and the electrostatic protection unit.

Description

  The present invention relates to a test circuit and a test apparatus.

A test apparatus for testing a semiconductor or the like includes an electronic circuit having a driver and a comparator for transmitting and receiving signals to and from a device under test. This electronic circuit is provided with an ESD countermeasure by providing an ESD (Electrostatic Discharge) suppressor or a mechanical relay.
Patent Document 1 International Publication No. 2007/043482 Pamphlet

  However, when inputting and outputting a high-speed test signal, the method of providing an ESD suppressor has deteriorated the signal waveform due to the capacitance component connected to the transmission line. In addition, the method of providing the mechanical relay has increased the cost.

  In a first aspect of the present invention, a test circuit for transmitting a signal to and from the device under test in testing the device under test, the signal output to the device under test and the signal input from the device under test An interface unit that performs at least one of the following: a transmission line that is connected to the interface unit and transmits a signal to and from the device under test; and an electrostatic protection unit that protects the interface unit from static electricity flowing in the transmission line There are provided a test circuit including a normally-off semiconductor switch connected between the transmission line and the electrostatic protection unit, and a test apparatus including such a test circuit.

  According to a second aspect of the present invention, there is provided an interface circuit that is connected to or disconnected from an external electronic device and transmits a signal to and from the electronic device in a state where the electronic device is connected, An interface unit that performs at least one of signal output and signal input from the electronic device, a transmission line that is connected to the interface unit and transmits a signal to and from the electronic device, and static electricity that flows through the transmission line An interface circuit comprising: an electrostatic protection unit that protects a part; and a normally-off semiconductor switch connected between the transmission line and the electrostatic protection unit.

  It should be noted that the above summary of the invention does not enumerate all the necessary features of the present invention. In addition, a sub-combination of these feature groups can also be an invention.

1 shows a configuration of a test apparatus 10 according to the present embodiment. The structure of the input-output part 24 which concerns on this embodiment is shown. The other structural example of the input-output part 24 which concerns on this embodiment is shown. Still another configuration example of the input / output unit 24 according to the present embodiment will be described.

  Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. In addition, not all the combinations of features described in the embodiments are essential for the solving means of the invention.

  FIG. 1 shows a configuration of a test apparatus 10 according to the present embodiment. The test apparatus 10 inputs / outputs signals to / from the device under test to test the device under test. The test apparatus 10 is connected to a device under test via a cable and a performance board. Prior to the test, the device under test is attached to the socket on the performance board of the test apparatus 10 by the handler device. The device under test is removed from the socket by the handler device after the test is completed.

  The test apparatus 10 includes one or a plurality of test modules 20. Each of the one or more test modules 20 is incorporated in a housing (for example, a test head). In such a test apparatus 10, as an example, ESD may occur when the test module 20 is incorporated in the housing and when the handler apparatus attaches or removes the device under test.

  Each test module 20 includes a pattern generation unit 22, an input / output unit 24, a determination unit 26, a DC test unit 28, and a control unit 30. The pattern generator 22 generates a test signal supplied to the device under test and an expected value output from the device under test.

  The input / output unit 24 transmits signals to and from the device under test in testing the device under test. More specifically, the input / output unit 24 supplies the test signal output from the pattern generation unit 22 to the device under test. Further, the input / output unit 24 acquires a response signal output from the device under test in response to the supply of the test signal. The determination unit 26 compares the logical value of the response signal acquired by the input / output unit 24 with the expected value to determine pass / fail of the device under test.

  The DC test unit 28 generates a DC voltage having a designated value when a DC voltage is supplied to the device under test for testing. The DC voltage generated from the DC test unit 28 is supplied to the device under test via the input / output unit 24. The control unit 30 sets parameters and controls operations for the pattern generation unit 22, the input / output unit 24, the determination unit 26 and the DC test unit 28.

  FIG. 2 shows a configuration of the input / output unit 24 according to the present embodiment. The input / output unit 24 includes an interface unit 32, a terminal 34, a transmission line 36, an electrostatic protection unit 38, and a semiconductor switch 40.

  The interface unit 32 performs at least one of signal output to the device under test and signal input from the device under test. In the present embodiment, the interface unit 32 includes a driver unit 52 and a comparator unit 54. The driver unit 52 supplies the test signal output from the pattern generation unit 22 to the device under test via the transmission line 36. The comparator unit 54 receives the response signal output from the device under test via the transmission line 36 and outputs the logical value of the response signal.

  The terminal 34 is connected to the device under test via a cable or the like. The transmission line 36 is a line that electrically connects the terminal 34 connected to the device under test and the interface unit 32. The transmission line 36 transmits a signal exchanged between the interface unit 32 and the device under test.

  The electrostatic protection unit 38 protects the interface unit 32 from static electricity flowing through the transmission line 36. The electrostatic protection unit 38 includes, as an example, a capacitor 56 that is provided between the transmission line 36 and the ground and charges static electricity flowing through the transmission line 36. The capacitor 56 can accumulate static charges flowing in the transmission line 36 and prevent the interface unit 32 from being electrostatically destroyed.

  The semiconductor switch 40 is connected between the transmission line 36 and the electrostatic protection unit 38. The semiconductor switch 40 switches between an on (connected) state or an off (disconnected) state between the transmission line 36 and the electrostatic protection unit 38 in accordance with a control signal supplied from the control unit 30.

  As an example, the semiconductor switch 40 is an optical semiconductor relay that connects or disconnects the transmission line 36 and the electrostatic protection unit 38 according to an optical signal. More specifically, the optical semiconductor relay is an optical MOS (Metal Oxide Semiconductor) relay. In the present embodiment, one end of the capacitor 56 in the electrostatic protection unit 38 is connected to the ground. Then, the semiconductor switch 40 switches between the transmission line 36 and the end of the capacitor 56 that is not connected to the ground, in an on state or an off state.

  When the control unit 30 supplies a test signal from the interface unit 32 to the device under test for testing, the control unit 30 turns off the semiconductor switch 40. Thereby, the semiconductor switch 40 can eliminate the capacitance component connected to the transmission line 36 and reduce the deterioration of the waveform of the signal transmitted to the transmission line 36.

  Further, the DC test unit 28 is connected between the semiconductor switch 40 and the electrostatic protection unit 38. Therefore, a DC voltage generated by the DC test unit 28 is applied between the semiconductor switch 40 and the electrostatic protection unit 38. Then, the control unit 30 turns on the semiconductor switch 40 when the DC test unit 28 supplies a DC voltage to the device under test for testing. Thereby, the semiconductor switch 40 is turned on when the DC test unit 28 supplies a voltage to the device under test, and the DC voltage output from the DC test unit 28 is transmitted to the device under test via the transmission line 36. Can be supplied with.

  The semiconductor switch 40 is a normally-off switch. In other words, the semiconductor switch 40 is a switch that is in an off (disconnected) state when no control signal is supplied. Accordingly, the semiconductor switch 40 is in an off state before or after the start of the test and in a state where no power is applied to the test apparatus 10.

  Here, in the off state, the semiconductor switch 40 has a breakdown voltage that is higher than the maximum voltage of a signal transmitted to the device under test and lower than the withstand voltage of the interface unit 32. For example, if the maximum voltage of a signal transmitted to the device under test is 30V and the withstand voltage of the interface unit 32 is 300V, the semiconductor switch 40 has a breakdown voltage higher than 30V and lower than 300V.

  Such a semiconductor switch 40 can limit the voltage of the transmission line 36 to the breakdown voltage or less in the OFF state. Thereby, the electrostatic protection unit 38 and the semiconductor switch 40 can protect the interface unit 32 without applying a voltage higher than the breakdown voltage to the interface unit 32. In addition, since the breakdown voltage in the OFF state of the semiconductor switch 40 is higher than the maximum voltage of the signal transmitted to the device under test, the electrostatic protection unit 38 transmits the signal transmitted to the device under test. Can be prevented from flowing to the side.

  In addition, the off-capacitance of the semiconductor switch 40 is preferably small. The input / output unit 24 can reduce the influence on the signal transmitted to the transmission line 36 as the off-capacitance of the semiconductor switch 40 is smaller. For example, the semiconductor switch 40 has an off capacitance smaller than that of the electrostatic protection unit 38.

  Further, the input / output unit 24 may have a function of releasing the charge accumulated in the electrostatic protection unit 38 to the ground. As a result, the input / output unit 24 can reliably accumulate charges in the electrostatic protection unit 38 when static electricity is applied to the transmission line 36.

  As described above, according to the test apparatus 10 according to the present embodiment, since the semiconductor switch 40 (for example, an optical MOS relay) is provided, an internal circuit can be protected against ESD at a low cost. Further, according to the test apparatus 10 according to the present embodiment, when a signal is transmitted between the interface unit 32 and the device under test, the semiconductor switch 40 is turned off, so that a capacitance component is present in the transmission line 36. Without being connected, the deterioration of the signal waveform can be reduced.

  FIG. 3 shows another configuration example of the input / output unit 24 according to the present embodiment. In the present embodiment, the input / output unit 24 may further include an inductor 62.

  The inductor 62 is connected between the semiconductor switch 40 and the transmission line 36. As an example, the inductor 62 is a ferrite bead inductor. The ferrite bead inductor has a dominant resistance component compared to the inductance component in the high frequency region, and has a dominant inductance component compared to the resistance component in the low frequency region.

  More specifically, the inductor 62 has a dominant inductance component compared to the resistance component in a band lower than the frequency band of the test signal (low frequency band), and the frequency region (high frequency region) of the frequency band of the test signal. The resistance component is dominant in comparison with the inductance component. Thus, the inductor 62 can be in a state in which the resistance component is eliminated when the DC voltage is applied, and the resistance component is connected in the application of the test signal.

  In addition, the electrostatic protection unit 38 may include an ESD suppressor 64 that discharges static electricity to the ground instead of the capacitor 56. For example, the ESD suppressor 64 is provided between the semiconductor switch 40 and the ground. By including the ESD suppressor 64, the electrostatic protection unit 38 can more reliably discharge static electricity generated in the transmission line 36 to the ground.

  FIG. 4 shows still another configuration example of the input / output unit 24 according to the present embodiment. Further, the electrostatic protection unit 38 may include a capacitor 56 and an ESD suppressor 64. In this case, the capacitor 56 and the ESD suppressor 64 are connected in parallel and are provided between the semiconductor switch 40 and the ground. Even if comprised in this way, the electrostatic protection part 38 can discharge the static electricity which generate | occur | produces in the transmission line 36 to a ground more reliably.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

  The order of execution of each process such as operations, procedures, steps, and stages in the apparatus, system, program, and method shown in the claims, the description, and the drawings is particularly “before” or “prior to”. It should be noted that the output can be realized in any order unless the output of the previous process is used in the subsequent process. Regarding the operation flow in the claims, the description, and the drawings, even if it is described using “first”, “next”, etc. for convenience, it means that it is essential to carry out in this order. It is not a thing.

DESCRIPTION OF SYMBOLS 10 Test apparatus 20 Test module 22 Pattern generation part 24 Input / output part 26 Determination part 28 DC test part 30 Control part 32 Interface part 34 Terminal 36 Transmission line 38 Electrostatic protection part 40 Semiconductor switch 52 Driver part 54 Comparator part 56 Capacitor 62 Inductor 64 ESD suppressor

Claims (10)

A test circuit for transmitting a signal to and from the device under test in the test of the device under test,
An interface unit for performing at least one of signal output to the device under test and signal input from the device under test;
A transmission line connected to the interface unit for transmitting signals to and from the device under test;
An electrostatic protection unit for protecting the interface unit from static electricity flowing in the transmission line;
A normally-off semiconductor switch connected between the transmission line and the electrostatic protection unit;
A test circuit comprising:   The test circuit according to claim 1, wherein the semiconductor switch has an off-capacitance smaller than a capacitance of the electrostatic protection unit.   The test circuit according to claim 1, wherein the semiconductor switch has a breakdown voltage that is higher than a maximum voltage of a signal transmitted to the device under test and lower than a withstand voltage of the interface unit.   The test circuit according to claim 1, further comprising an inductor connected between the semiconductor switch and the transmission line.   5. The test circuit according to claim 1, wherein the semiconductor switch is an optical semiconductor relay that connects or disconnects between the transmission line and the electrostatic protection unit according to an optical signal. 6. A DC test unit connected between the semiconductor switch and the electrostatic protection unit, and supplying a specified voltage to the device under test via the semiconductor switch;
The test circuit according to claim 1, wherein the semiconductor switch is switched on when the DC test unit supplies a voltage to the device under test.   The test circuit according to claim 1, wherein the electrostatic protection unit includes a capacitor that charges static electricity.   The test circuit according to claim 1, wherein the electrostatic protection unit includes an ESD suppressor that discharges static electricity to the ground. A test apparatus for testing a device under test,
A pattern generator for generating a test signal to be supplied to the device under test;
The test circuit according to any one of claims 1 to 8, wherein the test signal is output to the device under test.
A test apparatus comprising: An interface circuit that transmits or receives a signal to or from the electronic device in a state where the electronic device is connected or disconnected from an external electronic device;
An interface unit that performs at least one of signal output to the electronic device and signal input from the electronic device;
A transmission line connected to the interface unit and transmitting signals to and from the electronic device;
An electrostatic protection unit for protecting the interface unit from static electricity flowing in the transmission line;
A normally-off semiconductor switch connected between the transmission line and the electrostatic protection unit;
An interface circuit comprising:

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