JPS61225825A - Ｉｃ実装構造 - Google Patents

Ｉｃ実装構造

Info

Publication number
JPS61225825A
JPS61225825A JP60067588A JP6758885A JPS61225825A JP S61225825 A JPS61225825 A JP S61225825A JP 60067588 A JP60067588 A JP 60067588A JP 6758885 A JP6758885 A JP 6758885A JP S61225825 A JPS61225825 A JP S61225825A
Authority
JP
Japan
Prior art keywords
ics
mounting structure
face
wiring conductor
wiring conductors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60067588A
Other languages
English (en)
Inventor
Osamu Motosawa
本沢　修
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP60067588A priority Critical patent/JPS61225825A/ja
Publication of JPS61225825A publication Critical patent/JPS61225825A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はＩＣの回路基板への取付方法に関する〔発明の
概要〕 本発明はＩＯの回路基板への取り付は方法に関し、配線
導体を１箇所以上共有化し、且つＩＣ能動面を向い合わ
せに配置、接合することにより工Ｃ取り付けを同時に行
うことができる為、量産化、高密度化に寄与するもので
ある。
〔従来の技術〕
従来の工ａ実装構造は第３図及び第４図である。第３図
は従来のワイヤーボンディング構造であり、７は工０，
８は回路基板でありガラエボ銅張積層板である。１０は
ボンディングワイヤー、６はモールド剤である。また第
４図は従来のテープキャリア方式によるＸａ実装構造で
ある。１はバンプ付工０．４は回路基材でありポリイミ
ド材が多く用いられる。３は２、配線導体よりのびたフ
ィンガ一部である。
〔発明が解決しようとする問題点及び目的〕しかし、前
述の従来技術では多数のＩＣを取り付は様とする場合に
は回路基板平面サイズが大きくなってしまう。またＸａ
を取り付ける作業工数として非常に大・きな損失となっ
てしまう問題点がある。そこで本発明はこのような問題
点を解決するもので、その目的とするところは、小型な
高密度実装回路ブロックを提供するところにある。
〔問題点を解決するための手段〕
本発明の工０実装構造は工Ｃ実装構造に於いて配線導体
を１箇所以上共有化し、且つＩＣ能動面を向い合わせに
配置、接合することを特徴とする〔実施例〕 以下、本発明について実施例に基づいて詳細に説明する
。
第１図は本発明のＩＣ実装断面図である。１はバンプ何
重０，２は配線導体、３は２配線溝体よりのびた平らな
フィンガ一部、４は回路基材、材質は主にポリイミドが
用いられる。５はＩＣに具備されたパンダである。バン
プ材質としては金。
半田等が用いられる。実装方式としては一方のＩＣをギ
ヤグボンディング後、他のＩＯをフェースダウン法にて
実装する形態。又は画工Ｃを同時にフェースダウン法等
にて実装する形態等、種々の方法がある。
第２図は本発明による工Ｃ実装構造の他の例である。１
はバンプ何重０，２は配線導体、９は２の配線導体より
のびた突出部を有するフィンガ一部で、上の工Ｃ１と下
の工Ｃ７とのフィンガ一部は異なるものとなっている。
５は工Ｃに具備されたバンプ、７はバンプ無工Ｃ！、　
６はモールド剤、８は回路基材、材質は主にガラスエポ
キシ系である。７のバンプ無工Ｃは５のフィンガー突出
部ニより実装される。該実装後、１．バンプ何重Ｃはフ
ェースダウン法等により共通化する配線導体（３、突出
部を有するフィンガ一部）に実装される。
また、７のバンプ無ＩＣの裏面（能動面の反対側）の断
面的位置は、第２図に示す通り、８の回路基材面と同一
面、又は回路基材内に収納することができる。
尚ここに挙げた実施例はあくまでも一実施例にすぎない
ものである。
〔発明の効果〕
以上述べたように本発明によれば、回路基板パターンを
沢山引き出すことな（、Ｒ，ＯＭ　、　ＲＡＭ等のパス
ラインを共通化可能となり、高密度実装に対応できる効
果を有する。また、工Ｃを２コ向い合せに用いる為、Ｎ
チャンネルＩＣ１ＰチヤンネルエＣを作成後、配線導体
を用いて接続すれば、１ｍ！−ＭＯ８−工Ｃが簡単に作
成できるという効果もある。
【図面の簡単な説明】
第１図は本発明のＩＣ実装断面図、第２図は本発明の他
の一例の工Ｃ実装断面図である。第５図は従来のワイヤ
ーボンディングによるＩＣ実装断面図。第４図は従来の
ギヤグボンディングによるＩＯ実装構造断面図である。 １・・・・・・バンプ付ＩＣ ２・・・・・・回路基材に接合された配線導体５・・・
・・・配線導体よりのびた平らなフィンガ一部４・・・
・・・回路基材（材質は主にポリイミド系）５・・・・
・・工Ｃに具備されたバンプ６°°°°°°モールド剤 ７ｅ・・・・・バンプ無工Ｃ ８・・・・・・回路基材（材質は主にガラスエポキシ系
９・・・・・・配線導体よりのびた突出部を有するフィ
ンガ一部 １０・・・・・・ボンディングワイヤー以上

Claims (1)

    【特許請求の範囲】
  1. ＩＣ実装構造に於いて配線導体を１箇所以上共有化し、
    且つＩＣ能動面を向い合わせに配置接合することを特徴
    とするＩＣ実装構造。
JP60067588A 1985-03-29 1985-03-29 Ｉｃ実装構造 Pending JPS61225825A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60067588A JPS61225825A (ja) 1985-03-29 1985-03-29 Ｉｃ実装構造

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60067588A JPS61225825A (ja) 1985-03-29 1985-03-29 Ｉｃ実装構造

Publications (1)

Publication Number Publication Date
JPS61225825A true JPS61225825A (ja) 1986-10-07

Family

ID=13349220

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60067588A Pending JPS61225825A (ja) 1985-03-29 1985-03-29 Ｉｃ実装構造

Country Status (1)

Country Link
JP (1) JPS61225825A (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5313367A (en) * 1990-06-26 1994-05-17 Seiko Epson Corporation Semiconductor device having a multilayer interconnection structure
JPH06232327A (ja) * 1993-02-01 1994-08-19 Nec Corp フレキシブルプリンティングサーキットテープとこれを用いた半導体装置用パッケージ

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5313367A (en) * 1990-06-26 1994-05-17 Seiko Epson Corporation Semiconductor device having a multilayer interconnection structure
JPH06232327A (ja) * 1993-02-01 1994-08-19 Nec Corp フレキシブルプリンティングサーキットテープとこれを用いた半導体装置用パッケージ

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