JPH1022315A - 電子回路の形成方法 - Google Patents

電子回路の形成方法

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Publication number
JPH1022315A
JPH1022315A JP17458496A JP17458496A JPH1022315A JP H1022315 A JPH1022315 A JP H1022315A JP 17458496 A JP17458496 A JP 17458496A JP 17458496 A JP17458496 A JP 17458496A JP H1022315 A JPH1022315 A JP H1022315A
Authority
JP
Japan
Prior art keywords
substrate
jig
bumps
components
positioning
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17458496A
Other languages
English (en)
Inventor
Takamichi Suzuki
高道 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
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Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP17458496A priority Critical patent/JPH1022315A/ja
Publication of JPH1022315A publication Critical patent/JPH1022315A/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
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    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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    • H01L2224/4805—Shape
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    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
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    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8512—Aligning
    • H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
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  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】 【課題】従来構造では回路基板の種類に対応して異なっ
た治具を１品種当たり相当枚数準備しなければならず、
治具の製作費用が莫大である。 【解決手段】基板２上の搭載部品が載置される位置の周
囲に、ワイヤボンダによりワイヤバンプ法により突起５
を形成する。あるいは耐熱性の樹脂をディスペンサで塗
布して固化し突起を形成し、これを位置決め用の土手と
して用いる。

Description

【発明の詳細な説明】
【０００１】
【発明の属する技術分野】本発明は電子回路の形成方法
に関する。
【０００２】
【従来の技術】従来は図４，図５に示したように基板１
４上に搭載する部品１６の配置に対応した孔１５を持つ
治具１３を乗せ、治具１３の開口した孔１５に、接続用
の板状はんだ４並びに搭載部品１６を挿入し位置合わせ
する。これをリフロー炉に投入し、はんだ４を溶融して
基板と搭載部品１６を結合させる。更にこれらをベース
となる基板１４に更に搭載する場合はもう１度同様の治
具１３を用いて同じ作業を行う。
【０００３】
【発明が解決しようとする課題】しかし上記の従来方法
には以下述べる問題がある。
【０００４】上記の方法は、回路基板の種類に対応して
異なった治具を１品種当たり相当枚数準備しなければな
らず、治具の製作費用が莫大である。したがって、回路
基板の設計変更をしたくても容易に変更することはでき
ない。また、治具は、はんだ付け工程を通過するため再
使用に当たって洗浄しなければならず工数，費用がかか
る。更にリフロー炉も治具を含めて加熱するため回路基
板単体の場合に比べ遥かに熱容量の大きい炉としなけれ
ばならず、設備投資額，ランニング費用とも多大にな
る。
【０００５】本発明の目的は、安価且つ、フレキシブル
な回路基板の製造方法を提供することにある。
【０００６】
【課題を解決するための手段】上記の課題を解決するた
めに、基板上の搭載部品が載置される位置の周囲に、ワ
イヤボンダによりワイヤバンプを形成するあるいは耐熱
性の樹脂をディスペンサで塗布して突起を形成し、これ
を位置決め用の土手として用いる。これにより位置決め
用の治具を用いる必要が無くなる。
【０００７】
【発明の実施の形態】図１から図３に実施の形態を示
す。図２に図１の半導体チップ６の搭載部分の断面を示
す。ベース１は銅などの放熱性の良い材料からなる。基
板は、たとえば、アルナミ基板２のように伝熱性の良い
且つ電気的絶縁性の良い材料に銅箔３を接着したものな
どを用いる。銅箔３の付いたアルミナ基板２は、はんだ
４を介してベース１との間で金属結合されている。半導
体チップ６はアルミナ基板２の上にはんだ４を介して同
様に金属結合されている。この構造で、ベース１及びア
ルミナ基板２の上面には突起５が形成されている。突起
５は、ワイヤボンダによって金，アルミなどの材料で形
成している。図１はモジュールの平面図である。突起５
はアルミナ基板２の周囲を基板の位置ずれを生じないよ
うに複数点形成されている。同様に、半導体チップ６の
周囲もチップにずれが生じないように突起５が形成され
ている。
【０００８】図３は本発明の方式をＩＧＢＴモジュール
に適用した例を示す。ベース１上のアルミナ基板２に搭
載された半導体チップ６は、金やアルミ線のワイヤ７で
ワイヤボンディングによって電気的に接続される。更
に、アルミナ基板２上の配線パターンとも同様の方法で
接続される。この配線パターン上には端子ブロック１２
と一体となった端子８がはんだ付けされており、外部と
の入出力端子となっている。モジュールはケース９に収
納された形で内部にゲル１０を充填し、ハードレジン１
１で封止した構造となっている。
【０００９】本実施例で、ワイヤボンダによるバンプの
形成に変えて、熱硬化性の樹脂をディスペンサによって
供給し固化することによって突起５を形成しても良い。
【００１０】
【発明の効果】本発明の方式によれば部品を順次積層す
る過程で、専用の位置決め治具を用いる必要が無く、任
意の位置に位置決めの基準となる凸部を形成することが
できる。
【００１１】これにより製品ごとに専用で且つ高価な治
具を用いず、ソフトウェアのデータを準備するだけで搭
載部品を位置決めする凸部を安価且つ容易に形成する事
ができる。また、熱容量の大きな治具を用いないので、
はんだの大型のリフロー炉が必要ないまたは同じ炉で従
来に比べ大量に処理することが可能となる。また、品種
交換ごとに部品の熱容量の違いに対応して温度プロファ
イルやコンベア速度などのプロセス条件を変更する必要
も少なくすることができ作業工数も大幅に低減できる。
【図面の簡単な説明】
【図１】本発明を適用した電子回路形成における搭載部
品の平面図。
【図２】本発明を適用した電子回路形成における搭載部
品の断面図。
【図３】本発明を適用したＩＧＢＴモジュールの断面
図。
【図４】従来方式による搭載部品の位置決め方法におけ
る治具の平面図。
【図５】従来方式による搭載部品の位置決め方法におけ
る治具の断面図。
【符号の説明】
１…ベース、２…アルミナ基板、３…銅箔、５…突起、
６…半導体チップ、７…ワイヤ。

Claims (4)

    【特許請求の範囲】
  1. 【請求項１】母体となる基板を用意し、用意した上記基
    板上の所定の位置に基板または電子部品などの搭載部品
    を搭載し上記基板と上記搭載部品を接合固定する電子回
    路の形成方法において、上記母体となる上記基板の所定
    位置に突起を形成し、これをガイドとして上記搭載部品
    を上記基板上の所定の位置に搭載し接合することを特徴
    とする電子回路の形成方法。
  2. 【請求項２】請求項１において、位置決め用の突起をワ
    イヤバンプ法によって形成する電子回路の形成方法。
  3. 【請求項３】請求項１において、位置決め用の突起を樹
    脂によって形成した電子回路の形成方法。
  4. 【請求項４】請求項１の方法によって形成した電子回
    路。
JP17458496A 1996-07-04 1996-07-04 電子回路の形成方法 Pending JPH1022315A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17458496A JPH1022315A (ja) 1996-07-04 1996-07-04 電子回路の形成方法

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017069401A (ja) * 2015-09-30 2017-04-06 日亜化学工業株式会社 基板及び発光装置、並びに発光装置の製造方法
CN106920791A (zh) * 2015-12-21 2017-07-04 斯坦雷电气株式会社 半导体发光装置及半导体发光装置的制造方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017069401A (ja) * 2015-09-30 2017-04-06 日亜化学工業株式会社 基板及び発光装置、並びに発光装置の製造方法
CN106920791A (zh) * 2015-12-21 2017-07-04 斯坦雷电气株式会社 半导体发光装置及半导体发光装置的制造方法
CN106920791B (zh) * 2015-12-21 2021-12-28 斯坦雷电气株式会社 半导体发光装置及半导体发光装置的制造方法

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