JPS61224037A - 多ビツト入力演算素子を用いた演算方式 - Google Patents

多ビツト入力演算素子を用いた演算方式

Info

Publication number
JPS61224037A
JPS61224037A JP60065664A JP6566485A JPS61224037A JP S61224037 A JPS61224037 A JP S61224037A JP 60065664 A JP60065664 A JP 60065664A JP 6566485 A JP6566485 A JP 6566485A JP S61224037 A JPS61224037 A JP S61224037A
Authority
JP
Japan
Prior art keywords
input
bit
arithmetic
arithmetic element
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60065664A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0424728B2 (enrdf_load_stackoverflow
Inventor
Shinichi Maki
新一 牧
Kiichi Matsuda
松田 喜一
Toshihiro Honma
敏弘 本間
Yutaka Fukuda
福田 裕
Takeshi Okazaki
健 岡崎
Takashi Ito
隆 伊藤
Osamu Kawai
修 川井
Toshitaka Tsuda
俊隆 津田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP60065664A priority Critical patent/JPS61224037A/ja
Publication of JPS61224037A publication Critical patent/JPS61224037A/ja
Publication of JPH0424728B2 publication Critical patent/JPH0424728B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50Adding; Subtracting
    • G06F7/505Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804Details
    • G06F2207/3808Details concerning the type of numbers or the way they are handled
    • G06F2207/3812Devices capable of handling different types of numbers
    • G06F2207/3816Accepting numbers of variable word length
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804Details
    • G06F2207/386Special constructional features
    • G06F2207/388Skewing

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
JP60065664A 1985-03-29 1985-03-29 多ビツト入力演算素子を用いた演算方式 Granted JPS61224037A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60065664A JPS61224037A (ja) 1985-03-29 1985-03-29 多ビツト入力演算素子を用いた演算方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60065664A JPS61224037A (ja) 1985-03-29 1985-03-29 多ビツト入力演算素子を用いた演算方式

Publications (2)

Publication Number Publication Date
JPS61224037A true JPS61224037A (ja) 1986-10-04
JPH0424728B2 JPH0424728B2 (enrdf_load_stackoverflow) 1992-04-27

Family

ID=13293483

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60065664A Granted JPS61224037A (ja) 1985-03-29 1985-03-29 多ビツト入力演算素子を用いた演算方式

Country Status (1)

Country Link
JP (1) JPS61224037A (enrdf_load_stackoverflow)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0484219A (ja) * 1990-07-26 1992-03-17 Fujitsu Ltd 演算処理装置及び演算処理方法
JPH05204605A (ja) * 1990-11-15 1993-08-13 Internatl Business Mach Corp <Ibm> データ処理方法及びその装置

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51134539A (en) * 1975-05-01 1976-11-22 Ibm Digital adder

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51134539A (en) * 1975-05-01 1976-11-22 Ibm Digital adder

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0484219A (ja) * 1990-07-26 1992-03-17 Fujitsu Ltd 演算処理装置及び演算処理方法
JPH05204605A (ja) * 1990-11-15 1993-08-13 Internatl Business Mach Corp <Ibm> データ処理方法及びその装置

Also Published As

Publication number Publication date
JPH0424728B2 (enrdf_load_stackoverflow) 1992-04-27

Similar Documents

Publication Publication Date Title
US6692534B1 (en) Specialized booth decoding apparatus
EP0654732B1 (en) Galois field multiplication method and multiplier utilizing the same
JPS595350A (ja) 組合わせ乗算器
JP3637073B2 (ja) 倍精度・単精度・内積演算および複素乗算が可能な乗算器
EP0862110A2 (en) Wallace-tree multipliers using half and full adders
JPS61224037A (ja) 多ビツト入力演算素子を用いた演算方式
US6338135B1 (en) Data processing system and method for performing an arithmetic operation on a plurality of signed data values
JPH0374419B2 (enrdf_load_stackoverflow)
Wang et al. A new redundant binary number to 2's-complement number converter
JPS5957343A (ja) 加算回路
JP3046115B2 (ja) 離散コサイン変換器
JPS6222178A (ja) 2つの複素数の乗算のための乗算器
Brenner et al. Proof of the fundamental theorem of algebra
Sreelakshmi et al. A novel approach to the learning of vinculum numbers in two’s compliment method for BCD arithmetic operations
JPS623330A (ja) 加算器
JP2581534B2 (ja) 演算回路
US3614403A (en) System for converting to a bcd code
JPS62120535A (ja) 並列乗算器
JP3612950B2 (ja) 演算装置およびその方法
Olshanetsky Scattering of clusters in quantum calogero model
JPS6049328B2 (ja) 10進4倍数生成回路
JPS63245517A (ja) デジタル加算回路
KR100234031B1 (ko) 산술 가산기
JPS60136871A (ja) 演算処理装置
JPS6289135A (ja) デイジタル固定小数点乗算器