JPS61206054A - 主記憶制御方式 - Google Patents

主記憶制御方式

Info

Publication number
JPS61206054A
JPS61206054A JP4781685A JP4781685A JPS61206054A JP S61206054 A JPS61206054 A JP S61206054A JP 4781685 A JP4781685 A JP 4781685A JP 4781685 A JP4781685 A JP 4781685A JP S61206054 A JPS61206054 A JP S61206054A
Authority
JP
Japan
Prior art keywords
access
register
emu
throughput
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4781685A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0414371B2 (enrdf_load_stackoverflow
Inventor
Nobuhiko Kuribayashi
栗林　暢彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP4781685A priority Critical patent/JPS61206054A/ja
Publication of JPS61206054A publication Critical patent/JPS61206054A/ja
Publication of JPH0414371B2 publication Critical patent/JPH0414371B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Multi Processors (AREA)
  • Complex Calculations (AREA)
JP4781685A 1985-03-11 1985-03-11 主記憶制御方式 Granted JPS61206054A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4781685A JPS61206054A (ja) 1985-03-11 1985-03-11 主記憶制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4781685A JPS61206054A (ja) 1985-03-11 1985-03-11 主記憶制御方式

Publications (2)

Publication Number Publication Date
JPS61206054A true JPS61206054A (ja) 1986-09-12
JPH0414371B2 JPH0414371B2 (enrdf_load_stackoverflow) 1992-03-12

Family

ID=12785878

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4781685A Granted JPS61206054A (ja) 1985-03-11 1985-03-11 主記憶制御方式

Country Status (1)

Country Link
JP (1) JPS61206054A (enrdf_load_stackoverflow)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59119996A (ja) * 1982-12-25 1984-07-11 Fujitsu Ltd マルチポ−トメモリを用いた時間スイツチ方式

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59119996A (ja) * 1982-12-25 1984-07-11 Fujitsu Ltd マルチポ−トメモリを用いた時間スイツチ方式

Also Published As

Publication number Publication date
JPH0414371B2 (enrdf_load_stackoverflow) 1992-03-12

Similar Documents

Publication Publication Date Title
US5134695A (en) Method and apparatus for constant stride accessing to memories in vector processor
EP0138451B1 (en) Vector data processing system for indirect address instructions
Lim et al. Efficient algorithms for block-cyclic redistribution of arrays
US6954812B2 (en) Two-stage round robin arbitration system
JPS6367705B2 (enrdf_load_stackoverflow)
US4757444A (en) Vector processor capable of performing iterative processing
JPH0752420B2 (ja) 入出力装置アドレス方式
JP4240610B2 (ja) 計算機システム
JPS61206054A (ja) 主記憶制御方式
JPH0214364A (ja) 多次元配列の一次元記憶空間への写像・参照方式
EP0215621B1 (en) Data processing system for processing units having different throughputs
JPS6261131A (ja) 主記憶制御方式
JPS6347866A (ja) 信号制御回路
JP3223530B2 (ja) データ転送命令生成処理方法
EP3953815B1 (en) Computing device and computing system based on said device
JPS616745A (ja) アドレス発生装置
JPH0241778B2 (enrdf_load_stackoverflow)
AU596541B2 (en) Data processing system for processing units having different throughputs
SU1108460A1 (ru) Устройство дл решени дифференциальных уравнений
JPH0456352B2 (enrdf_load_stackoverflow)
JPH04148365A (ja) 組合せ最適化装置
JPS58158755A (ja) メモリ制御装置
JPS63198144A (ja) マルチポ−トメモリにおけるダイレクトメモリアクセス制御方式
Souravlas et al. A message passing strategy for array redistributions in a torus network
JPH0644270B2 (ja) ベクトルプロセッサの制御処理方式