JPH0414371B2 - - Google Patents
Info
- Publication number
- JPH0414371B2 JPH0414371B2 JP60047816A JP4781685A JPH0414371B2 JP H0414371 B2 JPH0414371 B2 JP H0414371B2 JP 60047816 A JP60047816 A JP 60047816A JP 4781685 A JP4781685 A JP 4781685A JP H0414371 B2 JPH0414371 B2 JP H0414371B2
- Authority
- JP
- Japan
- Prior art keywords
- access
- address
- throughput
- register
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Multi Processors (AREA)
- Complex Calculations (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4781685A JPS61206054A (ja) | 1985-03-11 | 1985-03-11 | 主記憶制御方式 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4781685A JPS61206054A (ja) | 1985-03-11 | 1985-03-11 | 主記憶制御方式 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS61206054A JPS61206054A (ja) | 1986-09-12 |
JPH0414371B2 true JPH0414371B2 (enrdf_load_stackoverflow) | 1992-03-12 |
Family
ID=12785878
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4781685A Granted JPS61206054A (ja) | 1985-03-11 | 1985-03-11 | 主記憶制御方式 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61206054A (enrdf_load_stackoverflow) |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59119996A (ja) * | 1982-12-25 | 1984-07-11 | Fujitsu Ltd | マルチポ−トメモリを用いた時間スイツチ方式 |
-
1985
- 1985-03-11 JP JP4781685A patent/JPS61206054A/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS61206054A (ja) | 1986-09-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5134695A (en) | Method and apparatus for constant stride accessing to memories in vector processor | |
US4827403A (en) | Virtual processor techniques in a SIMD multiprocessor array | |
US5155823A (en) | Address generating unit | |
Lim et al. | Efficient algorithms for block-cyclic redistribution of arrays | |
KR950012256A (ko) | 벡터 데이타 처리용 컴퓨터 시스템 및 그 방법 | |
US7305507B2 (en) | Multi-stage round robin arbitration system | |
US4757444A (en) | Vector processor capable of performing iterative processing | |
KR960042420A (ko) | 파라메트릭 곡선 발생 장치 | |
CN110119375A (zh) | 一种将多个标量核链接为单核向量处理阵列的控制方法 | |
JP4240610B2 (ja) | 計算機システム | |
JPS638952A (ja) | メモリのアドレス方法およびこの方法を用いたプロセッサ | |
JPH0414371B2 (enrdf_load_stackoverflow) | ||
JPH0214364A (ja) | 多次元配列の一次元記憶空間への写像・参照方式 | |
JPS60129853A (ja) | アドレス発生装置 | |
Matheson et al. | Analysis of multigrid methods on massively parallel computers: architectural implications | |
JP3223530B2 (ja) | データ転送命令生成処理方法 | |
JPS61262971A (ja) | ベクトルレジスタの構成方式 | |
JPS58158755A (ja) | メモリ制御装置 | |
del Corral et al. | Reducing inter-vector-conflicts in complex memory systems | |
JP2828972B2 (ja) | 並列プロセツサ | |
Smitley et al. | Comparative analysis of hill climbing mapping algorithms | |
JP2000259493A (ja) | メモリアクセスシステム | |
JPS63198144A (ja) | マルチポ−トメモリにおけるダイレクトメモリアクセス制御方式 | |
JP2591362B2 (ja) | データ選択処理方法 | |
JPH04227589A (ja) | データフロープログラムの割付け装置および割付け方法 |