JPH0350298B2 - - Google Patents

Info

Publication number
JPH0350298B2
JPH0350298B2 JP60043205A JP4320585A JPH0350298B2 JP H0350298 B2 JPH0350298 B2 JP H0350298B2 JP 60043205 A JP60043205 A JP 60043205A JP 4320585 A JP4320585 A JP 4320585A JP H0350298 B2 JPH0350298 B2 JP H0350298B2
Authority
JP
Japan
Prior art keywords
access
ports
port
banks
access ports
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60043205A
Other languages
English (en)
Japanese (ja)
Other versions
JPS61202246A (ja
Inventor
Shoji Nakatani
Nobuyuki Sugiura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP60043205A priority Critical patent/JPS61202246A/ja
Publication of JPS61202246A publication Critical patent/JPS61202246A/ja
Publication of JPH0350298B2 publication Critical patent/JPH0350298B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Complex Calculations (AREA)
  • Memory System (AREA)
JP60043205A 1985-03-05 1985-03-05 メモリアクセス制御方式 Granted JPS61202246A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60043205A JPS61202246A (ja) 1985-03-05 1985-03-05 メモリアクセス制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60043205A JPS61202246A (ja) 1985-03-05 1985-03-05 メモリアクセス制御方式

Publications (2)

Publication Number Publication Date
JPS61202246A JPS61202246A (ja) 1986-09-08
JPH0350298B2 true JPH0350298B2 (enrdf_load_stackoverflow) 1991-08-01

Family

ID=12657423

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60043205A Granted JPS61202246A (ja) 1985-03-05 1985-03-05 メモリアクセス制御方式

Country Status (1)

Country Link
JP (1) JPS61202246A (enrdf_load_stackoverflow)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7619139B2 (ja) * 2021-04-16 2025-01-22 株式会社リコー メモリアクセス制御装置

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5757370A (en) * 1980-09-22 1982-04-06 Fujitsu Ltd Access control system

Also Published As

Publication number Publication date
JPS61202246A (ja) 1986-09-08

Similar Documents

Publication Publication Date Title
US4837682A (en) Bus arbitration system and method
US4481572A (en) Multiconfigural computers utilizing a time-shared bus
US5263169A (en) Bus arbitration and resource management for concurrent vector signal processor architecture
US4965718A (en) Data processing system incorporating a memory resident directive for synchronizing multiple tasks among plurality of processing elements by monitoring alternation of semaphore data
US3931613A (en) Data processing system
US4542455A (en) Signal-processing multiprocessor system
JP2761506B2 (ja) 主記憶制御装置
JPS6353678A (ja) ベクトル処理装置
EP0409285B1 (en) Method and apparatus for data transfer between processor elements
US4048623A (en) Data processing system
US4138720A (en) Time-shared, multi-phase memory accessing system
JP2561261B2 (ja) バッファ記憶アクセス方法
US4089052A (en) Data processing system
US6223196B1 (en) Shared mac (multiply accumulate) system and method
JPH0350298B2 (enrdf_load_stackoverflow)
EP0359192B1 (en) Vector processors and vector register control
Siegel et al. Parallel memory system for a partitionable SIMD/MIMD machine
GB2138182A (en) Digital processor
EP3953815B1 (en) Computing device and computing system based on said device
JP2781742B2 (ja) 並列計算機
JP2742245B2 (ja) 並列計算機
Tuomenoksa et al. Preloading Schemes for the PASM Parallel Memory System.
JP2731743B2 (ja) 通信レジスタ付並列計算機
JPH0424843A (ja) メモリアクセス制御装置
JPH06266860A (ja) ベクトル処理プロセッサ

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees