JPS6119543Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a power amplifier circuit that operates with almost the same power efficiency as in class B operation and does not generate switching distortion.

Conventionally, single-ended push-pull (hereinafter abbreviated as SEPP) circuits have been frequently used in audio power amplifier circuits, and class B circuits, which allow a specified idling current to flow, are particularly effective in achieving good power efficiency. A class B SEPP power amplifier circuit biased for operation is employed.

However, in the B-class SEPP power amplifier circuit, the transistors that supply power to the load are different between the positive half-cycle input signal input period and the negative half-cycle input signal input period, if the idling current is ignored. Switching of the transistor is performed in accordance with the switching of the positive and negative half-cycle periods of the input signal, and there is a drawback that switching distortion occurs due to the carrier accumulation effect of the transistor.

The present invention has been developed in consideration of the above, and eliminates the above drawbacks, operates with almost the same power efficiency as class B amplifier operation, and operates in accordance with the switching of the positive and negative half-cycle periods of the input signal. The purpose of this is to provide a power amplifier circuit that prevents transistors from switching and maintains all transistors in the on state even during low impedance loads until high output power is applied, and does not generate switching distortion. The present invention will now be explained by way of examples.

FIG. 1 is a circuit diagram of an embodiment of the present invention.

A power amplifier circuit according to an embodiment of the present invention connects a series circuit of a diode 12, a resistor 6, and a resistor 5 between the emitter of a transistor 1 and the collector of a transistor 2, thereby inverting the transistors 1 and 2. The common connection point of diode 12 and resistor 6 is connected to load 8 through resistor 7, and similarly diode 15, resistor 10, resistor 11 are connected between the emitter of transistor 3 and the collector of transistor 4. The series circuit of transistors 3 and 4 is connected in an inverted Darlington connection, the common connection point of diode 15 and resistor 10 is connected to load 8 through resistor 9, and the base of transistors 1 and 3 is connected. A constant bias voltage is applied to the SEPP power amplifier circuit. Resistors 13 and 14 are further connected to this SEPP power amplifier circuit between the emitter of transistor 1 and the collector of transistor 2, and between the emitter of transistor 1 and the common connection point of resistors 10 and 11, respectively. , and resistors 16 and 17 are respectively connected between the emitter of transistor 3 and the collector of transistor 4 and between the emitter of transistor 3 and a common connection point of resistors 5 and 6, respectively.

Note that +B and -B are positive and negative power supply terminals, respectively, and 18 is a bias circuit. Bias circuit 18 applies a constant voltage bias between the bases of transistors 1 and 3.

Therefore, in the power amplifier circuit according to the embodiment of the present invention described above, when there is no input signal, the bias circuit 18 is configured so that the transistors 1 to 4 can be turned on by the current flowing through the resistors 13, 14, 16, and 17, and the idling current If this is ignored, the bias voltage is set so that class B amplification operation is performed. Therefore, when there is no input signal, transistors 1, 2, 3, and 4 are on, and the current flowing through resistors 7 and 9 is equal to the base-emitter voltage V _BE of transistors 1 and 3 and the on-voltage of diodes 12 and 15. The sum is determined by the voltage subtracted from the bias voltage between transistors 1 and 3.

Next, when a positive half-cycle input signal is applied, the input signal is applied to transistors 1 and 2.
The emitter current of transistor 1 and the collector current of transistor 2 are amplified by resistor 7.
Flows into the load 8 through the power supply and supplies power to the load 8. Therefore, the voltage drop across the resistor 7 increases from the value due to the idling current, and the diode 15 is no longer able to maintain its on voltage, and the diode 15 becomes off. However, with respect to the potential at the common connection point between resistors 6 and 7, the potential at the common connection point between resistors 5 and 6 changes to the + side, the potential at the collector of transistor 4 changes to the - side, and the potential at the common connection point between resistors 16 and 17 changes to the + side.
The emitter potential of transistor 3 rises due to the current flowing through, transistor 3 is maintained in an on state, and transistor 4 is also maintained in an on state.

Now, when the diode 15 is turned off, the resistors 6, 7, 9, 10, 11, 16 and 17 are turned off.
A bridge circuit is constructed as shown in the figure. Since the current flowing through resistors 9, 10, and 11 is small, if resistors 9, 10, and 11 are ignored, the bridge circuit described above becomes a bridge circuit consisting of resistors 6, 7, 16, and 17; 1
If the resistance values of 7 are R ₆ , R ₇ , R ₁₆ and R ₁₇ ,
Between the resistance values of resistors 6, 7, 16 and 17
When set so that the relationship R ₆・R ₁₆ = R ₇・R ₁₇ is established, the above bridge circuit is balanced and the resistance 6
No matter how much the current flowing through resistors 6 and 7 increases,
The voltage between the common connection point of the resistors 6 and 7 and the emitter of the transistor 3 is the same as the voltage between the common connection point of the resistors 6 and 7 and the emitter of the transistor 3 when no signal is input, and there is no change. Therefore, the transistor 3 is in an on state in which the same emitter current as the emitter current of the transistor 3 when no input signal is applied flows through the transistor 3.

Further, even when the relationship R ₆ · R ₁₆ = R ₇ · R ₁₇ does not hold between the resistance values of the resistors 6, 7, 16, and 17, the transistor 3 is maintained in the on state as described above. In this case, the emitter current of the transistor 3 is turned on at a value different from the emitter current of the transistor 3 when no input signal is applied.

The operation when a negative half-cycle input signal is applied is also similar to the above case, and transistors 1 and 2 are maintained in the on state. A detailed explanation thereof will be omitted since it is similar to the above case, but in this case, the input signal is amplified by transistors 3 and 4, and power is supplied to load 8 from transistors 3 and 4. Also, resistors 9, 10,
13 and 14 (resistors 5, 6, and 7 are omitted because the current flowing therein is small) constitute a bridge circuit, and the equilibrium condition is to set the resistance values of resistors 9, 10, 13, and 14 to R ₉ , R ₁₀ , R ₁₃ and R ₁₄ , R ₉ · R ₁₄ = R ₁₀ · R ₁₃ .

Next, when there is no input signal, resistors 5, 6, 7, 9,
Bridge circuit consisting of 10, 13 and 14 and resistors 6, 7, 9, 10, 11, 16 and 17
In the bridge circuit consisting of resistors 5 and 1
_{If the resistance values R 5 and R 11 of ​ ​ ​ 6} +R ₇ +R ₉ ) When each resistance value is set so that the relationship of Improved stability.

As explained above, according to the present invention, regardless of the polarity of the input signal, the magnitude of load impedance, and the magnitude of output power, all transistors do not switch and are always on, causing switching distortion. There isn't.

Moreover, if the idling current of each transistor is ignored, the amplification effect is performed depending on the polarity of the input signal, the transistors that supply power to the load are replaced, and the power efficiency is almost the same as in the case of class B amplification operation.

Furthermore, there is also the effect of improving bias stability.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the present invention. FIG. 2 is a diagram for explaining the operation of an embodiment of the present invention. 1, 2, 3 and 4...transistor, 8...
Load, 12 and 15... Diode, 18...
bias circuit.

Claims (1)

[Scope of utility model registration request] A circuit in which a first diode, a first resistor, and a second resistor are connected in series is connected between the emitter of the first transistor and the collector of the second transistor. Connect the inverted Darlington and connect the first
The common connection point between the diode and the first resistor is connected to the third
A second diode, a fourth resistor and a fifth transistor are connected between the emitter of the third transistor and the collector of the fourth transistor.
The third transistor and the fourth transistor are connected in an inverted Darlington connection by connecting a circuit in which resistors of
A common connection point with the resistor is connected to the load through the sixth resistor, and a constant bias voltage is applied between the bases of the first and third transistors to form a single-ended push-pull power amplifier circuit. Furthermore, the emitter of the first transistor and the second
a seventh resistor between the collector of the transistor; a common connection point between the fourth resistor and the fifth resistor;
An eighth resistor is connected between the emitter of the first transistor, a ninth resistor is connected between the emitter of the third transistor and the collector of the fourth transistor, and an eighth resistor is connected between the emitter of the third transistor and the collector of the fourth transistor. A common connection point with
A power amplifier circuit characterized in that a tenth resistor is connected between the emitter of the third transistor.