JPS6223133Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a power amplifier circuit that performs an amplification operation with power efficiency substantially similar to that of a class B amplification operation and does not generate switching distortion.

Conventionally, for example, as shown in FIG. 1, a transistor 1 and an emitter resistor 3, and a transistor 2 and an emitter resistor 4 are connected in series between positive and negative power supplies +B and -B, and the emitter resistors 3 and 4 are connected in series. In a single-ended push-pull (hereinafter simply abbreviated as SEPP) power amplifier circuit configured by connecting a load 5 with one end grounded to the common connection point, that is, the output terminal A, the output terminal A, the base of the transistor 1, and the base of the transistor 2 are connected. Amplifiers 6 and 7 each having an amplification factor of 1 are provided for inputting the voltage between the base of The bias voltage of transistor 1 is changed by the output of , and the bias voltage of transistor 2 is changed by the output of amplifier 7 according to the change in the input signal in the negative half cycle, and transistors 1 and 2 are always kept in the on state to avoid switching distortion. There is a power amplification circuit designed to prevent this from occurring.

However, in the conventional power amplifier circuit described above, the amplification factors of amplifiers 6 and 7 are set to +1, and the output terminal A
Since the voltage change between the potential of the transistor and the potential of the base of the transistor is positively fed back to the base of the transistor, the bias stability is not good.

The present invention has been made in consideration of the above-mentioned drawbacks, and it is an object of the present invention to provide a power amplifier circuit that eliminates the above-mentioned drawbacks.

The present invention will be explained below with reference to examples.

FIG. 2 is a circuit diagram of a power amplifier circuit according to an embodiment of the present invention. The power amplifier circuit of this embodiment is configured as follows.

In an SEPP power amplifier circuit consisting of transistors 1 and 2, emitter resistors 3 and 4, and a load 5, a series circuit of resistors 8 and 9 is connected between the emitters of transistor 1 and the emitter of transistor 2, and A first voltage is obtained by dividing the potential difference between the emitter of transistor 1 and the emitter of transistor 2 at a common connection point B with transistor 9. On the other hand, A ₁ is a non-inverting amplifier consisting of feedback resistors 14 and 20 and an operational amplifier 10, and A ₂ is a non-inverting amplifier consisting of feedback resistors 15 and 21 and an operational amplifier 11. The first voltage is applied to the non-inverting input terminal of the non-inverting amplifier A ₁ through an input cutoff diode 16, and the voltage at the output terminal A is applied to the inverting input terminal of the non-inverting amplifier A ₁ through a diode 12 and a resistor 14. The configuration is such that the non-inverting amplifier _A1 operates when the voltage at the output terminal A is equal to or lower than the first voltage. Further, the output voltage of the non-inverting amplifier _A1 is applied in series to the bias circuit 18 so as to be superimposed on the voltage of the bias circuit 18, which is a constant voltage circuit connected to the base of the transistor 1. Similarly,
The first voltage is applied to the non-inverting input terminal of the non-inverting amplifier _A2 through an input cutoff diode 17.
The voltage at the output terminal A is applied to the inverting input terminal of the non-inverting amplifier _A2 through the diode 13 and the resistor 15, so that the non-inverting amplifier _A2 operates when the voltage at the output terminal A is higher than the first voltage. Configure. In addition, the output voltage of the non-inverting amplifier A ₂ is determined by the bias circuit 1 consisting of a constant voltage circuit connected to the base of the transistor 2.
It is applied in series to the bias circuit 19 so as to be superimposed on the voltage of 9.

Note that the diodes 12 and 13 are connected to compensate for the forward voltage drop of the input cutoff diodes 16 and 17, and are biased so that current always flows in the forward direction.

The resistance values R 3 and R _{4 of the emitter resistors 3 and 4 are} selected to be equal, and the resistance values R 8 and R 9 of the resistors ₈ and ₉ are selected to be equal.

In the power amplifier circuit of the embodiment configured as described above, when there is no input signal, transistors 1 and 2 are turned on by the voltages of bias circuits 18 and 19, and a predetermined idling current flows through transistors 1 and 2. In this case, output end A
There is no potential difference between the voltage of and the first voltage,
The inputs of non-inverting amplifiers A ₁ and A ₂ are zero.

Next, when a positive half-cycle input signal is applied to the power amplifier circuit of this embodiment, the emitter current of transistor 1 becomes a current obtained by adding the current that amplified the input signal to the idling current, and this increased The emitter current of the transistor 1 flows into the load 5, and generates power in the load 5 by amplifying the input signal.

Now, if the resistance value of the emitter resistor 3 is _R3 , and the increase in the emitter current of the transistor 1 flowing through the emitter resistor 3 is _I3 , then the increase in the voltage drop across the emitter resistor 3 is _R3 · _I3 . Therefore, the first voltage seen from the output terminal A becomes the voltage obtained by dividing the voltage drop R ₃ ·I ₃ of the emitter resistor 3 by the resistors 8, 9, and 4, if the idling current is ignored. Here, resistor 8 and resistor 9 have the same resistance value, and resistor 4
Since the resistance value of is normally a small value, the first voltage seen from the output terminal A becomes I ₃ ·R ₃ /2. Therefore, if the resistance value of load 5 is R _L , the voltage at output terminal A is
I ₃ ·R _L , and the first voltage becomes I ₃ ·R _L +I ₃ ·R ₃ /2 if the idling current is ignored. Therefore, the voltage at the output terminal A is lower than the first voltage, and the input of the non-inverting amplifier A ₁ becomes I ₃ ·R ₃ /2. It is 1/2 of the increase in voltage drop across the emitter resistor 3. Therefore, the output voltage of the non-inverting amplifier A ₁ becomes I ₃ ·R ₃ when the resistance values R 14 and R ₂₀ of the resistors ₁₄ and 20 are set as R ₁₄ =R ₂₀ . Therefore, the voltage of I ₃ ·R ₃ is added to the voltage of the bias circuit 18.

On the other hand, at this time, the input to the non-inverting input terminal of the non-inverting amplifier A ₂ is cut off by the input cut-off diode 17, so the output of A ₂ is the same as when there is no signal, and the bias circuit 19 A voltage is applied and the bias of transistor 2 becomes the same as when there is no signal. Therefore, the increase in the voltage drop across the emitter resistor 3 is compensated for, and the transistors 1 and 2 are never turned off but always operate in the on state.
The idling current value of the transistor 2 in this case is approximately equal to that in the case of no input signal.

Also, if the gains of non-inverting amplifiers A ₁ and A ₂ exceed 2, transistor 1
and 2 bias voltages will increase.

Further, since the operation when a negative half-cycle input signal is applied to the power amplifier circuit of this embodiment is the same as that in the above case, a detailed explanation thereof will be omitted.

In the above embodiments, a case has been described in which the first voltage is obtained by dividing the voltage between the emitters of transistors 1 and 2 using a series circuit of resistors 8 and 9. However, the first voltage is
The voltage between the base of transistor 2 and the base of transistor 2 may be divided, and in this case, it is possible to compensate for changes in the voltage between the base and emitter of transistors 1 and 2 caused by the input signal. You can get better results.

As explained above, according to the present invention, all the transistors operate in an on state at all times during the entire cycle of the input signal regardless of the polarity of the input signal, and no switching occurs, so that switching distortion does not occur.

Further, the transistor that supplies current to the load is switched according to the polarity of the input signal, and the idling current can be set to a small value, so the power efficiency is almost the same as in the case of class B amplification operation.

In addition, the non-inverting amplifier is configured so that its input is balanced when no input signal is applied, and its output is fed back to the input side of the transistor only when an input signal is applied, so the bias stability when no input signal is applied is lower than that of the conventional one. This is an improvement over the case of a power amplifier circuit.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a conventional power amplifier circuit. FIG. 2 is a circuit diagram of a power amplifier circuit according to an embodiment of the present invention. 1 and 2...transistor, 3 and 4...
Emitter resistance, 5...Load, 18 and 19...
Bias circuit, A ₁ and A ₂ ... non-inverting amplifier.

Claims (1)

[Scope of utility model registration request] A first output transistor is biased by a first fixed bias circuit and has its emitter connected to the output terminal through a first resistor, and a first output transistor is biased by a second fixed bias circuit and has its emitter connected to the output terminal through a second resistor. In a single-ended push-pull power amplifier circuit having a second output transistor connected to an output terminal thereof, voltage dividing means divides the voltage between the emitters or bases of the first and second transistors. The divided first voltage is applied to the non-inverting input terminal via the first and second diodes, and the voltage at the output terminal of the single-ended push-pull power amplifier circuit is always biased on. 3. A first non-inverting amplifier that is applied to each inverting input terminal via a fourth diode and operates when the first diode is turned on when the voltage at the output terminal is equal to or lower than the first voltage. and a second non-inverting amplifier that operates by turning on the second diode when the voltage at the output terminal is equal to or higher than the first voltage.
The output voltage of the non-inverting amplifier is superimposed on the voltage of the first fixed bias circuit and fed back to the input side of the first output transistor, and the output voltage of the second non-inverting amplifier is superimposed on the voltage of the first fixed bias circuit. A power amplification circuit characterized in that the power amplification circuit is configured to be superimposed on a voltage and fed back to the input side of a second output transistor.