JPS61154176A - Manufacture of field effect type transistor - Google Patents

Abstract

PURPOSE:To implement low noises and high gain in an FET, by making the thickness of a channel provided in the active layer in the FET thinner along the path from a source electrode to a drain electrode as the drain electrode is approached. CONSTITUTION:A channel 10 is formed in an asymmetrical shape so that the thickness of an active layer 3 becomes thinner toward the side of a drain elec trode 5 from the side of a source electrode 4 as the drain electrode 5 is approached. The minimum thickness is about 1,200Angstrom . In this structure, the source resistance is made lower than the conventional value by about 50%. The gate withstanding voltage can be increased by about twice. The impurity concentration of the active layer 3 is 2-4 X 10<17> cm<-3>, and the gate length is 0.5-1mum.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a field effect transistor that achieves low noise and high gain.

Field effect transistors using gallium arsenide (GaAs) compound semiconductors with high carrier mobility are used as amplifiers used in the microwave frequency band.

Here, the necessary conditions for a transistor are to generate as little noise as possible during use and to obtain a high gain, and there is a desire for a transistor that achieves this to be put into practical use.

[Prior Art] As shown in FIG. 4, the structure of a conventional field effect transistor (hereinafter abbreviated as PET) is such that a buffer layer 2 is formed on a GaAs substrate 1, and an active layer 3 is further formed on the buffer layer 3 by epitaxial growth. is formed, and using this active layer 3, PET
is formed.

In other words, in this example, silicon (S) is used as the donor.
i), the active layer 3 whose impurity concentration was adjusted to 2 to 5XIQ"aJ is removed by etching leaving an IHT formation region of, for example, 200X50μ, and then a source electrode 4 and a drain electrode 5 are patterned. ing.

In this case, ohmic contact is maintained between the active layer 3 and the source and drain electrodes 4.5 by providing a gold-germanium (Au-Ge) alloy layer or the like.

Next, after covering the entire area of the GaAs substrate 1 with a resist, a window is opened in the gate forming region, and in this state, the active layer 3 is recessed by a method such as dry etching, and a channel 6 is formed.

Thereafter, a gate electrode 7 made of metal such as aluminum (^l) is formed in the recessed region by a lift-off method, and the gate electrode 7 is made of metal such as aluminum (^l).
ET has been completed.

Conventionally, when forming the channel 6, the active layer 3 is recessed evenly, so in order to lower the source resistance, it is necessary to form the active layer 3 thickly.However, if the active layer 3 is thick, the pinch-off voltage increases and approaches the gate breakdown voltage.

Another drawback is that if the active layer 3 is thin, the source resistance increases.

[Problem that the invention seeks to solve]

As explained above, it has been difficult to achieve the goals of lowering the source resistance and increasing the gate breakdown voltage in an FET because they are contradictory.

[Means for solving problems]

The above problem can be solved by a method of manufacturing a field effect transistor, which is characterized in that the thickness of the active layer provided on the buffer layer of the semiconductor substrate is gradually reduced from the source electrode to the drain electrode.

[Effect]

The present invention is to form the channel 6 asymmetrically so that it becomes thinner as it goes from the source electrode 4 to the drain electrode 5 as a method of increasing the gate breakdown voltage while keeping the source resistance low. There are two methods: a method of recessing the layer 3 asymmetrically, and a method of providing an asymmetrical depletion layer in the channel 6 from the buffing layer 2.

〔Example〕

FIG. 1 shows how to recess the active layer 3 asymmetrically, so that a patterned layer on the buffer layer 2 with a thickness of approximately 400 nm is shown in FIG.
A resist film 8 is coated over the entire area of the substrate including the active layer 3 to a thickness of about 1 μm by a method such as a spin code method, a window is opened in the gate electrode forming region 9, and dry etching is performed. In this process, as shown in the figure, the substrate is placed obliquely, for example, at an inclination angle of 15 degrees, and directional ion etching such as ion milling or reactive ion etching is performed.

FIG. 2 shows a cross-sectional structure of an FET equipped with a channel 10 formed in this manner, in which the thickness of the active layer 3 decreases from the source electrode 4 side to the drain electrode 5 side. The channel 10 is formed asymmetrically so that there are about 1200 people.

In this way, the source resistance can be lowered by about 50% than in the conventional case, and the gate breakdown voltage can be increased by about twice that in the conventional case.

In this case, the impurity concentration of the active layer 3 is 2 to 4×10
The gate length was 0.5 to 1 .mu.m.

Next, in FIG. 3, a depletion layer 12 is provided in the active layer 11 to form a substantially asymmetric channel.

Here, in order to provide the depletion layer 12 in the active layer 11, a semiconductor layer having a trap source is used as the buffer layer 13.

Specifically, the buffer layer 13 is made of aluminum gallium arsenide (AI, Ga1.lAs, where X≧0.3
) with 5 to 10 x 10 ” silicon (St) elements
It is doped to a concentration of am-1 to make it n-type.

The thickness of the doped layer here is about 200 nm, and the impurity donor is depleted before the drain voltage is applied due to the difference in electron affinity with the substrate level, and becomes a trap source for electrons.

An active layer 11 made of n-type GaAs is formed on this,
Thereafter, the source electrode 4. A drain electrode 5 and a gate electrode 7 are formed.

Here, the channel portion formed under the gate electrode 7 may be formed thinly by recessing as in the conventional method, or the active layer 11 may be used as is as shown in FIG.

In the PET made in this way, the drain electrode 5
When a voltage is applied between the source electrode 4 and the source electrode 4, the accelerating electric field increases as the electrons from the source electrode 4 approach the drain electrode 5, move into the AlGaAs buffer Jila, and are trapped.

When electrons are trapped in the buffer layer 13 in this way, the depletion layer 2 extends from the buffer layer 13 side into the active layer 11 as shown in the figure, and the channel becomes effectively thinner.

Note that since the gate electrode 7 is always used with a reverse bias applied to it, a depletion layer 14 is also formed on the side of the gate electrode ti7, and a channel is formed between these two depletion layers 12 and 14. be done.

Here, the depletion layer 12 extending from the buffer layer 13 is formed in an asymmetrical shape in the direction in which the accelerating electric field increases as shown in the figure, so the channel is thicker on the source electrode 4 side.
Furthermore, since the drain electrode 5 side is formed thin, the source resistance is reduced, while the gate breakdown voltage is improved.

〔Effect of the invention〕

As explained above, in the present invention, the thickness of the channel provided in the active layer of the FET is made thinner as it approaches from the source electrode to the drain electrode, and by implementing the present invention, it is possible to reduce the noise and increase the gain of the PUT. It can be achieved.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view illustrating a method for forming an asymmetrically shaped channel, and FIG. 2 is a P
FIG. 3 is a cross-sectional structural diagram of a PET with a different structure according to the present invention; FIG. 4 is a cross-sectional structural diagram of a conventional FET. In the figure, 1 is a GaAs substrate, 2.13 is a buffer layer,
3.11 is an active layer, 4 is a source electrode, 5 is a drain electrode, 6 and 10 are channels, 7 is a gate electrode, 8 is a resist film, and 12 and 14 are depletion layers.

Claims (3)

[Claims] (1) A method for manufacturing a field effect transistor, characterized in that the thickness of an active layer provided on a buffer layer of a semiconductor substrate is gradually reduced from a source electrode to a drain electrode. (2) A field effect type according to claim 1, characterized in that a gate electrode is provided by performing dry etching in an oblique direction on an active layer having a uniform thickness, and etching the active layer non-uniformly. Method of manufacturing transistors. (3) A buffer layer with a deep trap source is formed on the semiconductor substrate, and a depletion layer is formed in the active layer by trapping electrons in the buffer layer, and the existence of the depletion layer effectively reduces the active layer. A method of manufacturing a field effect transistor according to claim 1, characterized in that the film thickness is reduced.