JPH0385733A - Field effect transistor - Google Patents

Abstract

PURPOSE:To reduce the source resistance and to improve gm to reduce generation of noises by forming an active layer which is thinned as it gets near a drain electrode from a source electrode and by forming it by at least one layer of a shallow N-type layer and a deep P-type layer, respectively. CONSTITUTION:The thickness of an ion implantation N<->-layer 4 is formed thin gradually from a source 5 to a drain 6 to reduce the source resistance and to improve the gate withstand voltage. As for a method to increase sharpness of a carrier concentration profile and to improve gm, a P-layer 7 is formed in parallel below the N<->-layer 4 to compensate for the electrons near the N<->- layer to substrate interface with a P-layer. Thereby, a channel is thick at the side of a source electrode and thin at the side of a drain electrode. Since a carrier concentration profile is sharp, the source resistance lowers while the gate withstand voltage increases, thereby improving gm in comparison with a conventional FET.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a structure that can realize low noise and high gain in a field effect transistor.

(Prior art) Conventional ion implanted field effect transistor (hereinafter referred to as FE)
The structure of GaA (abbreviated as T) is shown in Figure 3.
On the s-substrate 101, an n''M2O3, 103 that makes ohmic contact with the source electrode and the drain electrode,
An n-layer 104, which becomes an active layer, is formed by selective ion implantation and subsequent annealing for activation, and then a source electrode 105, a drain electrode 106, and a gate electrode 107 are provided to obtain an FET.

That is, in this example, Si + ions are implanted,
n+ with impurity concentration ~I x 10111an-”
Ohmic contact is maintained by providing a source electrode 105 and a drain electrode 106 on the layers 102 and 103 using a gold-germanium (Au-Ge) alloy layer.

Next, a gate electrode 107 is formed using a metal such as aluminum (AO) to complete the FET.

If an attempt is made to lower the source resistance for the purpose of improving gain in a conventional FET'a, the steepness of the electron carrier concentration profile decreases because it is necessary to perform ion implantation at high energy and form a thick n-layer 104. As a result, gm also decreases, and rigs with large pinch-off voltage
1 to close to withstand pressure. On the other hand, if the n-layer is formed to be 1.04 thick for the purpose of improving gm, there is a drawback that the source resistance increases.

(Problems to be Solved by the Invention) In FETs with the conventional structure as described above, the demands for lowering the source resistance, increasing the gate withstand voltage, and further improving the gm have been realized because they are in a contradictory relationship with each other. was difficult.

SUMMARY OF THE INVENTION An object of the present invention is to provide an FET that reduces source resistance, improves gm, generates less noise, and provides high gain.

[Structure of the invention]

(Means for Solving the Problems) An FET according to the present invention includes an active layer formed on a semiconductor substrate by selective ion implantation and annealing.
In ET, the active layer is formed to have a smaller thickness as it approaches from the source electrode to the drain electrode, and furthermore, the active layer consists of at least one layer each of a shallow n-type layer and a deep p-type layer. It is characterized by:

(Function) According to the present invention, the channel in the FET is thicker on the source electrode side and thinner on the drain electrode side, and the carrier concentration profile becomes steeper, so the source resistance is lower than in conventional FETs. While the gate voltage decreases, the gate breakdown voltage improves and the GM also improves.

(Example) Hereinafter, one example of the FET of the present invention will be described with reference to the drawings.

As shown in FIG. 1, in order to lower the source resistance and increase the gate breakdown voltage at the same time, the thickness of the ion-implanted layer 4 forming the channel is gradually thinned from the source 5 to the drain 6. As a method of further increasing the steepness of the carrier concentration profile and increasing gm, nine layers 7 are formed in parallel under this n-layer 4.
This can be realized by compensating the electrons near the n-substrate interface with nine layers.

Next, a method for manufacturing the above-described structure of an FET according to the present invention will be explained with reference to FIGS. 2(a) to 2(f) showing the steps in order.

Figure 2 shows a method of forming the FET shown in Figure 1 by changing the thickness of the n-Jl (active layer) 4 from the source to the drain direction. 2
After forming a plasma CVD silicon nitride film 22 with a thickness of 2500 Å on top of the resist 23, a resist 23 is coated using a spin code method.
Then, an opening 23a of the photoresist is provided with a length of μm and a width of the active layer from the surface 26 in contact with the active layer on the source formation region 25 (second
Figure (b)), by etching the silicon nitride film from this opening using an ammonium fluoride/hydrofluoric acid solution (NH,F/14F) 28 at a rate of about 400 Å/min, the area above where the channel is to be formed is etched. The silicon nitride film 22 has a taper angle of about 1
It is formed on a silicon nitride film portion 22a having an inclination of 5° (FIG. 2(C)).

Thereafter, the silicon nitride film portion in the area where the channel is to be formed is covered with a resist 29, and the silicon nitride film other than this area is covered with CF.
4: Remove by O7 plasma etching 210 (FIG. 2(d)). Next, Si + ions 212 with a dose of 3.8 x 10'2 Cm-2 are implanted into the openings of the resist 211 in the regions where the source part, channel part, and drain part of the FET are planned to be formed, with an energy of 50 KeV and 120 KeV (7). An injection layer 24 is provided, and further 180 KeV
dose with energy],.

X 10'2an-''Ile''213 was injected and p
Ion implantation M27 is formed (FIG. 2(e)). After removing the silicon nitride film portion 28 on the active layer by plasma etching with CF4, the silicon oxide film 214 and the resist 21 are removed.
5 as a mask, Si+ ions 218 are selectively implanted into the openings of the source part 216 and the drain part 217 at an energy of 120 KeV and 250 KeV at a dose of 2×1013 m-2, respectively (Fig. 2(f)), and silicon oxide is implanted. Membrane 21
After removing the 4 spacers and the resist 215, annealing is performed at 850° C. for 15 minutes in an AsH3 atmosphere to activate the ion implantation layer. Openings for the source and drain portions are again formed using resist, and Ni/AuGe is vacuum-deposited. Metal is removed from areas other than the source and drain electrode forming regions by lift-off, and alloying is performed at 450° C. for about 2 minutes to obtain ohmic contacts.

A gate pattern is formed using resist, a hole is formed in the spacer oxide film in the area where the gate electrode is to be formed by etching, and AQ is vacuum deposited. Metals other than goo 1 and the electrodes are removed by the lift-off method to complete the FET.

Note that 5 in FIGS. 1 and 2 is a source electrode, and 6 is a source electrode.
8 is a drain electrode, and 8 is a gate electrode.

In this way, the source resistance was lowered by about 50% than the conventional one, the gate breakdown voltage was raised about twice that of the conventional one, and the gm was improved by more than 10%. In addition,
The length of the n-active layer in this case is 2 μm, and the carrier concentration is 500-μm from the GaAs substrate surface on the source side.
At a depth of 1.000 people, it becomes 2X1017cm"-',
On the drain side, about 8 x 10 near the surface of the GaAs substrate.
It was "cw-". Furthermore, the carrier concentration profile became steeper due to the injection of 8e+ (FIG. 4).

The taper angle of the silicon nitride film used for ion implantation of the active layer is
This can be controlled by continuously changing the etching rate of the silicon nitride film in the thickness direction, and can be achieved by continuously changing any of the plasma CVD gas flow rate ratio, chamber pressure, and RF power during film formation. In this example,
The gas flow ratio of plasma CVD is SiH4: NH3:
N2=4:1:15, chamber pressure 1.0To
rr, RF power was 150W, and formation temperature was 300℃, but the gas flow rate ratio was changed to SiH4:Nl(,:N2=
When the ratio is 2.5:1:15, the etching rate is about twice as high as 800 people/min.
By continuously changing the H4 flow rate, the taper angle can be made even smaller, 10° or less, under the same etching conditions.

〔Effect of the invention〕

In FETs made in this way, the channel has a structure that is thick on the source electrode side and thin on the drain electrode side, and the carrier concentration profile is steeper, so the source resistance is lower than in conventional FETs, but the gate The breakdown voltage is increased and the gm is also improved.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of an FET according to an embodiment of the present invention, and FIGS. 2(a) to (f) are FETs shown in FIG. 1.
3 are cross-sectional views showing the manufacturing method in order of steps, FIG. 3 is a cross-sectional view of a conventional FET, and FIG. 4 is a line diagram showing a carrier concentration profile. 1...GaAs substrate (semiconductor substrate) 2.3.4.216.217 Ion implantation layer 4...
N-ion implantation M (active layer) 5... Source electrode 6... Drain electrode 7...
P ion implantation layer 8...Gate electrode 2b...Source/
tangent of the working layer

Claims (2)

[Claims] (1) A field effect transistor comprising an active layer formed on a semiconductor substrate by selective ion implantation and annealing, characterized in that the active layer is formed with a thickness that decreases from the source electrode to the drain electrode. field effect transistor. (2) The field effect transistor according to claim 1, wherein the active layer comprises at least one layer each of a shallow n-type layer and a deep p-type layer.