JPH0897238A - Semiconductor element and its manufacture - Google Patents

Abstract

PURPOSE: To provide a manufacturing method of a semiconductor element wherein the withstand voltage of a Schottky electrode can easily be improved at a low cost, without necessitating complicated process and structure, and the leakage current of the Schottky electrode can be reduced. CONSTITUTION: A source electrode 3 and a drain electrode 4 are formed on an active layer 2 in the upper part of a compound semiconductor substrate 1. By applying plasma treatment to the active layer 2 between the source electrode 3 and the drain electrode 4, a modified layer 2a is formed, on which a Schottky electrode 7a constituting a Schottky junction is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method. In particular, the present invention relates to GaAs MESFE
The present invention relates to a semiconductor element having a Schottky junction electrode such as a field effect transistor such as T or HEMT or a Schottky barrier diode, and a manufacturing method thereof.

[0002]

[Prior art]

(GaAs MESFET) A GaAs Schottky gate field effect transistor (hereinafter referred to as GaAs MESFET) is used as a high-power semiconductor device in a high-frequency band such as a high-frequency amplification device due to its excellent high-frequency characteristics (high speed).

Generally, GaAs MESFETs are Ga
There is a problem that the drain breakdown voltage and the gate breakdown voltage are low due to the influence of high-density surface defect levels existing on the surface of the active layer of the As substrate and the electric field concentration in the active layer immediately below the gate electrode. Especially for high-power GaAs MESFETs, improving the drain breakdown voltage and gate breakdown voltage is
It is indispensable for improving performance such as output power limit and reliability of MESFET.

FIGS. 15A, 15B, and 15C show general Ga.
It is sectional drawing which shows the manufacturing method of AsMESFET71.
In this GaAs MESFET 71, semi-insulating GaAs
By implanting a p-type impurity into the surface of the substrate 40 to form a p-active layer 41, then implanting an n-type impurity into an n-active layer 42, and further implanting an n-type impurity into the source region and the drain region. After forming the n ⁺ active layer 43 on both sides of the n active layer 42 (FIG. 15A), ohmic metal is deposited on the n ⁺ active layer 43 to provide the source electrode 44 and the drain electrode 45 (see FIG. 15). (B)) Further, the gate electrode 47 is provided in the recess 46 formed by etching the n active layer 42 (FIG. 15C).

Thus, n ⁺ is formed in the source and drain regions.
By providing the active layer 43, the electric field in the vicinity of the drain electrode 45 can be lowered and the drain breakdown voltage can be improved. Also, by providing the recess 46,
The drain breakdown voltage and the gate breakdown voltage can be improved by dispersing the electric field concentration near the gate electrode 47 and the drain electrode 45 and lowering the electric field.

However, it cannot be said that the structure shown in FIG. 15C has sufficient withstand voltage. For this reason, especially in high-power GaAs MESFETs, LD
Including improvement of withstand voltage by D (Lightly Doped Drain) structure and multi-step recess structure, tunneling suppression, barrier height improvement, improvement of gate breakdown voltage by various methods such as mitigation of electric field concentration in active layer, reduction of leakage current ,Consideration,
It has been implemented. Specifically, the barrier height is improved by selecting the metal of the gate electrode, and
Examples include improvement of the gate breakdown voltage by applying a special treatment to the interface of the aAs substrate and improvement of the gate breakdown voltage by providing a buffer layer on the active layer of the GaAs substrate.

For example, FIG. 16 shows an LDD structure. In this GaAs MESFET 72 having the LDD structure, the carrier concentration is higher than that of the n ⁺ active layer 43 between the n active layer 42 provided with the gate electrode 47 and the n ⁺ active layer 43 provided with the source and drain electrodes 44 and 45. Small n '
Since the layer 48 is formed, the electric field strength at the interface between the n ⁺ active layer 43 and the n active layer 42 can be prevented from becoming too large, and the drain breakdown voltage and the gate breakdown voltage can be improved.

Further, FIG. 17 shows a structure in which a buffer layer is provided on an active layer of a GaAs substrate, and a surface undoped layer (one layer) 53 is formed on the active layer 52 of the GaAs substrate 51 as a buffer layer. Structure of GaAs MESFE
It is T73.

The GaAs MESFET 73 shown in FIG.
Is manufactured by the following manufacturing process. First, the surface undoped layer 53 is formed on the active layer 52, and the ohmic source electrode 56 and the drain electrode 57 are formed on the GaAs substrate 51 on which the n-type low resistance layer 54 is formed. SiO ₂ is between the drain electrode 57 and the
An oxide film 55 is formed. Next, using the patterned resist film (not shown) as a mask, the oxide film 55 is opened by dry etching, and etching is performed corresponding to the depth of burying the gate. Next, oxide film 55 up to the recess length
Is side-etched, and recess etching is performed to a desired depth. Finally, after vapor deposition of Al / Ti / WSi or the like, lift off is performed to form a gate electrode 58 forming a Schottky junction. In FIG. 17, the gate electrode 58
Is formed on the active layer 52 by penetrating the surface undoped layer 53, but the gate electrode 58 may be formed on the surface undoped layer 53 in some cases.

In the GaAs MESFET 73 having the surface undoped layer 53 as described above, there is no current limit due to channel constriction between the gate and the drain or between the gate and the source, and an effect similar to that of the LDD structure or the multi-step recess structure can be obtained. In addition, the influence of the surface due to the interface state is buffered in the surface undoped layer 53, and the gate breakdown voltage and the like are improved.

However, in the conventional GaAs MESFET having the LDD structure and the multi-step recess structure as described above, the manufacturing process is complicated due to the complicated structure, and the controllability and reliability in the manufacturing process are difficult.
There is a problem that practical application is difficult. Similarly, in the GaAs MESFET 73 as shown in FIG. 17, many complicated steps such as formation of a surface undoped layer, dry etching such as RIE (reactive ion etching), and side etching are required, and the control thereof is difficult. ,
There is a problem that the manufacturing cost becomes high. Further, in any method other than this conventional example, a complicated process and a complicated structure are required.

Among the above-mentioned conventional examples, G shown in FIG.
It is considered that the aAs MESFET 73 has achieved the highest output and the highest efficiency. In this conventional example, as described above, the active layer 52, the surface undoped layer 53, and the n-type low resistance layer 54 are formed using the epitaxial growth technique. When the epitaxial growth technique is used as described above, the surface undoped layer 53 having a high resistance is used as the ohmic electrode (the source electrode 44 or the drain electrode 45) and the active layer 5.
It always exists between 2 and the parasitic resistance in series with the channel increases.

On the other hand, regarding the output of the FET (field effect transistor), the following can be generally said. FIG. 18 is a diagram showing the static characteristics of the FET (drain current Id with respect to the source-drain voltage Vds) and the load line E. FET
18 shows the maximum output power P ₀ max when the class A operation is performed.
The maximum current Imax, knee voltage (knee voltage; voltage of bent portion) Vknee, and breakdown voltage BVds can be expressed by the following equation. P ₀ max = I max (BVds-Vknee) / 8 According to this equation, in order to increase the maximum output P ₀ max, Imax and BVds should be increased and Vknee should be decreased. Generally, in order to increase the maximum current Imax or decrease the knee voltage Vknee, the resistance of the element can be lowered, but on the other hand, there are measures for increasing the breakdown voltage BVds to increase the withstand voltage. It leads to high resistance. Therefore,
These values cannot be independently determined.

In the case of the GaAs MESFET 73 shown in FIG. 17, by inserting the surface undoped layer 53, the breakdown voltage BVds can be increased and the breakdown voltage can be increased.
However, as described above, due to the increase of the resistance component in series with the channel, the maximum current Imax decreases as compared with the case where the surface undoped layer 53 is not inserted, and the knee voltage Vkne
e increases. Therefore, the maximum output P ₀ max cannot be effectively increased. Further, in order to cope with recent portable devices and the like, it is necessary to increase the maximum current Imax and decrease the knee voltage Vknee to reduce the power consumption and the voltage of the device. Therefore, the high breakdown voltage by the GaAs MESFET having the structure as shown in FIG. 17 cannot meet such a demand. Further, although the maximum output has been described here, the efficiency has the same limitation.

(Schottky barrier diode)
There is a Schottky barrier diode as a semiconductor element using a Schottky junction between a semiconductor and a metal. 19 (a) (b) (c) are cross-sectional views showing a method of manufacturing a conventional Schottky barrier diode 74.
An n active layer 62 having a low carrier concentration is formed on the n ⁺ GaAs substrate 61 (FIG. 19A), and a Schottky electrode 63 that forms a Schottky junction with the n active layer 62 is formed on the n active layer 62. (FIG. 19B), n ⁺ GaAs substrate 6
An ohmic electrode 64 is formed on the lower surface of the substrate 1 (see FIG. 1).
9 (c)). Then, a depletion layer is generated under the Schottky electrode 63 to match the Fermi level due to the semiconductor-metal contact, and when a reverse voltage is applied between the Schottky electrode 63 and the ohmic electrode 64, the Schottky electrode 63 A reverse current cannot flow due to the depletion layer immediately below the key electrode 63, and exhibits rectification characteristics.

However, in order to allow the forward current to flow through the Schottky barrier diode 74, the potential barrier of the depletion layer needs to be made sufficiently low. The applied voltage for reducing the potential barrier of the depletion layer all contributes as a forward voltage drop, so that the forward voltage is increased. GaAs Schottky barrier diodes have excellent high frequency characteristics,
For this reason, there is a problem that the forward voltage is large and the power loss is large as compared with the silicon diode.

When a reverse voltage of a certain level or more is applied, avalanche breakdown occurs due to the generation of electron-hole pairs, and the breakdown voltage when the reverse voltage is applied is determined by this avalanche breakdown. In a Schottky barrier diode,
There is a problem that the breakdown voltage is low when the reverse voltage is applied. In order to improve the reverse breakdown voltage, it is sufficient to reduce the impurity concentration of the GaAs substrate, but if the impurity concentration is reduced, the forward current becomes small, which causes a serious problem in the diode characteristics.

[0018]

SUMMARY OF THE INVENTION The present invention has been made in view of the problems of the above conventional examples, and it is an object of the present invention to improve the characteristics of a semiconductor device using a Schottky junction between a semiconductor and a metal. It was done for the purpose. In particular,
The object of the present invention is to solve the problems of the conventional semiconductor device and the like having improved pressure resistance as described above, do not require a complicated process and a complicated structure, and are inexpensive and easily shot. GaAs MES capable of improving the withstand voltage of the key electrode and reducing the leak current of the Schottky electrode
It is to provide a semiconductor element such as an FET and a method for manufacturing the same. Another object of the present invention is to improve the forward current-voltage characteristic or the reverse current-voltage characteristic of a semiconductor element such as a Schottky barrier diode using a Schottky junction.

[0019]

A semiconductor device according to the present invention is a semiconductor device having a Schottky electrode forming a Schottky junction with an active layer formed on a compound semiconductor substrate, wherein the Schottky electrode of the active layer is formed. The modified layer is formed in at least a part of the formed region and its vicinity.

The modified layer is a high resistance layer, and
For example, it can be formed by plasma treatment.

In particular, it is preferable that the modified layer is formed in a region including a region of the active layer where the Schottky electrode is formed.

The semiconductor element may be a field effect transistor element having a Schottky electrode and two ohmic electrodes formed on the active layer.

Alternatively, it may be a Schottky barrier type diode element in which a Schottky electrode is formed on the active layer. In that case, the modified layer can be formed in a region directly below the outer peripheral portion of the Schottky electrode or in a region adjacent to the outer peripheral portion. The modified layer can also be formed in a region directly below the Schottky electrode or in a region smaller than the region directly below the Schottky electrode. Alternatively, the modified layer may be formed in a region directly below the Schottky electrode or in a region larger than the region directly below the Schottky electrode.

The method for manufacturing a semiconductor device according to the present invention is the method for manufacturing a semiconductor device, wherein an active layer is formed on a compound semiconductor substrate, and a Schottky electrode forming a Schottky junction with the active layer is provided. At least a part of a region where a Schottky electrode of the layer is to be formed and its vicinity are subjected to plasma treatment for modification, and then the Schottky electrode is contacted with or adjacent to the modified layer to form the Schottky electrode in the active layer. It is characterized by being formed on top.

In particular, in this manufacturing method, a plasma treatment is applied to a region of the active layer where the Schottky electrode is formed and its vicinity to form a modified layer on the active layer, and then the Schottky layer is formed on the modified layer. It is preferable to form electrodes.

[0026]

According to the present invention, a device of a semiconductor device is provided by providing a modified layer (modified high resistance layer) on an active layer in at least a part of a region where a Schottky electrode is formed and its vicinity. The characteristics could be improved. It is speculated that this is because the modification of the active layer and the surface of the active layer caused a decrease in the carrier concentration and a change in the surface level density in at least a part of the active layer immediately below and near the Schottky electrode. It It is also presumed that the electric field concentration at the end of the Schottky electrode is alleviated.

If the modified layer is formed by subjecting the active layer to plasma treatment, the modified layer can be provided by a simple method. Therefore, the structure of the semiconductor element, the manufacturing process, etc. are not complicated, and the modified layer is simple. The device characteristics can be improved by various means.

For example, in a field effect transistor element in which a modified layer is formed in a region including a region in which an Schottky electrode of an active layer is formed, carrier density is reduced and surface level density is changed. As a result, a thin high resistance layer is formed under the gate electrode, and the influence of the surface level, which is considered to have a great influence on the gate breakdown voltage and the like, can be suppressed. As a result, it is possible to improve the device characteristics such as improving the gate breakdown voltage and reducing the leak current of the gate.

Further, in the Schottky barrier type diode element, if the reforming layer is formed in the region immediately below the outer peripheral portion of the Schottky electrode or in the region adjacent to the outer peripheral portion, electric field concentration at the end of the Schottky electrode is relaxed. Therefore, the reverse characteristic of the diode element can be improved.

Further, in the Schottky barrier type diode element, if the reforming layer is formed in the region directly under the Schottky electrode or in a region smaller than the region directly under the Schottky electrode, the barrier height can be reduced and the forward characteristics of the diode element can be improved. can do.

Further, in the Schottky barrier type diode element, if the reforming layer is formed in a region directly under the Schottky electrode or in a region larger than the region directly under the Schottky electrode, both the forward characteristic and the reverse characteristic of the diode element are improved. can do.

[0032]

Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same parts are designated by the same reference numerals.

(First Embodiment) FIGS. 1A to 1E are sectional views showing a method of manufacturing a GaAs MESFET according to an embodiment of the present invention. First, as shown in FIG.
An active layer 2 (carrier concentration of about 1 × 10 ¹⁷ cm ⁻³ ) is formed on the semiconductor substrate 1 made of semi-insulating GaAs by an ion implantation method or an MBE method. Next, a resist (not shown) is formed on the active layer 2 by photolithography or the like.
After patterning, the Au-Ge / Ni-based metal is evaporated and lifted off to form the source electrode 3 and the drain electrode 4 on the active layer 2, and the source electrode 3 and the drain electrode 4 are formed.
Is heat treated to alloy.

Next, as shown in FIG. 3B, a lower resist film 5 is formed so as to cover the semiconductor substrate 1, the source electrode 3 and the drain electrode 4. Next, a resist is applied again on the lower resist film 5, baked, and then exposed and developed to form an upper resist film 6 having a predetermined pattern. The upper resist film 6 thus formed has a window 8a opened in the gate electrode formation region.

Next, as shown in FIG. 3C, the lower resist film 5 is dry-etched by using the upper resist film 6 as a mask, and a window 8b under the window 8a is slightly wider than the window 8a.
To open. After that, the semiconductor substrate 1 is subjected to plasma treatment (in the figure, the arrow indicates the direction of plasma irradiation) through the windows 8a and 8b. By this plasma treatment, the modified layer 2a is formed on the active layer 2 in the gate electrode formation region and its peripheral portion.
Is formed. Therefore, it is possible to continuously form the modified layer 2a after the dry etching.

This plasma treatment can be carried out using, for example, an RIE device. Further, as the gas species serving as the plasma source, any gas such as O ₂ , N ₂ , Ar, CF ₄ , CHF ₃ , H _{2 and the} like can be used as long as it is a gas serving as the plasma source. Alternatively, a combination of a plurality of these gases may be used.

Next, as shown in FIG.
Recess etching of the modified layer 2a is performed, and then the semiconductor substrate 1 is immersed in 6N-HCl (6N hydrochloric acid) for 1 minute to remove an oxide film (not shown) formed on the surface of the modified layer 2a. After the removal, a metal such as Ti / Pt / Au or Al is vapor-deposited to form the metal film 7.

Finally, as shown in FIG. 6 (e), unnecessary portions of the metal film 7 are removed together with the lower resist film 5 and the upper resist film 6 by lift-off to form a gate electrode 7a in the recess 9, Target GaAs MESFET
Get 31.

As described above, this GaAs MES
A feature of the FET 31 and its manufacturing method is that the modified layer 2a is formed on the active layer 2 by plasma treatment by performing plasma treatment immediately below and in the vicinity of the gate electrode 7a forming a Schottky junction. Therefore, in the above embodiment, the steps other than the plasma treatment step are the same as the conventional steps.

In the above embodiment, the plasma treatment was performed before the recess etching, but the present invention is not limited to this.
After recess etching, plasma treatment is performed, and then the semiconductor substrate is immersed in 6N-HCl (6N hydrochloric acid) for 1 minute to remove the oxide film formed on the surface of the modified layer, and then a gate electrode is formed thereon. You may. Further, it may have a structure in which recess etching is not performed, as shown in FIG.
The structure may be such that the gate electrode is formed without performing the recess etching after removing the oxide film formed on the surface of the modified layer after performing the plasma treatment described in 1. above.

(Measurement result of the first embodiment) In order to investigate the characteristics of the above-mentioned embodiment, O ₂ was used as a gas species serving as a plasma source.
A GaAs MESFET of the above-mentioned embodiment was subjected to plasma treatment by a RIE device using gas under the conditions shown in Table 1.
Was produced.

[0042]

[Table 1]

Further, under the same conditions as in the embodiment except that the plasma treatment was not performed, the Ga of the conventional example was manufactured by the conventional manufacturing method.
An AsMESFET was produced. Then, the gate current Ig was measured when a reverse bias voltage (Vgd = -12V; open source) was applied between the gate and the drain. Also,
The gate-source voltage Vgs was set to 0V, and the gate current Ig was measured when a voltage Vds = 9V was applied between the source and drain. In addition, the GaAsME of both the example and the conventional example
SFET also has a gate length of 0.5 μm and a gate width of 300
μm, recess depth: 0.15 μm. As a result of this measurement, as shown in Table 2, the GaAs MESF of the present example.
In ET, the gate current Ig at the time of applying a reverse bias voltage is about 1/10, which is much smaller than that in the conventional manufacturing method. That is, it can be seen that the gate breakdown voltage is significantly improved. In addition, the gate-source voltage Vgs is 0V
In addition, the gate current Ig when a voltage of Vds = 9V is applied between the source and the drain is also greatly reduced to about 1/50. That is, the GaAs MESFET in which the surface undoped layer is formed on the active layer as shown in FIG. 17 of the conventional example.
It was possible to obtain a gate breakdown voltage equal to or higher than the above.

[0044]

[Table 2]

Further, in the GaAs MESFET of this embodiment, deterioration of element characteristics such as transconductance (g _m ) and cutoff frequency (f _t ) was not observed, and characteristics equivalent to those of the conventional manufacturing method were confirmed.

Further, the same measurement was carried out under the plasma processing conditions with the RF power set to 80 W and the processing time set to 10 minutes. In this case as well, substantially the same effect as that obtained under the conditions shown in Table 1 was confirmed. It was

When the semiconductor substrate 1 is subjected to the plasma treatment in this way, the active layer 2 is reformed, the carrier density immediately below the gate electrode 7a of the active layer 2 and in the vicinity thereof is reduced, and the surface level density is changed. It is presumed that this is caused, and as a result, a thin high resistance layer is formed under the gate electrode 7a,
It is possible to mitigate the influence of the surface level, which is said to have a great influence on the gate breakdown voltage and the like. At the same time, the gate electrode 7
It is possible to reduce the electric field concentration at a and the end of the drain electrode 4. As a result, it is possible to improve the gate breakdown voltage of the GaAs MESFET 31 and to improve the characteristics of the GaAs MESFET, such as reducing the leak current of the gate.

(Second Embodiment) FIGS. 2A to 2D are sectional views showing a manufacturing method of another embodiment of the present invention, in which the semiconductor element shown here is a source and a drain. GaAsM with a high carrier concentration n + active layer formed in the region
ESFET 32.

First, as shown in FIG. 2A, a semi-insulating GaA produced by the liquid encapsulation pull-up (LEC) method.
An n active layer 12 is formed on the semiconductor substrate 11 made of s, and n ⁺ having a high carrier concentration is formed on both sides of the n active layer 12.
The active layer 13 is selectively formed. For example, implantation energy of 80 is applied to the upper portion of the semiconductor substrate 11 by an ion implantation method.
After forming the n active layer 12 by implanting n-type ions with keV and an implanting carrier density of 6 × 10 ¹² cm ^-2 , a resist (not shown) is formed in the region except the region where the n ⁺ active layer 13 is to be formed. Then, using this resist as a mask, the implantation energy is 120 keV and the implantation carrier density is 2 × 10 ^13.
The n ⁺ active layer 13 is formed below the region where the source electrode and the drain electrode are formed by implanting n-type ions deeper than the n active layer at cm ⁻² .

Next, as shown in FIG. 2B, a source electrode 14 and a drain electrode 15 are formed by vapor-depositing an ohmic metal such as Au-Ge / Ni system on the n ⁺ active layer 13. The electrodes 14 and 15 are heat-treated and alloyed. After that, as shown in FIG. 2C, plasma is formed on the n active layer 12 and the n ⁺ active layer 13 between the electrodes 14 and 15 by using the source and drain electrodes 14 and 15 as a mask and using an RIE device or the like. And the modified layer 16 is formed. It is presumed that the plasma treatment was performed to form the modified layer 16 in this way, which caused a change in the level density near the surface of the n active layer 12 and the n ⁺ active layer 13 as in the first embodiment. As a result, the original intrinsic level of the semiconductor substrate 11 can be compensated and the influence of the surface level can be mitigated. In addition,
Also in this case, the gas serving as the plasma source is O ₂ , N ₂ , A
Not only gases such as r, CF ₄ , CHF ₃ and H ₂ ,
Any gas can be used as long as it serves as a plasma source. Alternatively, a combination of a plurality of these gases may be used.

Next, as shown in FIG. 2D, the semiconductor substrate 11 is immersed in 6N-HCl (6N hydrochloric acid) for 1 minute to form an oxide film (not shown) on the surface of the modified layer 16. After removal of the above), a gate electrode 18 made of Ti / Pt / Au or Al or the like is formed in the recess 17 formed in the modified layer 16 on the n-active layer 12, and the target GaAs MES is formed.
Get the FET 32. At this time, the recess etching for forming the recess 17 may be performed after the plasma irradiation, or may be performed after the recess etching is performed.

In this way, also in the GaAs MESFET of the type having the n ⁺ active layer 13, the gate breakdown voltage can be improved and the leakage current can be reduced, as in the GaAs MESFET of the first embodiment.

(Measurement result of the second embodiment) In order to investigate the characteristics of the above embodiment, O ₂ was used as a gas species to be a plasma source.
Using a gas, plasma treatment was performed by an RIE device under the conditions shown in Table 3 to fabricate the GaAs MESFET of the above example. In addition, the GaA of the conventional example is manufactured by the conventional method under the same conditions as the example except that the plasma treatment is not performed.
An sMESFET was produced. The GaAs MESFETs of both the embodiment and the conventional example have a gate length of 0.5 μm,
Gate width: 100 μm, Distance between n ⁺ active layers: 2.5 μm
And

[0054]

[Table 3]

Then, the relationship between the gate-drain voltage Vgd and the gate current Ig was measured. This gate current-voltage characteristic curve is shown in FIG. In FIG. 3, what is shown by a solid line is the gate current-voltage characteristic curve a of the embodiment, and what is shown by a broken line is the gate current-voltage characteristic curve b of the conventional example. As can be seen from FIG. 3, according to the example, the gate breakdown voltage is higher than that of the conventional example, and the leak current can be reduced. Further, the change of the gate current Ig with respect to the source-drain voltage Vds was measured. The measurement result is shown in FIG. In FIG. 4, the solid line shows the gate current C of the embodiment, and the broken line shows the gate current D of the conventional example. As can be seen from FIG. 4, in the embodiment, the gate current is smaller than that in the conventional example. Further, the gate-source voltage Vgs was set to 0 V, and changes in the drain conductance gd with respect to the source-drain voltage Vds were measured.
The results of these measurements are shown in FIG. In FIG. 5, the solid line shows a curve e showing the drain conductance gd of the embodiment, and the broken line shows a curve showing the drain conductance gd of the conventional example. As can be seen from FIG. 5, in the embodiment, the value of the drain-source voltage Vds that gives the peak of the drain conductance gd (the portion marked with a circle in FIG. 5) is large, which means that the concentration of the internal electric field is relaxed. It means being done. From these measurement results, according to the GaAs MESFET of the present invention,
It can be seen that the output power can be increased and the reliability and the like can be significantly improved.

(Third Embodiment) FIG. 6 is a sectional view showing still another embodiment of the present invention. The semiconductor element shown in FIG. 6 also has a high carrier concentration n ⁺ active region in the source and drain regions. GaAs MESFET 32 with layer 13 formed
a. This GaAs MESFET 32a is GaA
Compared to the sMESFET 32, the recess 17 is not provided and the element surface is flat. Further, the modified layer 16 is formed by irradiating the region of the n-active layer 12 which is slightly wider than the gate electrode 18 with plasma. In addition, 11a is a p layer.

The present invention is based on the GaAs MESF of this embodiment.
ET32a and GaAs MES of the embodiment shown in FIG. 1 (e)
The high resistance region (the modified layers 2a and 16) is formed by performing plasma treatment only in the vicinity of the gate of the element such as the FET 31. This makes it possible to increase the breakdown voltage. In such a structure, the conventional Ga
The parasitic resistance existing in series with the channel, which is a problem in the AsMESFET 73, can be suppressed low. Furthermore, for regions other than the plasma processing region, it is possible to achieve low resistance by using an ion implantation method or the like,
High breakdown voltage and low resistance can be realized independently. This is
In the above equation, the maximum current Imax and the breakdown voltage BVds can be increased, and the knee voltage Vknee can be decreased independently and simultaneously, which is very effective in increasing the output and efficiency of the MESFET. . Also,
According to the present invention, it is possible to use the LDD structure and the multi-step recess structure mentioned as the conventional example at the same time, and it is possible to add the effect of the present invention to the effect of the conventional example.

Further, when the resistance of the element is partially increased,
With the epitaxial growth technique, it is not possible to make a planar structure of the semiconductor layer. On the other hand, in the method using the plasma processing technique as in the present invention, a planar structure can be freely formed by combining the photolithography techniques. Therefore, in the planar structure, it is possible to partially increase the resistance of the element, and it is possible to increase the resistance by performing processing only on a necessary portion.

(Fourth Embodiment) FIGS. 7A to 7E are sectional views showing a method of manufacturing a Schottky barrier diode 33 according to still another embodiment of the present invention. First, FIG.
As shown in (a), n heavily doped with impurities
^An n active layer 22 is epitaxially grown on a low resistance semiconductor substrate 21 such as ⁺ GaAs.

Next, as shown in FIG. 7B, the resist 23 formed on the n active layer 22 is subjected to photolithography to be patterned so as to correspond to the Schottky electrode formation planned region and its peripheral region. Window on resist 23
To open.

Then, as shown in FIG. 7C, plasma is irradiated to the n active layer 22 by using the resist 23 as a mask and an RIE device or the like, and a modified layer 25 is formed on the surface of the n active layer 22. To do. By performing the plasma treatment on the n active layer 22 in this manner, the vicinity of the surface of the n active layer 22 can be modified. It is presumed that this causes a change in the surface level of the n-active layer 22, and as a result, the inherent level inherent in the semiconductor substrate 21 can be compensated and the influence of the surface level can be mitigated. In this case, the gas serving as the plasma source is O ₂ , N ₂ , Ar, CF ₄ , CHF ₃ , H.
Not only the gas such as ₂ but also any gas can be used as long as it is a gas serving as a plasma source. Alternatively, a combination of a plurality of these gases may be used.

After irradiating the plasma to the n active layer 22 in this way, the resist 23 is peeled off. After this, the semiconductor substrate 2
Another resist (not shown) is again formed on 1 and a window is opened in the resist corresponding to the Schottky electrode formation planned region by photolithography. Then, the semiconductor substrate 21 is immersed in 6N-HCl (6N hydrochloric acid) for 1 minute to remove the oxide film (not shown) formed on the surface of the modified layer 25, and then Ti / Pt /
An electrode material such as Au is vapor-deposited, and the Schottky electrode 26 is formed by lift-off as shown in FIG. In this way, the modified layer 25 is formed immediately below the Schottky electrode 26 and in a region wider than the Schottky electrode 26 around the Schottky electrode 26, and the electric field concentration at the end of the Schottky electrode 26 is relaxed.

Finally, as shown in FIG. 7E, an ohmic electrode 27 made of Au—Ge / Ni or the like is provided on the lower surface of the semiconductor substrate 21.

(Measurement result of the fourth embodiment) In order to investigate the characteristics of the above embodiment, O ₂ was used as a gas species to be a plasma source.
Plasma treatment was performed by using an RIE device under the conditions shown in Table 4 using gas, and the Schottky barrier diode of the above example was produced. Further, a Schottky barrier diode of a conventional example was manufactured by a conventional manufacturing method under the same conditions as those of the example except that the plasma treatment was not performed. further,
A comparative example in which the plasma treatment was applied only to the region immediately below the Schottky electrode under the same conditions as in the example (that is, FIG. 12).
A Schottky barrier diode (Schottky barrier diode as shown in (e)) was manufactured.

[0065]

[Table 4]

Then, the reverse current-voltage characteristics of the Schottky barrier diode were examined for the example, the conventional example and the comparative example. The result is shown in FIG. In FIG. 8, the horizontal axis represents the applied voltage (reverse voltage) between the Schottky electrode and the ohmic electrode, and the vertical axis represents the current density of the current flowing between the Schottky electrode and the ohmic electrode. The characteristic curve G and the broken line show the characteristic curve H of the conventional example, and the broken line shows the characteristic curve L of the comparative example.
As shown in FIG. 8, according to this example, it is apparent that the reverse characteristic of the Schottky electrode is significantly improved and the reverse breakdown voltage is increased. Also, the reverse breakdown voltage is significantly improved as compared with the comparative example in which the plasma is irradiated only directly below the Schottky electrode.

However, in this embodiment, the electric field concentration at the end portion (outer peripheral portion) of the Schottky electrode is relaxed by the modified layer, so that the reverse characteristic of the Schottky barrier diode is not deteriorated. Is improved.

(Fifth Embodiment) FIG. 9 shows a sectional view of a Schottky barrier diode 34 according to still another embodiment of the present invention. In this embodiment, the plasma treatment is applied only to the region immediately below the outer peripheral portion of the Schottky electrode 26 to form the modified layer 25.

Also in such a Schottky barrier diode 34, the electric field concentration at the end of the Schottky electrode 26 can be reduced by the modified layer 25,
Similar to the embodiment of FIG. 7, the reverse current-voltage characteristics are greatly improved while maintaining the forward characteristics.

(Sixth Embodiment) FIG. 10 shows a sectional view of a Schottky barrier diode 35 according to still another embodiment of the present invention. In this embodiment, the modified layer 25 is formed by performing plasma treatment only near the outside of the Schottky electrode 26.

Even in such a Schottky barrier diode 35, the electric field concentration at the end of the Schottky electrode 26 can be reduced by the modified layer 25,
Similar to the embodiment of FIG. 7, the reverse current-voltage characteristics are greatly improved while maintaining the forward characteristics. In the case of the Schottky barrier diode 35 having such a structure, the reformed layer 25 can be formed by performing plasma treatment after forming the Schottky electrode 26.

(Seventh Embodiment) FIGS. 11A to 11E are sectional views showing a method of manufacturing a Schottky barrier diode 36 according to still another embodiment of the present invention. this is,
Schottky barrier diode 33 as shown in FIG.
This is another method for manufacturing the Schottky barrier diode 36 having the same structure as the above.

First, n ⁺ GaAs as shown in FIG.
A resist 23 is formed on the n-active layer 22 on the low-resistance semiconductor substrate 21, etc., and an upper layer resist 28 is formed on the resist 23.

Next, as shown in FIG. 11B, the upper layer resist 28 is subjected to photolithography to be patterned, and a window 29 is opened in the upper layer resist 28 corresponding to the region where the Schottky electrode is to be formed. Then, the lower resist 23 is etched using the upper layer resist 28 as a mask,
A window 24 larger than the window 29 of the upper layer resist 28 is opened in the lower resist 23.

Next, as shown in FIG. 11C, the window 2
Plasma is applied to the n active layer 22 through 9, 24 to form the modified layer 25 in the region exposed in the window 24 of the resist 23. After that, the semiconductor substrate 21 is changed to 6N-HCl (6
The oxide film (not shown) formed on the surface of the modified layer 25 is removed by immersing it in normal hydrochloric acid for 1 minute, and then Ti / Pt / is formed on the modified layer 25 through the window 29 of the upper resist 28. A
Electrode materials such as u are vapor-deposited, and lift-off is performed, as shown in FIG.
The Schottky electrode 26 is formed as shown in (d).
Then, as shown in FIG. 11E, an ohmic electrode 27 of Au—Ge / Ni or the like is provided on the lower surface of the semiconductor substrate 21.

(Eighth Embodiment) FIGS. 12A to 12E are sectional views showing a method of manufacturing a Schottky barrier diode 37 according to still another embodiment of the present invention. First, as shown in FIG. 12A, an n active layer 22 is epitaxially grown on a low resistance semiconductor substrate 21 such as n ⁺ GaAs which is highly doped with impurities.

Next, as shown in FIG. 12B, the resist 23 formed on the n active layer 22 is patterned by photolithography to form a resist 23 corresponding to the Schottky electrode formation planned region. The window 24 is opened.

Then, as shown in FIG. 12C, the resist 23 is used as a mask to irradiate the n active layer 22 with plasma by using an RIE device or the like to form a modified layer 25 on the surface of the n active layer 22. To do. By performing the plasma treatment on the n active layer 22 in this manner, the vicinity of the surface of the n active layer 22 can be modified. It is presumed that this is because the surface level of the n-active layer 22 can be changed to compensate for the inherent level inherent in the semiconductor substrate 21 and to reduce the influence of the surface level. Also in this case, as the plasma source gas, not only gases such as O ₂ , N ₂ , Ar, CF ₄ , CHF ₃ and H ₂ but also any gas can be used as long as it is a plasma source gas. it can. Alternatively, a combination of a plurality of these gases may be used.

Thus, the modified layer 25 is formed by irradiating the n active layer 22 with plasma, and then the semiconductor substrate 21 is exposed to 6N-.
After immersing in HCl (6N hydrochloric acid) for 1 minute to remove an oxide film (not shown) formed on the surface of the modified layer 25, Ti / Pt is deposited on the modified layer 25 from above the resist 23. / Au
Electrode materials such as the above are vapor-deposited, and the Schottky electrode 26 is formed by lift-off as shown in FIG. In this way, the modified layer 25 is formed on the entire surface immediately below the Schottky electrode 26.

Finally, as shown in FIG. 12E, an ohmic electrode 27 made of Au—Ge / Ni or the like is provided on the lower surface of the semiconductor substrate 21.

(Measurement Result of Eighth Embodiment) In order to investigate the characteristics of the above embodiment, O ₂ was used as a gas species serving as a plasma source.
Using a gas, plasma treatment was performed by an RIE device under the conditions shown in Table 5, and the Schottky barrier diode of the above example was produced. Further, a Schottky barrier diode of a conventional example was manufactured by a conventional manufacturing method under the same conditions as those of the example except that the plasma treatment was not performed.

[0082]

[Table 5]

Then, the forward current-voltage characteristics of the Schottky barrier diode were examined for the example and the conventional example. The result is shown in FIG. The horizontal axis of FIG. 13 is the applied voltage (forward voltage) between the Schottky electrode and the ohmic electrode, and the vertical axis is the value of the current flowing between the Schottky electrode and the ohmic electrode. The solid line shows the characteristic curve of the example. Numerals indicated by a broken line are characteristic curves of the conventional example. As can be seen from FIG. 13, according to this embodiment, the forward characteristic of the Schottky electrode is improved as compared with the conventional example.
In addition, FIG. 14 shows the forward characteristic curves N and L of FIG. 13 using a logarithmic scale of the current value, and the size of the barrier height of the Schottky junction is determined from the slope of each forward characteristic curve N and L. When Φ _BIV is _calculated , Φ _BIV = 0.6 in the embodiment.
4 eV, Φ _BIV = 0.76 eV in the conventional example. Therefore, according to the embodiment of the present invention, the barrier height of the Schottky junction can be reduced without changing the carrier concentration of the n active layer or the n ⁺ semiconductor substrate. On the other hand, the reverse characteristic was similar to that of the conventional example (FIG. 8).
See the curve).

According to this embodiment, however, the barrier height of the Schottky electrode 26 can be reduced as a result of the modification of the n active layer 22 in the region directly below the Schottky electrode 26, and the Schottky barrier diode. The forward characteristic can be improved without deteriorating the reverse characteristic of 37. Note that in FIG. 12E, the Schottky electrode 26 and the modified layer 25 are aligned because of the manufacturing method thereof, but the modified layer 25 is formed in a region narrower than the Schottky electrode 26. It doesn't matter.

When the fourth to eighth embodiments are examined, the forward characteristics of the Schottky barrier diode are improved by forming a modified layer by performing plasma treatment on almost the entire area immediately below the Schottky electrode. You can
It can be seen that the reverse direction characteristics can be improved by performing the plasma treatment on the outer peripheral edge of the Schottky electrode or a region adjacent to the outer peripheral edge to form the modified layer. Further, by performing plasma treatment on the entire surface immediately below the Schottky electrode and its peripheral region to form the modified layer, both the forward characteristic and the reverse characteristic of the Schottky barrier diode can be improved.

The plasma apparatus, the conditions of the plasma treatment, etc. are not limited to those of the above-mentioned embodiments, and the compound semiconductor substrate to be used and its characteristics (carrier concentration,
It may be appropriately selected and set according to the structure).

In the above embodiment, GaAs MESF is used.
Although the ET and the Schottky barrier diode have been described, the feature of the present invention resides in that the Schottky electrode formation region of the active layer of the semiconductor substrate or the vicinity thereof is formed before the Schottky electrode formation (after the formation in some cases). At least a part is subjected to plasma treatment. Therefore, the present invention is applicable to HEMT (High Electron Transfer Transistor), planar Schottky barrier diode, etc. in addition to GaAs MESFET and Schottky barrier diode.
It can be applied to general compound semiconductor devices utilizing a Schottky junction between a metal and a semiconductor. Also, GaAs
The case of the MESFET and the Schottky barrier diode is not limited to the structure and the manufacturing process of each of the above-described embodiments, and can be applied to a semiconductor device having another structure and another manufacturing method.

[0088]

As described above, according to the method for manufacturing a semiconductor device of the present invention, the active layer immediately below and adjacent to the Schottky electrode forming a Schottky junction with the active layer is modified by plasma treatment. Can be quality. It is presumed that this is because the carrier density immediately below and near the Schottky electrode in the active layer is reduced, and the surface level density is changed to improve the device characteristics of the semiconductor device. At the same time, it seems that the electric field concentration at the ends of the gate electrode and the drain electrode can be alleviated.

For example, in a field effect type transistor element such as GaAs MESFET, the gate breakdown voltage can be improved and the gate leakage current can be reduced. Further, in a diode element such as a Schottky barrier diode, the forward characteristic and the reverse characteristic of the diode element can be improved.

The plasma treatment may be performed after the active layer is formed and before the Schottky electrode is formed (or in some cases, after the Schottky electrode is formed), in a semiconductor device that forms a Schottky junction with the active layer of the compound semiconductor substrate. If so, it can be widely applied regardless of its structure and manufacturing method.

That is, it is possible to manufacture a semiconductor element having excellent pressure resistance and good characteristics by a simple method of plasma treatment without requiring complicated steps, complicated structures, special equipment, and complicated control. Therefore, the manufacturing cost and the material cost can be significantly reduced.

[Brief description of drawings]

1A to 1E are Ga according to an embodiment of the present invention.
It is sectional drawing which shows each process of the manufacturing method of AsMESFET.

2 (a) to 2 (d) are graphs of G according to another embodiment of the present invention.
It is sectional drawing which shows each process of the manufacturing method of aAs MESFET.

FIG. 3 is a diagram showing measurement results of a gate current and a gate-drain voltage of the above-mentioned embodiment and the conventional example.

FIG. 4 is a diagram showing measurement results of a gate current and a source-drain voltage of the above-mentioned embodiment and the conventional example.

FIG. 5 is a diagram showing measurement results of the drain conductance and the source-drain voltage of the above-described example and the conventional example.

FIG. 6 is a GaAsME according to yet another embodiment of the present invention.
It is sectional drawing which shows SFET.

7A to 7E are cross-sectional views showing respective steps of a method of manufacturing a Schottky barrier diode according to still another embodiment of the present invention.

FIG. 8 is a diagram showing reverse current-voltage characteristics of Schottky barrier diodes according to the above-described example, conventional example, and comparative example.

FIG. 9 is a sectional view showing a structure of a Schottky barrier diode according to still another embodiment of the present invention.

FIG. 10 is a sectional view showing the structure of a Schottky barrier diode according to still another embodiment of the present invention.

11A to 11E are cross-sectional views showing respective steps of a method of manufacturing a Schottky barrier diode according to still another embodiment of the present invention.

12A to 12E are sectional views showing a method of manufacturing a Schottky barrier diode according to still another embodiment of the present invention.

FIG. 13 is a diagram showing forward current-voltage characteristics of the Schottky barrier diodes of the above-mentioned embodiment and the conventional example.

FIG. 14 is a diagram showing forward current-voltage characteristics of the Schottky barrier diode of the above-described example and the conventional example.

FIG. 15: Conventional GaAs MESF with general structure
It is sectional drawing which shows the manufacturing method of ET.

FIG. 16: Conventional GaAs MESF with LDD structure
It is sectional drawing which shows ET.

FIG. 17 is a cross-sectional view showing an example of a conventional semiconductor device having a structure with an improved breakdown voltage.

FIG. 18 is a diagram showing static characteristics and a load line of a GaAs MESFET.

19 (a), (b) and (c) are cross-sectional views showing a conventional method of manufacturing a Schottky barrier diode.

[Explanation of symbols]

 1 Semiconductor Substrate 2 Active Layer 2a Modified Layer 3 Source Electrode 4 Drain Electrode 5 Lower Layer Resist Film 6 Upper Layer Resist Film

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 29/93 S

Claims (10)

[Claims] 1. A semiconductor device having a Schottky electrode forming a Schottky junction with an active layer formed on a compound semiconductor substrate, wherein at least a part of a region where the Schottky electrode of the active layer is formed and its vicinity are provided. A semiconductor device having a modified layer formed on the surface. 2. The semiconductor device according to claim 1, wherein the modified layer is a high resistance layer. 3. The semiconductor device according to claim 1, wherein the modified layer is formed by plasma treatment. 4. The semiconductor device according to claim 1, wherein a modified layer is formed in a region including a region of the active layer where the Schottky electrode is formed. 5. A Schottky electrode and 2 on the active layer.
5. The semiconductor device according to claim 1, wherein the semiconductor device is a field effect transistor device having one ohmic electrode formed thereon. 6. In a Schottky barrier type diode element having a Schottky electrode formed on the active layer, a modified layer is formed in a region immediately below the outer periphery of the Schottky electrode or in a region adjacent to the outer periphery. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device. 7. A Schottky barrier type diode element having a Schottky electrode formed on the active layer, wherein a modified layer is formed in a region directly under the Schottky electrode or in a region smaller than the region directly under the Schottky electrode. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device. 8. A Schottky barrier type diode device having a Schottky electrode formed on the active layer, wherein a modified layer is formed in a region directly under the Schottky electrode or in a region larger than the region directly under the Schottky electrode. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device. 9. A method of manufacturing a semiconductor device, comprising: forming an active layer on a compound semiconductor substrate; and providing a Schottky electrode forming a Schottky junction with the active layer, wherein the Schottky electrode of the active layer is formed. At least a part of the region and its vicinity are subjected to plasma treatment for modification, and then a Schottky electrode is formed on the active layer so as to be in contact with or adjacent to the modified layer. Device manufacturing method. 10. A plasma treatment is applied to a region of the active layer where the Schottky electrode is formed and its vicinity to form a modified layer on the active layer, and then a Schottky electrode is formed on the modified layer. 10. The method for manufacturing a semiconductor device according to claim 9, wherein.