JPH11204544A - Compound semiconductor field-effect transistor and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten effective gate length, without performing the shortening of a gate-electrode length and to improve mutual conductance by cutting off a channel region in the depletion layer extending into the channel region from the gate electrode only in the channel region at the side of a source from the center. SOLUTION: The impurity concentration of a channel region 3a at the lower part of a gate electrode 6 is lower than that in the region on the side of a drain electrode 8 in a region 30 on the side of a source electrode 7 from the approximate center of the channel region 3a. In this structure, the extension of the depletion layer from the gate electrode 6 becomes larger than the region on the side of the drain electrode 8 in the region 30 on the side of the source electrode 7. As a result, when a negative voltage is applied on the gate electrode 6, the channel region 30 is pinched off in the region 30 on the side of the source electrode 7. In this case, since the shortening of the effective gate length which determines the pinch-off voltage becomes possible, the increase in drain voltage and the improvement of the mutual conductance can be achieved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compound semiconductor field-effect transistor, and more particularly, to a compound semiconductor field-effect transistor in which the effective gate length is reduced and the transconductance is improved.

[0002]

2. Description of the Related Art In order to improve the transistor characteristics of a compound semiconductor field-effect transistor, it is necessary to shorten the gate length (shortening the gate length). The effect causes variations in the pinch-off voltage (Vp) and increases the gate resistance, and consequently the transistor characteristics are degraded.

[0003] Therefore, the inventor of the present invention has proposed a method as shown in FIG.
Depletion type SAGFET (Self Aligned Gate FE
Using T), we studied to shorten only the effective gate length without shortening the actual gate length. In the figure, 1 is a semi-insulating GaAs semiconductor substrate, 2 is a p-type semiconductor layer, 3 is an n-type channel layer, 4 is an intermediate-concentration n-type conductive layer (n ′ layer), and 5 is a high-concentration n-type conductive layer. (N ⁺ layer), 6 is a Schottky junction gate electrode (gate electrode) formed on the channel layer 3, 7 is a source electrode formed on the n ⁺ layer 5, and 8 is n ⁺
This is a drain electrode formed on the layer 5. FIG.
9 schematically shows the distribution of the carrier concentration Nd in the vicinity of the channel layer 3 below the gate electrode 6.
Usually has a uniform distribution in both the X and Y directions (in FIG. 14, the n ′ layer and the n ⁺ layer are also shown).

In such a SAGFET, as shown in FIG. 15, a depletion layer 600 extending from the gate electrode extends to the channel layer 3 to control the amount of electrons moving through the channel layer 3. Since the electrode 8 is maintained at a higher potential than the source electrode 7, the depletion layer 600 extends toward the drain electrode 8 as shown in FIG. That is, when the depletion layer 600 is extended, first, pinch-off occurs on the drain electrode 8 side. Therefore, by controlling the electron path in the channel region 3 in the depletion layer 600 extending to the drain electrode 8 side, the actual gate length (the length of the gate electrode 6) is not shortened, but the effective gate length is reduced. (The length of the portion where the depletion layer 600 contacts the p-layer 2) can be reduced.

[0005]

When the amount of electrons passing through the channel region 3 is controlled on the drain electrode 8 side of the channel region 3, there is a certain limit to the improvement of the transconductance. Therefore, the present inventors have conducted intensive studies and found that the limit to the improvement of the transconductance described above is that electrons flowing into the narrow channel region 3 are further controlled by the depletion layer 600 on the drain electron 8 side of the channel region 3. ,
It has been found that electrons accumulate in the channel 3 near the source electrode 7 side of the depletion layer 600, and such electrons do not contribute to conduction and result in loss. Therefore, an object of the present invention is to provide a compound semiconductor field-effect transistor in which the effective gate length is shortened without shortening the gate electrode length and the mutual conductance is improved.

[0006]

Therefore, as a result of intensive studies, the present inventors have developed a depletion layer on the source electrode side of the channel region to control the movement of electrons in the channel region, thereby forming a channel region within the channel region. It has been found that it is possible to prevent the accumulation of electrons and to improve the mutual conductance while shortening the effective gate length, and completed the present invention.

That is, the present invention provides a compound semiconductor field effect transistor in which a source electrode, a drain electrode, and a gate electrode are formed on a conductive region, and the conductive region immediately below the gate electrode is used as a channel region. Wherein the depletion layer extending from the gate electrode to the channel region blocks the channel region only in the source-side channel region closer to the source electrode than substantially in the center of the channel region. Thus, the depletion layer blocks the channel region only on the source electrode side from the approximate center of the channel region,
First, the pinch-off structure prevents electrons from stagnation in the channel region of the depletion layer on the source electrode side unlike the conventional structure, thereby improving the transconductance. Second, the effective gate length when the channel region is pinched off can be made shorter than the actual gate electrode length, and the gate length can be reduced while suppressing the short channel effect and the increase in gate resistance. Therefore, it is possible to improve the transistor characteristics of the compound semiconductor field effect transistor.

The channel region is cut off by a depletion layer having no electrons extending from the gate electrode to close the channel region and stop the flow of electrons. Also,
The source electrode side from the approximate center of the channel region is called a source-side channel region, and the drain electrode side from the approximate center of the channel region is called a drain-side channel region.

The present invention also provides the compound semiconductor field effect transistor, wherein the conductive region is an n-type conductive layer formed on a p-type region, and the channel region is an n-type conductive layer immediately below the gate electrode. A depletion layer reaching the p-type region and pinching off only in the source-side channel region.

The channel length of the channel region is
0.2 to 1.0 μm, and the source side channel region extends from the source electrode side electrode end to the channel length of 20 to 40 μm.
% Of the compound semiconductor field-effect transistor. As described above, when the channel length is 0.2 to 1.0 μm, the short channel effect becomes remarkable. Therefore, by applying the present invention,
It is possible to shorten the effective gate length and to improve the mutual conductance.

The channel depth of the source-side channel electrode is preferably smaller than the drain-side channel region. By using such a structure, pinch-off can be performed on the source electrode side of the channel region.

Preferably, a step having a step is provided substantially at the center of the bottom of the channel region, and the depth of the channel region is smaller on the source electrode side than on the step and smaller on the drain electrode side. By using such a structure, pinch-off can be performed on the source electrode side of the channel region.

Further, according to the present invention, a step having a step is provided substantially at the center of the surface of the channel region, and the depth of the channel region is smaller on the source electrode side than on the step and on the drain electrode side. A compound semiconductor field-effect transistor characterized by the above feature. By using such a structure, the channel region can be pinched off on the source electrode side of the channel region.

It is preferable that the n-type impurity concentration in the source-side channel region is lower than that in the drain-side channel region. This is because the extension of the depletion layer in the source-side channel region increases, and the channel can be pinched off in the source-side channel region.

[0015] The n-type impurity concentration of the channel region may gradually increase from the source electrode side to the drain electrode side.

Further, according to the present invention, preferably, the gate electrode in contact with the surface of the channel region includes a source-side gate electrode provided on the source electrode side from a substantially center of the channel region, and a drain provided on the drain electrode side. And a work function difference between the semiconductor material in the channel region and the gate electrode, wherein the source-side gate electrode is larger than the drain-side gate electrode. It is also a transistor. By using two types of electrode materials having different electrode materials, the length of the depletion layer formed under the gate electrode is larger at the lower portion of the source-side gate electrode than at the lower portion of the drain-side gate electrode, and the length of the depletion layer is lower in the source-side channel region. This is because the channel can be pinched off.

Further, the present invention provides a semiconductor device comprising:
The compound semiconductor field effect transistor is characterized in that the lower part of the channel region is a semi-insulating region.
By adopting such a structure, the parasitic capacitance generated below the channel region can be reduced.

Further, according to the present invention, a semi-insulating layer, an n-type electron supply layer, and an n-type contact layer are sequentially laminated, and a channel layer is formed near the interface of the semi-insulating layer with the n-type electron supply layer. A heterojunction transistor comprising: a source electrode provided on the n-type contact layer; a drain electrode;
A gate electrode made of a p-type electrode layer penetrating the n-type contact layer so as to reach the n-type electron supply layer, wherein the gate electrode also extends on the n-type contact layer on the drain electrode side. The compound semiconductor field effect transistor is characterized in that a current flowing through the channel layer is controlled by a depletion layer extending from the bottom of the p-type electrode layer. By using such a structure, it is possible to improve the mutual conductance while shortening the effective gate length even in a heterojunction transistor (HEMT). The bottom of the p-type electrode layer refers to a portion where the p-type electrode layer embedded in the opening provided to penetrate the n-type contact layer is in contact with the n-type electron supply layer below the n-type contact layer. Say.

The semi-insulating layer may be a semi-insulating GaAs layer, the n-type electron supply layer may be an n-type Al _x Ga _{1 -x} As layer, and the n-type contact layer may be an n-type GaAs layer. preferable. The Al content is 0 <x <0.3.
(% By weight) is preferred.

Further, the present invention provides a substrate forming step of sequentially forming a p-type semiconductor layer and an n-type conductive layer on a semiconductor substrate;
Forming a source electrode, a drain electrode, and a gate electrode between these electrodes on the type conductive layer, forming an electrode using the n-type conductive layer immediately below the gate electrode as a channel region, and using the gate electrode as a mask. An implantation step of obliquely implanting a p-type impurity from a substantially center of the channel region into a region on the source electrode side, so that an n-type impurity concentration of the source-side channel region is lower than an n-type impurity concentration of the drain-side channel region; And a method for manufacturing a compound semiconductor field-effect transistor.

The implantation step may also serve as a step of making the depth of the source-side channel region smaller than that of the drain-side channel region.

Also, in the present invention, the electrode forming step includes a step of forming a gate electrode composed of a source-side gate electrode and a drain-side gate electrode, and the step of forming the gate electrode includes a step of forming a drain-side gate electrode. Forming a protective film covering the upper surface of the drain-side gate electrode and extending on the n-type conductive layer on the drain side; and depositing a source-side gate electrode material layer on the entire surface. Forming a source-side gate electrode by reducing the thickness of the gate electrode material layer from the upper surface, thereby producing a compound semiconductor field-effect transistor. This is because a gate electrode including a source-side gate electrode and a drain-side gate electrode can be easily formed by such a method.

Further, according to the present invention, after the substrate forming step,
Etching the surface of the n-type conductive layer, providing a step substantially orthogonal to the set channel length direction, comprising the step of forming a step, the electrode forming step straddles the step, A method for manufacturing a compound semiconductor field-effect transistor, comprising the step of forming the gate electrode. This is because a structure in which the depth of the channel region is smaller on the source electrode side than on the drain electrode side can be easily manufactured by such a method.

Further, according to the present invention, after the substrate forming step,
Forming a step substantially orthogonal to the set channel length direction at the bottom of the n-type conductive layer to form a step;
A step of selectively injecting an n-type impurity into the n-type conductive layer so that a channel depth on the drain electrode side from the step portion is larger than a channel depth on the source electrode side; The method is also a method for manufacturing a compound semiconductor field effect transistor, wherein the step is a step of forming the gate electrode so as to cover the step portion. This is because a structure in which the depth of the channel region is smaller on the source electrode side than on the drain electrode side can be easily manufactured by such a method.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described with reference to FIGS. Embodiment 1 FIG. FIG. 1A is a cross-sectional view of a GaAs field-effect transistor according to a first embodiment of the present invention, in which p-type semiconductor layers 20, 21, and n are sequentially provided on a semi-insulating GaAs substrate 1. A n-type conductive layer 5; a source electrode 7, a drain electrode 8 provided on the n-type conductive layer 5; and a gate electrode 6 provided between these electrodes. A compound semiconductor field-effect transistor having a conductive layer as a channel region 3a includes a depletion layer extending from the gate electrode 6 to the channel region 3a to control a current flowing through the channel region. At the source electrode 7 side from the approximate center of the channel region 3a,
A compound semiconductor field effect transistor characterized by being lower than the drain electrode 8 side.

That is, the channel region 3 below the gate electrode 6
The impurity concentration of a is lower in the source electrode 7 side region 30 than in the drain electrode 8 side region from substantially the center of the channel region 3a. Here, the n ′ layer is provided for forming an LDD structure.

With such a structure, the extension of the depletion layer from the gate electrode 6 is larger in the source electrode 7 side region 30 than in the drain electrode 8 side region, so that a negative voltage is applied to the gate electrode 6. The source electrode 7
In the side region 30, the channel region 30 is pinched off. That is, the channel region 3 on the source electrode 7 side
The pinch-off voltage at 0 (hereinafter, referred to as “Vp1”) and the pinch-off voltage at the channel region 31 on the drain electrode 8 side (hereinafter, referred to as “Vp2”) satisfy Vp1> Vp2.

In this case, as shown in FIG. 1B, when the pinch-off is performed on the channel region 30 on the source electrode 7 side under the gate electrode 6, the channel region on the drain electrode 8 side is not yet in the pinch-off state. Is determined by Vp1. Accordingly, it is possible to reduce the effective gate length (the length of the region where the depletion layer actually cuts off the channel region), which determines the pinch-off voltage, while keeping the actual dimensions of the gate electrode 6 as in the conventional case. It is possible to increase the increase and the mutual conductance. On the other hand, the shape of the depletion layer looks like a pseudo dual gate. Therefore, as compared with the case where the length of the actual gate electrode 6 is shortened, the occurrence of the short channel effect can be suppressed, and the drain conductance can be reduced. Further, since the size of the actual gate electrode 6 is large, the gate resistance does not increase. Further, since the depletion layer pinches off only on the source electrode 7 side from the approximate center of the channel region 3, electrons do not stay in the channel region 3 on the source electrode 7 side of the depletion layer as in the conventional structure. It is possible to improve the mutual conductance.

The length of the gate electrode 6 is 2.0 μm.
Hereinafter, it is particularly preferable that the depletion layer reaches the p layer 20 and pinches off at a distance of 20 μm to 40% of the channel length from the source electrode side, particularly 1.0 μm or less. In particular, when the gate length is 1.0 μm or less, the short channel effect becomes remarkable. Therefore, by applying the present invention, only the effective gate length can be reduced without shortening the actual gate electrode length. This is because it is possible to suppress the occurrence of the channel effect and the like.

Embodiment 2 FIG. FIG. 2 is a sectional view of a GaAs field effect transistor according to the present embodiment. In the present embodiment, the channel region 3b under the gate electrode 6
Are the source electrode 7 side channel region 32 and the drain electrode 8
In the same manner as in the first embodiment, the n-type impurity concentration of the channel region 32 is lower than the n-type impurity concentration of the channel region 33. Is formed shallower than the depth of the channel region 33. For example, the channel region 32 has a depth of 300 to 500 ° and the channel region 3
3 is 1500-2000 °. In the figure,
1 denote the same or corresponding parts.

Also in such a structure, the first embodiment is used.
Similarly to the above, the source electrode 7 side region 32 under the gate electrode 6
, The channel region 33 on the drain electrode 8 side is not yet in the pinch-off state, and the pinch-off voltage of the transistor is determined by Vp1. Therefore, the effective gate length for determining the pinch-off voltage can be reduced while the actual dimensions of the gate electrode 6 remain unchanged. Also,
Since the depletion layer pinches off only on the source electrode side from the center of the channel region, electrons do not stagnate in the channel region on the source electrode side of the depletion layer as in the conventional structure, and the transconductance is improved. Becomes possible.

Next, FIG. 3 shows the G according to the second embodiment.
FIG. 2 is a cross-sectional view illustrating a manufacturing process of an aAs field-effect transistor.
FIG. 3 shows a multi-finger structure in which a plurality of gate electrodes 6 are formed on a GaAs substrate 1 in order to show a manufacturing process of a high-output transistor.

First, as shown in FIG.
A p-type semiconductor layer 2 and an n-type channel region 3 are formed on a semi-insulating substrate 1 by using an ion implantation technique.
Is formed, an n ′ layer 4 and an n ⁺ layer 5 are formed. Next, a resist mask 9 serving as an ion implantation mask for changing the concentration of the channel region 3 below the gate electrode 6 is formed.

Next, as shown in FIG. 3B, using the resist 9 and the gate electrode 6 as a mask, for example, Mg ions as a p-type
^Under the implantation condition of ¹² cm ^-2 , ion implantation is performed twice obliquely in the direction shown in the figure. Thus, the p-type semiconductor layer is divided into two regions 20 and 21 having different p-type impurity concentrations. Also,
The n-type carrier concentration distribution of the channel region 3 under the gate electrode also changes, and the region where the ion implantation is not performed becomes the channel layer 31 having the high n-type impurity concentration, while the region where the ion implantation is performed has the n-type impurity concentration. The lower area 30 is obtained.
Also, by controlling so that a large amount of p-type ions are implanted near the bottom of the channel region 30, such a region is inverted from n-type to p-type to become the p-type semiconductor layer 20, and FIG. As shown, the depths of the channel layer 30 and the channel layer 31 can be made different. When the ion implantation is performed under the condition that the depths do not differ, a structure as shown in FIG. 1 can be obtained.

Next, as shown in FIG. 3C, the resist 9 is removed.

Next, as shown in FIG. 3D, a source electrode 7 is formed on the n ⁺ layer 5 on the channel region 30 side, and a drain electrode 8 is formed on the n ⁺ layer 5 on the channel layer 31 side. Thus, the GaAs field effect transistor according to the present embodiment is completed.

Embodiment 3 FIG. 4 is a sectional view of a GaAs field effect transistor according to the third embodiment of the present invention. In the figure, the same reference numerals as those in FIG. 1 indicate the same or corresponding parts. In the present embodiment, the gate electrode 6a in contact with the surface of the channel region 3 has a first electrode 60 provided on the source electrode 7 side from a substantially center of the channel region and a second electrode provided on the drain electrode 8 side. The work function difference between the semiconductor material forming the channel region 3 and the electrode material of the first electrode 60 is determined by the difference between the semiconductor material forming the channel region 3 and the electrode material of the second electrode 61. The structure is larger than the work function difference.

With such a structure, the first electrode 6
0 and the barrier potential (φb1) of the channel region 3 become higher than the barrier potential (φb2) of the second electrode 61 and the channel region 3. As a result, as shown in FIG.
On the source electrode 7 side, it expands more than on the drain electrode 8 side, and as a result, Vp1 becomes a value larger than Vp2. That is, when the channel region 3 on the source electrode 7 side below the gate electrode 6a is pinched off, the channel region 3 on the drain electrode 8 side is not yet in the pinch-off state, and the pinch-off voltage of the transistor is determined by Vp1.
Therefore, by using such a structure, the same effect as in the first embodiment can be obtained.

Next, a first manufacturing process of the structure according to the present embodiment will be described with reference to FIG. First, FIG.
As shown in FIG. 1A, after a p-type semiconductor layer 2 and an n-type channel layer 13 are formed on a GaAs substrate 1, a gate electrode 6 is formed.
The first electrode 60 on the side of the source electrode 7 constituting a is formed by vapor deposition or the like. Materials for such electrodes include Ti, Pt
And the like are preferably used.

Next, as shown in FIG. 5B, a second electrode material on the drain electrode 8 side is deposited on the entire surface by using sputtering or the like. Such electrode materials include WSi, WN, W
It is preferable to use SiN or the like. Subsequently, a resist 90 is formed as an etching mask for the second electrode material.

Next, as shown in FIG. 5C, the second electrode material is removed by reactive ion etching or the like using the resist 90 as a mask to form a second electrode 61.

Next, as shown in FIG. 5D, ion implantation using the gate electrode 6a as a mask causes the n ′ layer 4,
The n ⁺ layer 5 is formed, and the lower part of the gate electrode 6a is used as the channel region 3. Further, the source electrode 7 and the drain electrode 8
Is formed to complete the GaAs field effect transistor shown in FIG.

Next, a second manufacturing process of the structure according to the present embodiment will be described with reference to FIG. First, FIG.
As shown in FIG. 1A, after a p-type semiconductor layer 2 and a channel layer 13 are formed on a GaAs substrate 1, a second electrode on the drain electrode 8 side is formed.
An electrode 61 is formed, and further, a protective film 10 made of SiO ₂ or the like, which covers the second electrode 61 and extends on the channel layer 13 on the drain electrode 8 side, is formed. Subsequently, an electrode material 60 ′ of the first electrode 60 on the source electrode 7 side is deposited on the entire surface by sputtering or the like.

Next, as shown in FIG. 6B, the electrode material 60 'is removed using reactive ion etching or the like.
In this case, the electrode material 60 'remains only in the thicker portion of the electrode material 60'.

Next, as shown in FIG.
0, the electrode material 6 on the protective film 10 is removed.
Remove 0 '. The electrode material 6 on the protective film 10
0 'is not in contact with the semiconductor substrate, and thus does not have to be removed. continue. Using ion implantation technology,
After forming an n ′ layer 4 and an n ⁺ layer 5 and forming a channel region 3 below the gate electrode 6 b, a source electrode 7 and a drain electrode 8 are formed.
Are formed, thereby completing the GaAs field effect transistor.

Embodiment 4 FIG. Fourth Embodiment A GaAs field effect transistor according to a fourth embodiment of the present invention will be described with reference to FIG. In the figure, the same reference numerals as those in FIG. 1 indicate the same or corresponding parts. In the manufacturing process of the field-effect transistor according to the present embodiment, first, as shown in FIG.
An etching step 3A is formed in the channel layer 13. It is preferable that the step 3A is about several hundreds to 1,000 degrees.

Next, as shown in FIG. 7B, the gate electrode 6 is formed in the direction of the step 3A so as to cover the step 3A and to have the step 3A substantially at the center of the gate electrode 6.
An n ′ layer 4 and an n ⁺ layer 5 are formed by ion implantation.

Next, a source electrode 7 and a drain electrode 8 are formed on the n ⁺ layer 5 to complete the GaAs field effect transistor according to the present embodiment.

In the GaAs field-effect transistor according to the present embodiment, the channel region 3 under the gate electrode 6 is shallower than the substantially center of the gate electrode 6 and shallower than the drain electrode 8 because of the step 3A. Even if the channel region 3 is pinched off on the source electrode 7 side,
The drain electrode 8 has not yet been pinched off.
Therefore, the pinch-off voltage of the transistor is determined by Vp1, and the same effect as in the first embodiment can be obtained.

Embodiment 5 A GaAs field effect transistor according to a fifth preferred embodiment of the present invention will be described with reference to FIG. In the figure, the same reference numerals as those in FIG. 1 indicate the same or corresponding parts. In the manufacturing process of the field effect transistor according to the present embodiment, first, as shown in FIG.
After forming the p-type semiconductor layer 2, a mask 10a is formed at a position as shown in the figure. Next, the channel layer 13 is formed by implanting n-type ions into the entire surface. In this case, the portion where the mask 10a is not formed is directly connected to the p-type semiconductor layer 2
Are implanted into the portion where the mask 10a is formed by the through implantation through the mask 10a. Therefore, the depth of the directly implanted region is
8 is larger than the depth of the through-implanted region.
Channel layer 13 provided with step 6B as shown in FIG.
Is formed.

Next, as shown in FIG.
After removing 0a, the gate electrode 6 is formed along the step 6B of the channel layer 13 formed in the step of FIG. 8A so as to cover above the step 6B. Thereby, an n ′ layer 4 and an n ⁺ layer 5 are formed.

Next, as shown in FIG. 8C, the drain electrode 8 is formed on the n ⁺ layer 5 where the channel layer 13 is deep, and the source electrode 7 is formed on the n ⁺ layer 5 where the channel layer 13 is shallow. Are formed, thereby completing the GaAs field effect transistor.

In the GaAs field-effect transistor according to this embodiment, the channel region 3 under the gate electrode 6 is also formed.
However, since it is shallower than the gate electrode 6 on the source electrode 7 side and the drain electrode 8 side, even if the channel region 3 is pinched off on the source electrode 7 side, the drain electrode 8 side is not yet in the pinch off state. Therefore, the pinch-off voltage of the transistor is determined by Vp1, and the same effect as in the first embodiment can be obtained.

Embodiment 6 FIG. Embodiment 6 A GaAs field effect transistor according to Embodiment 6 of the present invention will be described with reference to FIG. In the figure, the same reference numerals as those in FIG. 1 indicate the same or corresponding parts. In the manufacturing process of the field-effect transistor according to the present embodiment, first, as shown in FIG.
After the p-type semiconductor layer 2 and the channel layer 13 are formed, a first electrode 60 is formed, and only one side of the first electrode 60 is selectively ion-implanted with n-type ions. Thereby, the thickness of the channel layer 13 on one side of the first electrode 60 is increased, and the step 6C is formed.

Next, as shown in FIG. 9B, in the same manner as in the third embodiment, a second electrode is formed on the channel layer 13 side of the first electrode 60 on which the ion implantation is performed. 61 are formed.

Next, as shown in FIG. 9C, after the n ′ layer 4 and the n ⁺ layer 5 are formed, the source electrode 7 and the drain electrode 8 are formed, and the GaAs according to the present embodiment is formed.
The field effect transistor is completed.

In the GaAs field effect transistor according to the present embodiment, the channel region 3 under the gate electrode 6
However, in addition to having a structure that is shallower than the drain electrode 8 side on the source electrode 7 side from the approximate center of the gate electrode 6, the depletion layer extending from the gate electrode has extended more on the source electrode 7 side than on the drain electrode 8 side. Structure. Therefore, even when the channel region 3 is pinched off on the source electrode 7 side,
The drain electrode 8 has not yet been pinched off.
Therefore, the pinch-off voltage of the transistor is determined by Vp1, and the same effect as in the first embodiment can be obtained.

Embodiment 7 FIG. A GaAs field effect transistor according to a seventh embodiment of the present invention will be described with reference to FIG. In the figure, the same reference numerals as those in FIG. 1 indicate the same or corresponding parts. In the manufacturing process of the field-effect transistor according to the present embodiment, first, as shown in FIG. 10A, an n-type channel layer 13 is formed on a GaAs substrate 1, and a gate electrode 6 is formed thereon. . Subsequently, using the gate electrode 6 as a mask, a p-type conductive region 200 is formed in a self-aligned manner by ion implantation.

Next, as shown in FIG. 10B, p-type ions such as Mg are implanted into the source electrode 7 below the gate electrode 6 by the oblique ion implantation technique as in the second embodiment. I do. As a result, the GaAs under the gate electrode 6
A p-type region 210 is formed in the substrate 1. Further, similarly to the second embodiment, the n-type impurity concentration of the source electrode 7 side region 300 becomes lower than the n-type impurity concentration of the drain electrode 8 side region 310, and the depth of the channel region 3d also decreases. Therefore, it becomes shallower than the drain electrode 8 side. Subsequently, an n ′ layer 4 and an n ⁺ layer 5 are formed by ion implantation.

Next, the source electrode 7 and the drain electrode 8
Is formed by vapor deposition or the like, and GaAs according to the present embodiment is formed.
The s field effect transistor is completed.

In the GaAs field effect transistor according to the present embodiment, the channel region 3 under the gate electrode 6
However, the channel region 3d has a lower concentration on the source electrode 7 side than on the drain electrode 8 side in addition to a structure that is shallower than the drain electrode 8 side on the source electrode 7 side from the approximate center of the gate electrode 6. Become. Therefore, even when the channel region 3 is pinched off on the source electrode 7 side, the drain electrode 8 side is not yet in the pinch off state. Therefore, the pinch-off voltage of the transistor is determined by Vp1, and the same effect as in the first embodiment can be obtained. Further, since there is no p-type semiconductor layer 200 below the gate electrode 6, generation of a hole current in the p-type semiconductor layer 200 and a parasitic bipolar effect can be suppressed. As a result, it is possible to suppress the increase (kink) of the current value on the high voltage side which occurs in the current-voltage characteristics (IV waveform) of the transistor. Further, the parasitic capacitance generated in the p-type semiconductor layer below the gate electrode 6 can be reduced.

Embodiment 8 FIG. Embodiment 8 A GaAs field effect transistor according to Embodiment 8 of the present invention will be described with reference to FIG. In the figure, the same reference numerals as those in FIG. 1 indicate the same or corresponding parts. This embodiment corresponds to the seventh embodiment.
In addition, this is a structure to which the electrode structure according to the third embodiment is applied. That is, as shown in FIG. 11A, after the GaAs substrate 1 and the n-type channel layer 13 are formed, the first electrode 6 is formed.
0, a gate electrode 6a composed of the second electrode 61 is formed, and then, as shown in FIG.
Is formed by selective implantation, and finally, as shown in FIG. 11C, the n ′ layer 4 and the n ⁺ layer 5 are formed by ion implantation.
Further, a source electrode 7 and a drain electrode 8 are formed,
The GaAs field effect transistor according to the present embodiment is completed.

In the GaAs field effect transistor according to the present embodiment, the depletion layer extending from the gate electrode 6 has a structure extending from the source electrode 7 side to the drain electrode 8 side. Even if the pinch is turned off, the drain electrode 8 side is not yet in the pinch-off state. Therefore, the pinch-off voltage of the transistor is determined by Vp1, and the same effect as in the first embodiment can be obtained. Further, since there is no p-type semiconductor layer 200 under the gate electrode 6, the p-type semiconductor layer 200
And the parasitic bipolar effect can be suppressed.

Embodiment 9 Embodiment 9 A GaAs field effect transistor according to Embodiment 9 of the present invention will be described with reference to FIG. In the figure, the same reference numerals as those in FIG. 1 indicate the same or corresponding parts. In the present embodiment, in particular, the structure according to the present invention is applied to a heterojunction transistor (HEMT).

First, as shown in FIG.
The super lattice buffer layer 42, i-G
aAs layer 43, n-AlGaAs layer 44, n-GaAs
After the formation of the layer 45, an isolation region 49 is formed by, for example, hydrogen ion implantation for element isolation.
Subsequently, the n-GaAs layer 45 is etched to obtain n-A
An opening 48 is provided to reach the lGaAs layer 44.
The width of the opening 48 is preferably about 1 μm. Subsequently, a p-GaAs layer 46 is formed on the entire surface by regrowth so as to fill the opening 48.

Next, as shown in FIG. 12B, a material layer for the gate electrode 47 is formed on the entire surface and then etched to form a gate having a stacked structure of the p-GaAs layer 46 and the gate electrode metal 47. The electrode 6 is manufactured. The gate electrode 6 is formed so as to have a structure extending from the opening 48 toward the drain electrode 9 as shown in FIG.

Next, as shown in FIG. 12C, a source electrode 7 and a drain electrode 8 are formed to complete the HEMT according to the present embodiment.

In the HEMT structure, the i-GaAs layer 43 and the n-type
-The transistor operation is performed by controlling the flow of electrons in the two-dimensional electron gas layer formed near the interface with the AlGaAs layer 44. In this case, the depletion layer extending from the p-GaAs layer 46 becomes a pn junction at the interface with the n-GaAs layer 45, and the depletion layer is unlikely to extend.
It will extend only into the lGaAs layer 44. Therefore,
The pinch-off voltage of the HEMT is such that the n-GaAs layer 45
It is determined by the pinch-off voltage of the region joined to the i-AlGaAs layer 44, that is, the depletion layer having the width of the opening 48. As a result, similarly to the first embodiment, the effective gate length can be reduced, and the pinch-off is performed only on the source electrode 7 side of the channel region. Improvements are also possible.

In the first to eighth embodiments, the n ′ layer 4
Although the embodiment using the LDD structure having the structure described above has been described, the present invention can be similarly applied even when the n ′ layer 4 is not formed. Further, in the first to ninth embodiments, the case where GaAs is mainly used as the compound semiconductor has been described, but the present invention relates to AlGaAs, GaN, InP, and the like.
The present invention is also applicable to a field effect transistor made of another compound semiconductor. Further, the structure in which the channel concentration is changed, the structure in which the channel depth is changed, and the method in which the elongation of the depletion layer is changed, which are described in the above embodiments, can be combined with each other and applied as a structure of a field effect transistor. is there.

[0070]

As is apparent from the above description, according to the compound semiconductor field effect transistor of the present invention,
Only on the source electrode side from the approximate center of the channel region,
Since the depletion layer has a pinch-off structure, electrons do not accumulate in the channel region of the depletion layer on the source electrode side as in the conventional structure, so that the transconductance can be improved.

Further, since the effective gate length when the channel region is pinched off can be made shorter than the actual gate electrode length, the gate length can be reduced while suppressing the occurrence of the short channel effect and the like.

Further, since the actual electrode area of the gate electrode is not reduced, it is possible to prevent an increase in gate resistance.

[Brief description of the drawings]

FIG. 1A is a cross-sectional view of a field-effect transistor according to a first embodiment of the present invention. (B) It is an enlarged view of a channel part.

FIG. 2 is a sectional view of a field-effect transistor according to a second embodiment of the present invention.

FIG. 3 is a cross-sectional view illustrating a manufacturing process of the field-effect transistor according to the second embodiment of the present invention;

FIG. 4 is a sectional view of a field-effect transistor according to a third embodiment of the present invention;

FIG. 5 is a sectional view of the manufacturing process of the field-effect transistor according to the third embodiment of the present invention;

FIG. 6 is a cross-sectional view illustrating a manufacturing process of the field-effect transistor according to the third embodiment of the present invention;

FIG. 7 is a cross-sectional view showing a manufacturing step of the field-effect transistor according to the fourth embodiment of the present invention.

FIG. 8 is a cross-sectional view showing a manufacturing step of the field-effect transistor according to the fifth embodiment of the present invention.

FIG. 9 is a cross-sectional view showing a manufacturing step of the field-effect transistor according to the sixth embodiment of the present invention.

FIG. 10 is a cross-sectional view illustrating a manufacturing step of the field-effect transistor according to the seventh embodiment of the present invention.

FIG. 11 is a sectional view showing the manufacturing process of the field-effect transistor according to the eighth embodiment of the present invention;

FIG. 12 is a cross-sectional view illustrating a manufacturing process of the heterojunction transistor according to the ninth embodiment of the present invention;

FIG. 13 is a cross-sectional view of a field-effect transistor having a conventional structure.

FIG. 14 is a carrier concentration distribution diagram near a channel region of a field-effect transistor having a conventional structure.

FIG. 15 is a cross-sectional view of a channel region at the time of pinch-off of a field-effect transistor having a conventional structure.

[Explanation of symbols]

1 GaAs semiconductor substrate, 2 p-type semiconductor layer, 3 n-type channel layer, 4 intermediate concentration n-type conductive layer (n ′ layer), 5
High-concentration n-type conductive layer (n ⁺ layer), 6 Schottky junction gate electrode (gate electrode), 7 source electrode, 8 drain electrode.

Claims (17)

[Claims] 1. A compound semiconductor field-effect transistor in which a source electrode, a drain electrode, and a gate electrode are formed between these electrodes on a conductive region, and the conductive region immediately below the gate electrode serves as a channel region. A compound semiconductor field-effect transistor, wherein a depletion layer extending from the electrode to the channel region blocks the channel region only in a source-side channel region closer to the source electrode than substantially in the center of the channel region. 2. The compound semiconductor field-effect transistor according to claim 1, wherein the conductive region is an n-type conductive layer formed on a p-type region, and the channel region is an n-type conductive layer directly below the gate electrode.
Type depletion layer, wherein the depletion layer is p-type only in the source-side channel region.
2. The compound semiconductor field effect transistor according to claim 1, wherein the compound semiconductor field effect pinch-off occurs. 3. The method according to claim 1, wherein the channel length of the channel region is 0.
2 to 1.0 μm, and the source side channel region is
3. The compound semiconductor field effect transistor according to claim 2, wherein the distance from the source electrode side electrode end is 20 to 40% of the channel length. 4. The compound semiconductor field effect transistor according to claim 1, wherein a channel depth of the source-side channel region is smaller than a channel depth of the drain-side channel region. 5. A step having a step substantially at the center of the bottom of the channel region, wherein the depth of the channel region is smaller on the source electrode side and the drain electrode side than the step. Item 5. The compound semiconductor field effect transistor according to item 4. 6. A step having a step portion substantially at the center of the surface portion of the channel region, wherein the depth of the channel region is smaller on the source electrode side than on the step portion and on the drain electrode side. The compound semiconductor field-effect transistor according to claim 4. 7. The compound semiconductor field effect transistor according to claim 1, wherein the source-side channel region has an n-type impurity concentration lower than that of the drain-side channel region. 8. An n-type impurity concentration in the channel region,
From the source electrode side to the drain electrode side,
8. The compound semiconductor field effect transistor according to claim 7, wherein the concentration is gradually increased. 9. A gate electrode in contact with the surface of the channel region, wherein the gate electrode includes a source-side gate electrode provided on the source electrode side from a substantially center of the channel region, and a drain-side gate electrode provided on the drain electrode side. The difference in work function between the semiconductor material in the channel region and the gate electrode, wherein the source-side gate electrode is larger than the drain-side gate electrode. 3. The compound semiconductor field effect transistor according to item 1. 10. The compound semiconductor field effect transistor according to claim 2, wherein a lower portion of said channel region is a semi-insulating region instead of said p-type region. 11. A hetero layer comprising a semi-insulating layer, an n-type electron supply layer, and an n-type contact layer sequentially laminated, and a channel layer formed near the interface of the semi-insulating layer with the n-type electron supply layer. In the junction transistor, the hetero-junction transistor may be configured such that the n-type contact layer reaches the n-type electron supply layer between the source electrode and the drain electrode provided on the n-type contact layer and between these electrodes. A gate electrode of a penetrating p-type electrode layer, wherein the gate electrode also extends on the n-type contact layer on the drain electrode side, and a depletion layer extending from the bottom of the p-type electrode layer provides A compound semiconductor field-effect transistor characterized by controlling a current flowing through a channel layer. 12. The semi-insulating layer is a semi-insulating GaAs layer, the n-type electron supply layer is an n-type Al _x Ga _{1 -x} As layer, and the n-type contact layer is an n-type GaAs layer. The compound semiconductor field effect transistor according to claim 11, wherein: 13. A substrate forming step of sequentially forming a p-type semiconductor layer and an n-type conductive layer on a semiconductor substrate, and forming a source electrode, a drain electrode, and a gate electrode between these electrodes on the n-type conductive layer, respectively. Forming an electrode using the n-type conductive layer immediately below the gate electrode as a channel region, and obliquely implanting a p-type impurity from a substantially center of the channel region into a region closer to the source electrode using the gate electrode as a mask. An implantation step of lowering the n-type impurity concentration of the source-side channel region to be lower than the n-type impurity concentration of the drain-side channel region. 14. The method of manufacturing a compound semiconductor field effect transistor according to claim 13, wherein said implanting step is a step of making the depth of said source side channel region smaller than that of said drain side channel region. . 15. The method according to claim 15, wherein the step of forming an electrode includes a step of forming a gate electrode including a source-side gate electrode and a drain-side gate electrode. Forming a protective film covering the upper surface of the side gate electrode and extending on the n-type conductive layer on the drain side; and depositing a source side gate electrode material layer on the entire surface, and then forming a film of the source side gate electrode material layer. 15. The method of manufacturing a compound semiconductor field-effect transistor according to claim 13, comprising: forming a source-side gate electrode with a thickness reduced from an upper surface. 16. The method according to claim 16, further comprising the step of: forming a step by etching a surface of the n-type conductive layer to provide a step substantially orthogonal to a set channel length direction after the substrate forming step; 14. The step of forming the gate electrode over the step.
3. The method for producing a compound semiconductor field effect transistor according to item 1. 17. A step of providing a step substantially orthogonal to a set channel length direction at the bottom of the n-type conductive layer after the substrate forming step to form a step, wherein the step includes A step of selectively injecting an n-type impurity into the n-type conductive layer so that a channel depth on the electrode side is greater than a channel depth on the source electrode side; 15. The step of forming the gate electrode so as to cover the gate electrode.
3. The method for producing a compound semiconductor field effect transistor according to item 1.