JP2011071307A - Field effect transistor and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a field effect transistor hard to get damaged even if high voltage is applied. <P>SOLUTION: The field effect transistor includes a substrate 1, a channel layer 3 and a barrier layer 4, a source electrode 6, a gate electrode 7 and a drain electrode 8 which are separately provided on the barrier layer 4 in this order. A first n-type impurity diffusion region 12 is provided immediately below the source electrode 6. A second n-type impurity diffusion region 13 is provided immediately below the drain electrode 8. A third n-type impurity diffusion region 15 is provided in the channel layer 3 under the second n-type impurity diffusion region and the channel layer 3 and the barrier layer 4 on the side of the gate electrode of the second n-type impurity diffusion region. The third n-type impurity diffusion region 15 has a lower n-type impurity concentration than that of the second n-type impurity diffusion region 13. Concentration of an electric field exceeding a breakdown strength is thus prevented from occurring in the barrier layer 4 and the channel layer 3 when voltage is applied between the gate electrode and the drain electrode. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a field effect transistor and a manufacturing method thereof.

  High-voltage heterojunction field effect transistors (HFETs) using group III nitride semiconductors are widely studied as high-frequency power switching elements having high breakdown field strength and high thermal conductivity (for example, Patent Document 1). reference).

FIG. 8 shows a schematic cross section of a typical n-channel HFET using a group III nitride semiconductor.
In the transistor of FIG. 8, a channel layer 103 is formed on a substrate 101, and a barrier layer 104 having a larger band gap than the channel layer 103 is formed thereon. A heterojunction is formed at the interface between the channel layer 103 and the barrier layer 104 having different band gaps, and a two-dimensional electron gas in which electrons accumulate at a high concentration in the vicinity of the heterojunction interface due to spontaneous polarization and piezoelectric polarization. 117 is present. The sheet electron concentration of the two-dimensional electron gas 117 varies depending on the material of the channel layer 103 and the barrier layer 104, but a sheet electron concentration of, for example, about 1 × 10 ¹³ / cm ² is generated.
A source electrode 106, a drain electrode 108, and a gate electrode 107 are formed on the barrier layer 104, and an insulating film 110 is formed so as to cover the barrier layer 104.
In addition, the gate electrode 107 has a field plate structure in order to reduce electric field concentration.
In this transistor, the first n + type diffusion region 112 is formed in the barrier layer 104 and the channel layer 103 immediately below the source electrode 106 in order to lower the forward voltage during operation and to obtain a good ohmic contact. The second n + type diffusion region 113 is formed in the barrier layer 104 and the channel layer 103 immediately below the drain electrode 108.

  In the transistor as shown in FIG. 8, the current between the source electrode 106 and the drain electrode 108 flows mainly through the two-dimensional electron gas 117 using electrons as carriers, and changes the voltage applied to the gate electrode 107. Can be switched on / off. Specifically, for example, when the source electrode 106 is grounded and a positive voltage is applied to the drain electrode 108 and no voltage is applied between the source electrode 106 and the gate electrode 107, electrons in the source electrode 106 are transferred to the barrier layer. The transistor can be turned on by flowing the two-dimensional electron gas 117 formed at the interface between the channel 104 and the channel layer 103 to the drain electrode 108. Further, for example, when the source electrode 106 is grounded and a positive voltage is applied to the drain electrode 108 and a voltage of about −1 V to −30 V is applied to the gate electrode 107, the electrons of the gate electrode 107 and the two-dimensional electron gas 117 are applied. The two-dimensional electron gas 117 under the gate electrode 107 is depleted due to the interaction. As a result, electrons flowing from the source electrode 106 to the drain electrode 108 cannot flow through the two-dimensional electron gas 117 below the gate electrode 107. Accordingly, current between the source electrode 106 and the drain electrode 108 can be reduced or prevented from flowing, and the transistor can be turned off.

JP 2004-200248 A

However, in a field effect transistor having a structure as shown in FIG. 8, when a high voltage is applied between the source electrode, the gate electrode, and the drain electrode, carriers may increase due to the electric field applied to the inside of the element, and the element may be broken. is there. The cause of this carrier increase is not clear, but one of the causes is that when a high voltage is applied, a portion where an electric field strength exceeding the breakdown strength is locally generated inside the device, and avalanche breakdown occurs in this portion. It is thought to occur.
The present invention has been made in view of such circumstances, and provides a field effect transistor that is not easily broken even when a high voltage is applied.

  According to the present invention, “a channel layer and a barrier layer are provided in this order on a substrate, and a source electrode, a gate electrode and a drain electrode are provided on the barrier layer so as to be spaced apart in this order. A first n-type impurity diffusion region is provided in the barrier layer and the channel layer, and a second n-type impurity diffusion region is provided in the barrier layer and the channel layer immediately below the drain electrode. A third n-type impurity diffusion region is provided in the channel layer and the barrier layer on the gate electrode side of the channel layer below the impurity diffusion region and the second n-type impurity diffusion region, and the first n-type The impurity diffusion region and the third n-type impurity diffusion region are provided in a portion excluding the barrier layer and the channel layer immediately below the lower surface closest to the channel layer of the gate electrode. The third n-type impurity diffusion region has an n-type impurity concentration lower than that of the second n-type impurity diffusion region, and the third n-type impurity diffusion region is formed between the gate electrode and the drain electrode. There is provided a field effect transistor characterized by suppressing the occurrence of electric field concentration exceeding the dielectric breakdown strength in the barrier layer and the channel layer when a voltage is applied therebetween.

  In a conventional field effect transistor having a heterojunction as shown in FIG. 8, when a high voltage is applied, particularly when the sheet electron concentration of the two-dimensional electron gas 117 is small, breakdown occurs in the channel layer on the gate electrode side of the drain electrode. Prone to occur. The cause is considered as follows. First, in a state where the transistor is off, that is, in a state where carrier depletion occurs under the gate electrode, the carrier depletion under the gate electrode spreads to the drain electrode side by the voltage applied to the drain electrode, and this depletion is reduced. It is thought that it reaches the vicinity of the drain electrode. For this reason, it is considered that the region having a high sheet carrier concentration between the gate electrode and the drain electrode is only the barrier layer and the channel layer on the gate electrode side of the drain electrode in which the high concentration n-type impurity diffusion region is formed. As a result, it is considered that the voltage applied between the gate electrode and the drain electrode is locally concentrated in a region where the sheet carrier concentration in the vicinity of the drain electrode is rapidly increased, so that dielectric breakdown is likely to occur.

  According to the field effect transistor of the present invention, the third n-type impurity diffusion region containing the n-type impurity at a constant concentration is provided around the region where dielectric breakdown is likely to occur in the conventional field effect transistor. Specifically, a third n-type impurity diffusion region having an n-type impurity concentration lower than that of the second n-type impurity diffusion region is provided so as to surround the second n-type impurity diffusion region. This can prevent the carrier depletion under the gate electrode from spreading to the vicinity of the drain electrode, and the sheet carrier concentration in the portion where the third n-type impurity diffusion region is provided can be made substantially constant. As a result, the voltage applied between the gate electrode and the drain electrode is applied substantially uniformly to the third n-type impurity diffusion region. As a result, it is possible to suppress the occurrence of a portion where a high electric field strength is locally generated, and it is possible to make dielectric breakdown difficult to occur. In addition, electric field concentration applied to a portion where dielectric breakdown is likely to occur can be reduced. In addition, the breakdown voltage (breakdown voltage) of the transistor can be improved.

It is a schematic sectional drawing which shows the structure of the field effect transistor of one Embodiment of this invention. It is a schematic sectional drawing which shows the structure of the field effect transistor of one Embodiment of this invention. It is a schematic sectional drawing which shows the structure of the field effect transistor of one Embodiment of this invention. It is a schematic sectional drawing which shows the structure of the field effect transistor of one Embodiment of this invention. It is a schematic sectional drawing which shows the structure of the field effect transistor of one Embodiment of this invention. It is explanatory drawing which shows the result of the simulation about the conventional field effect transistor. It is explanatory drawing which shows the result of the simulation about the field effect transistor of one Embodiment of this invention. It is a schematic sectional drawing which shows the structure of the conventional field effect transistor.

1. About the field effect transistor of the present invention In the field effect transistor of the present invention, a channel layer and a barrier layer are provided in this order on a substrate, and a source electrode, a gate electrode and a drain electrode are spaced apart in this order on the barrier layer. A first n-type impurity diffusion region is provided in the barrier layer and the channel layer immediately below the source electrode, and a second n-type impurity diffusion is provided in the barrier layer and the channel layer immediately below the drain electrode. A third n-type impurity diffusion region is provided in the channel layer below the second n-type impurity diffusion region and the channel layer and the barrier layer on the gate electrode side of the second n-type impurity diffusion region. A first n-type impurity diffusion region and a third n-type impurity diffusion region are formed on a lower surface closest to the channel layer of the gate electrode. The third n-type impurity diffusion region provided in a portion excluding the barrier layer and the channel layer immediately below has a lower n-type impurity concentration than the second n-type impurity diffusion region, and the third n-type impurity diffusion region The impurity diffusion region is characterized by suppressing the occurrence of electric field concentration exceeding the dielectric breakdown strength in the barrier layer and the channel layer when a voltage is applied between the gate electrode and the drain electrode.

In the present invention, a field effect transistor refers to a transistor that controls carriers in a semiconductor layer under a gate electrode by a voltage (charge) applied to the gate electrode and increases or decreases a current between the source electrode and the drain electrode. The field effect transistor of the present invention may be a heterojunction field effect transistor.
In the present invention, the substrate is not particularly limited as long as it is a substrate on which a semiconductor layer such as a channel layer can be formed. For example, a substrate such as Si, Si, GaN, SiC or sapphire doped with n-type impurities.
In the present invention, the channel layer is not particularly limited as long as it is a layer provided on the substrate and through which a current between the source electrode and the drain electrode can flow. For example, it is a group III nitride semiconductor, and more specifically, For example, GaN, AlGaN, InGaN and the like.

In the present invention, the barrier layer is not particularly limited as long as it is a layer provided on the channel layer and capable of forming a heterojunction at the interface with the channel layer. The barrier layer may have a wider band gap than the channel layer. The barrier layer is, for example, a group III nitride semiconductor, and more specifically, AlN, AlGaN, InGaN, or the like.
In the present invention, the source electrode, the gate electrode, and the drain electrode are not particularly limited as long as they can form the field effect transistor of the present invention.

In the present invention, the first n-type impurity diffusion region is not particularly limited as long as it is a region in which an n-type impurity is diffused in the barrier layer and the channel layer immediately below the source electrode.
In the present invention, the n-type impurity is not particularly limited as long as it is an impurity (donor) that can increase the conductivity of the barrier layer and the channel layer by diffusing into the barrier layer and the channel layer. In the case where the channel layer is made of a group III nitride semiconductor, Si or the like is used. Further, the n-type impurity concentration refers to the concentration of n-type impurities. The n-type pure substance concentration is considered to be almost the same as the concentration of electrons as carriers.
In the present invention, the second n-type impurity diffusion region is not particularly limited as long as it is a region in which an n-type impurity is diffused in the barrier layer and the channel layer immediately below the drain electrode.

  In the present invention, the third n-type impurity diffusion region is a region in which an n-type impurity is diffused in the barrier layer and the channel layer, and is provided so as to surround the second n-type impurity diffusion region. Further, the third n-type impurity diffusion region includes a part of the interface between the channel layer and the barrier layer on the gate electrode side of the second n-type impurity diffusion region, and more than the second n-type impurity diffusion region. Has a low n-type impurity concentration.

2. Embodiment of Field Effect Transistor of the Present Invention In the field effect transistor of the present invention, the third n-type impurity diffusion region has a distance between the lower surface closest to the channel layer of the gate electrode and the lower surface of the drain electrode. 100, the interface between the channel layer provided with the third n-type impurity diffusion region on the gate electrode side of the second n-type impurity diffusion region and the barrier layer has a width of 10 to 80 It may be provided as follows.
With this configuration, it is possible to suppress the occurrence of a portion where high electric field strength is efficiently applied while maintaining the transistor characteristics, and it is possible to suppress the occurrence of dielectric breakdown.

  In the transistor of the present invention, the channel layer and the barrier layer may be made of a group III nitride semiconductor. Group III nitride semiconductors have high breakdown field strength and high thermal conductivity. For this reason, it can be set as the high frequency power switching element which has high dielectric breakdown electric field strength and high thermal conductivity. In addition, the transistor (HFET) particularly useful for high power / high frequency applications can be obtained.

In the transistor of the present invention, the first n-type impurity diffusion region and the second n-type impurity diffusion region have an n-type impurity concentration of 1.0 × 10 ¹⁴ cm ^{−2 to} 1.0 × 10 ¹⁶ cm ^−2. You may have. Thereby, the electrical resistance between the source or drain electrode and the channel layer can be reduced.

In the transistor of the present invention, the third n-type impurity diffusion region is 1.0 × 10 ^x-4 when the n-type impurity concentration of the second n-type impurity diffusion region is 1.0 × 10 ^x cm ^−2. It may have an n-type impurity concentration of cm ^{−2 to} 1.0 × 10 ^x−0.5 cm ⁻² . As a result, the conductivity of the third n-type impurity diffusion region can be prevented from becoming too high, and the electric field density is locally generated in the channel layer on the gate electrode side of the third n-type impurity diffusion region. It can suppress becoming high.

  In the transistor of the present invention, the channel layer includes an upper channel layer and a lower channel layer, and the upper channel layer may have a smaller band gap than any of the barrier layer and the lower channel layer. As a result, the current flowing between the source electrode and the drain electrode can be concentrated in the upper channel layer and leakage current can be reduced.

  In the transistor of the present invention, the substrate may be a conductive substrate. Further, the conductive substrate may be electrically connected to the source electrode. As a result, when a voltage is applied between the source electrode and the drain electrode, a vertical electric field is generated between the substrate and the drain electrode, and the electric field strength applied to the channel layer below the drain electrode is increased. As a result, the electric field between the source electrode and the gate electrode and the drain electrode can be relaxed. As a result, the electric field strength applied to the channel layer on the gate electrode side of the drain electrode, which easily causes dielectric breakdown, can be reduced, and the dielectric breakdown can be suppressed.

  In the transistor of the present invention, the barrier layer or the channel layer may have a recess structure, and the gate electrode may be provided on the recess of the recess structure. With this configuration, the transistor of the present invention can obtain good pinch-off characteristics. In addition, when the channel layer has a recess structure, a normally-off transistor can be obtained.

  The transistor of the present invention may further include an insulator layer between the gate electrode and the barrier layer or the channel layer. With this configuration, good gate insulation characteristics can be obtained.

  In the transistor of the present invention, the insulator layer may include a plurality of layers having different dielectric constants. With this configuration, good gate insulation characteristics can be obtained.

  The field effect transistor manufacturing method of the present invention includes a step of forming a channel layer and a barrier layer in this order on a substrate, and a first n-type impurity diffusion region and a third n-type in the channel layer and the barrier layer. A step of forming the impurity diffusion regions apart from each other; and a third n-type impurity diffusion region which is a part of the third n-type impurity diffusion region and is provided on the lower side and the first n-type impurity diffusion region side. Forming a second n-type impurity diffusion region in a certain part; forming a source electrode immediately above the first n-type impurity diffusion region; and forming a drain electrode directly above the second n-type impurity diffusion region. Neither the first n-type impurity diffusion region nor the third n-type impurity diffusion region is formed between the forming step and the first n-type impurity diffusion region and the third n-type impurity diffusion region. The channel layer and the barrier Forming a gate electrode immediately above the first n-type impurity diffusion region, wherein the third n-type impurity diffusion region has a lower n-type impurity concentration than the second n-type impurity diffusion region. .

3. Embodiments of the Field Effect Transistor of the Present Invention Hereinafter, embodiments of the present invention will be described with reference to the drawings. The configurations shown in the drawings and the following description are merely examples, and the scope of the present invention is not limited to those shown in the drawings and the following description.
1 to 5 are schematic cross-sectional views each showing the structure of a field effect transistor according to an embodiment of the present invention.

3-1. Field Effect Transistor As illustrated in FIG. 1, in the field effect transistor 20 of this embodiment, a channel layer 3 and a barrier layer 4 are provided in this order on a substrate 1, and a source electrode 6 and a gate electrode 7 are provided on the barrier layer 4. And the drain electrode 8 are provided separately in this order, the first n-type impurity diffusion region 12 is provided in the barrier layer 4 and the channel layer 3 immediately below the source electrode 6, and the barrier layer 4 immediately below the drain electrode 8 And the second n-type impurity diffusion region 13 is provided in the channel layer 3, and the channel layer 3 below the second n-type impurity diffusion region 13 and the gate electrode 7 side of the second n-type impurity diffusion region 13 are provided. A third n-type impurity diffusion region 15 is provided in the channel layer 3 and the barrier layer 4, and the first n-type impurity diffusion region 12 and the third n-type impurity diffusion region 15 are provided in the gate electrode 7. The third n-type impurity diffusion region 15 is provided in a portion excluding the barrier layer 4 and the channel layer 3 immediately below the lower surface closest to the channel layer 3, and the n-type impurity is lower than the second n-type impurity diffusion region 13. The third n-type impurity diffusion region 15 has a concentration, and when the voltage is applied between the gate electrode 7 and the drain electrode 8, an electric field concentration exceeding the dielectric breakdown strength occurs in the barrier layer 4 and the channel layer 3. It is characterized by suppressing this.

Further, the field effect transistor 20 of the present embodiment may have the insulating film 10 on the barrier layer 4.
Further, the field effect transistor 20 of the present embodiment may include an insulator layer 25 between the gate electrode 7 and the barrier layer 4 or the channel layer 3 as shown in FIG.
Further, the field effect transistor 20 of the present embodiment may be a heterojunction field effect transistor.

3-2. Substrate The substrate 1 is not particularly limited as long as it is a substrate on which a semiconductor layer such as the channel layer 3 can be formed. The substrate 1 may be a conductive substrate or a high resistance substrate. For example, a substrate such as Si (n ⁺ -Si substrate) doped with an n-type impurity, Si, GaN, SiC, or sapphire.
The substrate 1 may be a conductive substrate. Further, the substrate 1 and the source electrode 6 may be electrically connected. As a result, a voltage is applied between the substrate 1 and the drain electrode 8, and the electric field applied between the gate electrode 7 and the drain electrode 8 can be relaxed. As a result, the occurrence of dielectric breakdown can be suppressed. Further, the source electrode 6 and the substrate 1 can be grounded. Further, when the field effect transistor 20 is packaged by electrically connecting the substrate 1 and the source electrode 6, the device can be reduced in size.

3-3. Channel Layer The channel layer 3 is not particularly limited as long as it is provided on the substrate 1 and can flow a current between the source electrode 6 and the drain electrode 8. The carrier may be an electron. The channel layer 3 may be made of a group III nitride semiconductor such as GaN, Al _x Ga _1-x N, In _x Ga _1-x N, or the like. For example, x may be greater than 0 and 0.5 or less. For example, x may be 0.001 or more and 0.1 or less. Since the group III nitride semiconductor has high dielectric breakdown strength and high thermal conductivity, it can be a high-frequency power switching element.

  Although the thickness of the channel layer 3 is not specifically limited, For example, it is 1-10 micrometers, More preferably, it is 2 micrometers-5 micrometers.

  The channel layer 3 may have a smaller band gap than the barrier layer 4. As a result, the two-dimensional electron gas 17 can be formed at the interface between the channel layer 3 and the barrier layer 4. Further, the current between the source electrode 6 and the drain electrode 8 can mainly flow through the two-dimensional electron gas 17. The transistor can be turned on and off by controlling the two-dimensional electron gas 17 with a voltage applied to the gate electrode.

  The channel layer 3 may be composed of an upper channel layer 22 and a lower channel layer 23 as shown in FIG. 2, and the upper channel layer 22 has a smaller band gap than either the barrier layer 4 or the lower channel layer 23. May be. As a result, a band structure in which most of the electrons serving as carriers are confined in the upper channel layer 22 can reduce leakage current due to electrons moving through the lower channel layer 23 and the substrate 1. As a result, the current flowing between the source electrode 6 and the drain electrode 8 can be concentrated in the upper channel layer 22.

The material of the upper channel layer 22 is not particularly limited, but may be made of, for example, a group III nitride semiconductor such as GaN, Al _x Ga _1-x N, In _x Ga _1-x N, or the like. For example, x may be larger than 0 and smaller than 0.5. For example, x may be 0.001 or more and 0.1 or less.
Further, the thickness of the upper channel layer 22 is not particularly limited, and is, for example, 0.01 μm or more and 0.1 μm or less. For example, it is 0.01 micrometer or more and 0.03 micrometer or less. Further, the thickness of the upper channel layer may be smaller than the thickness of the lower channel layer. As a result, electrons that are carriers can be confined in a narrower range.

The material of the lower channel layer 23 is not particularly limited, but may be made of, for example, a group III nitride semiconductor such as Al _x Ga _1-x N, In _x Ga _1-x N, or the like. For example, x may be not less than 0.01 and not more than 0.95. For example, x may be 0.02 or more and 0.3 or less. For example, when the upper channel layer 22 is made of GaN, the lower channel layer 23 may be made of Al _x Ga _1-x N (0.1 ≦ x ≦ 0.3).
For example, when the upper channel layer 22 is made of GaN or Al _x Ga _1-x N and the lower channel layer 23 is Al _y Ga _1-y N, y may be larger than x. In this case, the band gap of the upper channel layer is larger than the band gap of the lower channel layer. Moreover, 0.02 ≦ (y−x) ≦ 0.3 may be satisfied.
The thickness of the lower channel layer 23 is not particularly limited, but is, for example, 1 to 10 μm, and more preferably 2 to 5 μm.

  Further, the channel layer 3 may have a recess structure as shown in FIG. In addition, by forming the insulator layer 25 between the channel layer 3 and the gate electrode 7, a normally-off transistor can be obtained. In the transistor as shown in FIG. 5, the two-dimensional electron gas is often not formed in the channel layer 3 immediately below the gate electrode 7. Therefore, when no voltage is applied to the gate electrode 7, the source electrode 6 and the drain electrode 8 are not connected. Almost no current flows. Further, by applying a positive voltage to the gate electrode 7, an electron layer can be formed in the channel layer immediately below the gate electrode 7, and the transistor can be turned on.

  The channel layer 3 can be formed on the substrate 1 by CVD, for example.

  When the substrate 1 is a conductive substrate, the length between the substrate 1 and the drain electrode 8 is set to a length between the source electrode 6 and the drain electrode 8 in order to prevent leakage current between the substrate 1 and the drain electrode 8. It can be made longer than the length between. Specifically, the thickness of the channel layer 3 can be made sufficiently thicker than the length between the source electrode 6 and the drain electrode 8. Accordingly, the leakage current can be reduced, and when an off voltage is applied to the gate electrode 7, the current flowing to the drain electrode 8 can be reduced or prevented from flowing.

3-4. Barrier layer The barrier layer 4 is not particularly limited as long as it is provided on the channel layer 3 and forms a heterojunction at the interface with the channel layer 3. The barrier layer 4 may be made of a group III nitride semiconductor, for example, Al _x Ga _1-x N, In _x Ga _1-x N, or the like. For example, x may be 0.05 or more and 0.9 or less. For example, x may be 0.1 or more and 0.5 or less. Since the group III nitride semiconductor has high dielectric breakdown strength and high thermal conductivity, it can be a high-frequency power switching element. For example, when the channel layer 3 is made of GaN or Ga _x Al _1-x N and the barrier layer 4 is made of Ga _y Al _1-y N, y may be larger than x, and 0.02 ≦ (y -X) ≦ 0.3 may be sufficient. As a result, the band gap of the barrier layer 4 can be made larger than the band gap of the channel layer 3.
The barrier layer 4 may have a larger band gap than the channel layer 3. As a result, the two-dimensional electron gas 17 can be formed at the interface with the channel layer 3. In the AlGaN / GaN heterojunction, a sheet electron concentration of about 1 × 10 ¹³ / cm ² is generated due to spontaneous polarization and piezoelectric polarization. Further, most of the current flowing between the source electrode 6 and the drain electrode 8, that is, electrons serving as carriers can be passed through the channel layer 3.

Although the thickness of the barrier layer 4 is not specifically limited, For example, it can be 0.01 micrometer or more and 0.1 micrometer or less. For example, it can be 0.015 μm or more and 0.07 μm or less.
Further, the barrier layer 4 may have a recess structure as shown in FIG. As a result, the field effect transistor 20 having good pinch-off characteristics can be obtained.

  The barrier layer 4 can be formed on the channel layer 3 by CVD, for example.

3-5. Source electrode The source electrode 6 is provided on the barrier layer 4 so as to be spaced apart in order of the source electrode 6, the gate electrode 7, and the drain electrode 8, and is provided immediately above the first n-type impurity diffusion region 12. If it is an electrode, it will not specifically limit. As the metal used to form the source electrode 6, for example, at least one metal selected from Ti, Zr, Hf, Al, AlSi, W, WN, Au, and Pt can be used. The source electrode 6 can be, for example, an electrode made of Hf / Al / Au or Ti / Pt / Au.
Although the width | variety of the source electrode 6 is not specifically limited, For example, it can be 10 micrometers or more and 1 mm or less.
The source electrode 6 can be formed by a vacuum deposition method, a sputtering method, or the like.
In the case where the insulating film 10 is formed on the barrier layer 4, the insulating film 10 in a portion where the source electrode 6 is to be formed is removed by etching so that the source electrode 6 is in contact with the barrier layer 4. it can.
Further, the source electrode 6 can be heat-treated after being formed by a vacuum deposition method, a sputtering method, or the like. Although heat processing is not specifically limited, For example, it can carry out at 550 degreeC for 1 minute. As a result, the source electrode 6 and the channel layer 3 can be ohmically connected via the first n-type impurity diffusion layer 12.

3-6. Drain electrode The drain electrode 8 is provided on the barrier layer 4 so as to be spaced apart in order of the source electrode 6, the gate electrode 7, and the drain electrode 8, and is provided immediately above the second n-type impurity diffusion region 13. If it is an electrode, it will not specifically limit. As the metal used to form the drain electrode 8, for example, at least one metal selected from Ti, Zr, Hf, Al, AlSi, W, WN, Au, and Pt can be used. The drain electrode 8 can be, for example, an electrode made of Hf / Al / Au or Ti / Pt / Au.
Although the width | variety of the drain electrode 8 is not specifically limited, For example, they are 1 micrometer or more and 5 micrometers or less.
The drain electrode 8 can be formed by a vacuum deposition method, a sputtering method, or the like.
In addition, when the insulating film 10 is formed on the barrier layer 4, the insulating film 10 in a portion where the drain electrode 8 is to be formed is removed by etching so that the drain electrode 8 is in contact with the barrier layer 4. it can.
Further, the drain electrode 8 can be heat-treated after being formed by a vacuum deposition method, a sputtering method, or the like. Although heat processing is not specifically limited, For example, it can carry out at 550 degreeC for 1 minute. Accordingly, the drain electrode 8 and the channel layer 3 can be ohmically connected via the second n-type impurity diffusion layer 12.

3-7. Gate electrode The gate electrode 8 is not particularly limited as long as it is an electrode provided on the barrier layer 4 so as to be spaced apart in order of the source electrode 6, the gate electrode 7 and the drain electrode 8. The barrier layer 4 and the channel layer 3 immediately below the gate electrode 8 are provided with a first n-type impurity diffusion region 12, a second n-type impurity diffusion region 13, and a third n-type impurity diffusion region 15. It is not done.
Further, the gate electrode 7 and the drain electrode 8 may be provided so as to have a constant interval. In addition, the lower surface of the gate electrode 7 closest to the channel layer 3 and the lower surface of the drain electrode 8 may be provided so as to have a certain distance.
The gate electrode 8 may be provided in contact with the barrier layer 4 as shown in FIGS. Further, as shown in FIGS. 3 and 5, it may be provided on the barrier layer 4 or the channel layer 3 through the insulating film 10 or the insulating layer 25. Thereby, good gate insulation characteristics can be obtained.

Moreover, the gate electrode 7 may be provided on the recessed part of the barrier layer 4 which has a recess structure like FIG. As a result, good pinch-off characteristics can be obtained. The recess structure as shown in FIG. 4 can be formed by removing a part of the barrier layer 4 and a part of the insulating film 10 by etching.
Further, the gate electrode 7 may be provided on the concave portion of the channel layer 3 having a recess structure as shown in FIG. As a result, good gate insulation characteristics can be obtained, and a normally-off transistor can be formed. The recess structure can be formed by etching.
In addition, the gate electrode 7 may have a shape (field plate structure) protruding like an eaves on the insulating film 10 formed on the barrier layer 4 as shown in FIGS. 1, 2, and 5. Thereby, the electric field concentration between the gate electrode 7 and the drain electrode 8 can be relaxed.

The gate electrode 7 can be formed using at least one metal selected from Ti, Zr, Hf, Al, AlSi, W, WN, Au, and Pt. The gate electrode 7 can be formed by a vacuum deposition method or a sputtering method.
In the case where the insulating film 10 is formed on the barrier layer 4, the insulating film 10 in a portion where the gate electrode 7 is to be formed is removed by etching so that the gate electrode 7 is in contact with the barrier layer 4. it can.

  The gate electrode 7 may be provided so that the width in the direction along with the source electrode 6, the gate electrode 7, and the drain electrode 8 has a width of 10 μm to 1 mm. Further, the distance between the lower surface closest to the channel layer 3 of the gate electrode 7 and the lower surface of the drain electrode 8 (interval indicated by Y in the drawing) may be 5 μm or more and 20 μm or less.

3-8. First n-type impurity diffusion region The first n-type impurity diffusion region 12 is provided in the barrier layer 4 and the channel layer 3 immediately below the source electrode 6. By providing the first n-type impurity diffusion region 12, the source electrode 6 can be ohmically connected to the channel layer 3. The first n-type impurity diffusion region 12 is not formed in the barrier layer 4 and the channel layer 3 immediately below the lower surface closest to the channel layer 3 included in the gate electrode 7. Further, substantially the entire barrier layer 4 and channel layer 3 immediately below the lower surface closest to the channel layer 3 of the gate electrode 7 may be substantially free of n-type impurities and p-type impurities. . Further, the first n-type impurity diffusion region 12 may be provided substantially only in the barrier layer 4 and the channel layer 3 immediately below the source electrode 6.
The first n-type impurity diffusion region 12 may have an n-type impurity concentration of 1.0 × 10 ¹⁴ cm ^{−2 to} 1.0 × 10 ¹⁶ cm ⁻² . As a result, the source electrode 6 and the channel layer 3 can be ohmically connected.

Further, the n-type impurity contained in the first n-type impurity diffusion region 12 is not particularly limited, but is Si, Ge, Sn, etc. when the barrier layer 4 and the channel layer 3 are group III nitrides.
The first n-type impurity diffusion region 12 can be formed by ion-implanting n-type impurities into the barrier layer 4 and the channel layer 3. Further, the first n-type impurity diffusion region 12 can be activated by performing a heat treatment after the ion implantation. Although the temperature of heat processing is not specifically limited, For example, it can be 1000 degreeC-1200 degreeC. Thereby, the contact resistance between the source electrode 6 and the channel layer 3 can be reduced.

The first n-type impurity diffusion region 12 can be formed by thermal diffusion of n-type impurities, for example, Si diffusion. Specifically, an Si layer is formed on the barrier layer 4 forming the first n-type impurity diffusion region 12, and Si of this Si layer is diffused to the barrier layer 4 and the channel layer 3 by heat treatment. A first n-type impurity diffusion region 12 can be formed. The conditions for this heat treatment are not particularly limited, but can be, for example, 1100 degrees and 2 minutes.
For example, when the channel layer 3 includes the upper channel layer 22 and the lower channel layer 23 as shown in FIGS. 2 and 5, the first n-type impurity diffusion region 12 is formed so as not to reach the lower channel layer 23. be able to. As a result, most of the electrons, which are carriers flowing between the source electrode 6 and the drain electrode 8, can flow to the upper channel layer 22.

3-9. Second n-type impurity diffusion region The second n-type impurity diffusion region 13 is provided in the barrier layer 4 and the channel layer 3 immediately below the drain electrode 8. By providing the second n-type impurity diffusion region 13, the drain electrode 8 can be ohmically connected to the channel layer 3. Further, the second n-type impurity diffusion region 13 may not be formed in the barrier layer 4 and the channel layer 3 immediately below the lower surface closest to the channel layer 3 of the gate electrode 7. Further, the second n-type impurity diffusion region 13 may be provided substantially only in the barrier layer 4 and the channel layer 3 immediately below the drain electrode 8.
Second n-type impurity diffusion region 13 may have an n-type impurity concentration of 1.0 × 10 ¹⁴ cm ^{−2 to} 1.0 × 10 ¹⁶ cm ⁻² . As a result, the drain electrode 8 and the channel layer 3 can be ohmically connected.

The n-type impurity contained in the second n-type impurity diffusion region 13 is not particularly limited, but is Si, Ge, Sn or the like when the barrier layer 4 and the channel layer 3 are group III nitride. The n-type impurities contained in the first n-type impurity diffusion region 12, the second n-type impurity diffusion region 13, and the third n-type impurity diffusion region 15 may be the same element. Good.
The second n-type impurity diffusion region 13 may be formed by ion-implanting n-type impurities into part of the barrier layer 4 and the channel layer 3 in which the third n-type impurity diffusion region 15 is formed. it can. This makes it possible to make a difference in the n-type impurity concentration between the third n-type impurity diffusion region 15 and the second n-type impurity diffusion region 13. Further, the third n-type impurity diffusion region can be configured to surround the second n-type impurity diffusion region. That is, first, the third n-type impurity diffusion region 15 is formed with a relatively low n-type impurity concentration by ion implantation or thermal diffusion of n-type impurities, and then a part of the third n-type impurity diffusion region 15 is formed. The second n-type impurity diffusion region 13 having a higher n-type impurity concentration than the third n-type impurity diffusion region 15 can be formed by ion-implanting the n-type impurity into the first n-type impurity. Similarly, when the second n-type impurity diffusion region 13 is formed by thermal diffusion of n-type impurities described later, the concentration difference of the n-type impurities can be similarly set.

  Further, the second n-type impurity diffusion region 13 can be activated by performing a heat treatment after the ion implantation. Further, the heat treatment after the ion implantation may be performed simultaneously on the first n-type impurity diffusion region 12, the second n-type impurity diffusion region 13, and the third n-type impurity diffusion region 15. Although the temperature of heat processing is not specifically limited, For example, it can be 1000 degreeC-1200 degreeC. This can reduce the contact resistance between the drain electrode 8 and the channel layer 3.

The second n-type impurity diffusion region 13 can be formed by thermal diffusion of n-type impurities, for example, Si diffusion. Specifically, a Si layer is formed on the barrier layer 4 in which the third n-type impurity diffusion region 15 is formed, and a part of the third n-type impurity diffusion region 15 is formed by heat-treating Si of the Si layer. Thus, the second n-type impurity diffusion region 13 can be formed. The conditions for this heat treatment are not particularly limited, but can be, for example, 1100 degrees and 2 minutes.
The second n-type impurity diffusion region 13 can be formed using epitaxial growth.
For example, when the channel layer 3 includes the upper channel layer 22 and the lower channel layer 23 as shown in FIGS. 2 and 5, the second n-type impurity diffusion region 13 is formed so as not to reach the lower channel layer 23. be able to. As a result, most of the electrons, which are carriers flowing between the source electrode 6 and the drain electrode 8, can flow to the upper channel layer 22.

3-10. Third n-type impurity diffusion region The third n-type impurity diffusion region 15 includes the channel layer 3 below the second n-type impurity diffusion region 13 and the gate electrode 7 side of the second n-type impurity diffusion region 13. The channel layer 3 and the barrier layer 4 are provided. The third n-type impurity diffusion region 15 may be provided in the barrier layer 4 and the channel layer 3 around the second n-type impurity diffusion region 13 so as to surround the second n-type impurity diffusion region 13. Good.
The third n-type impurity diffusion region 15 may include a part of the interface between the channel layer 3 and the barrier layer 4 on the gate electrode 7 side of the second n-type impurity diffusion region 13. The third n-type impurity diffusion region 15 has an n-type impurity concentration lower than that of the second n-type impurity diffusion region 13. Further, the third n-type impurity diffusion region 15 is not formed in the barrier layer 4 and the channel layer 3 immediately below the lower surface closest to the channel layer 3 of the gate electrode 7.
With this configuration, since the sheet carrier concentration can be made substantially constant in the third n-type impurity diffusion region 15, when a voltage is applied between the gate electrode 7 and the drain electrode 8, the barrier layer 4 and the channel layer 3. It is possible to suppress the occurrence of electric field concentration exceeding the dielectric breakdown strength.

  The third n-type impurity diffusion region 15 has an interval between the lower surface closest to the channel layer 3 of the gate electrode 7 and the lower surface of the drain electrode 8, that is, the length of Y shown in FIGS. Then, the interface between the channel layer 3 and the barrier layer 4 provided with the third n-type impurity diffusion region 15 on the gate electrode 7 side of the second n-type impurity diffusion region 13 has a width of 10 to 50 ( That is, it can be provided so as to have the length X in FIGS. For example, when the length of Y is 5 to 20 μm, the length of X can be 0.5 to 10 μm.

The third n-type impurity diffusion region 15 is 1.0 × 10 ^x-5 cm ⁻ when the n-type impurity concentration of the second n-type impurity diffusion region 13 is 1.0 × 10 ^x cm ^−2. The n-type impurity concentration may be ^{2 to} 1.0 × 10 ^x−0.5 cm ⁻² . For example, when the n-type impurity concentration of the second n-type impurity diffusion region 13 is 1.0 × 10 ¹⁵ cm ⁻² , the third n-type impurity diffusion region 15 is 1.0 × 10 ¹⁰ cm ⁻² to 1. It may have an n-type impurity concentration of 0.0 × 10 ^14.5 cm ⁻² . The third n-type impurity diffusion region 15 may have an n-type impurity concentration of 1.0 × 10 ¹⁰ cm ^{−2 to} 1.0 × 10 ¹⁴ cm ⁻² .

Further, the n-type impurity contained in the third n-type impurity diffusion region 15 is not particularly limited, but is Si, Ge, Sn, etc. when the barrier layer 4 and the channel layer 3 are group III nitrides.
The third n-type impurity diffusion region 15 can be formed by ion-implanting n-type impurities into the barrier layer 4 and the channel layer 3. Further, the third n-type impurity diffusion region 15 can be activated by performing a heat treatment after the ion implantation. Although the temperature of heat processing is not specifically limited, For example, it can be 1000 degreeC-1200 degreeC.

The third n-type impurity diffusion region 15 can be formed by thermal diffusion of n-type impurities, for example, Si diffusion. Specifically, an Si layer is formed on the barrier layer 4 forming the third n-type impurity diffusion region 15, and Si of this Si layer is diffused to the barrier layer 4 and the channel layer 3 by heat treatment. A third n-type impurity diffusion region 15 can be formed. The conditions for this heat treatment are not particularly limited, but can be, for example, 1100 degrees and 2 minutes.
The second n-type impurity diffusion region 13 can be formed using epitaxial growth.

3-11. Insulating Film The insulating film 10 can be provided on the barrier layer 4. 1, 2, 4, and 5, it can be provided between the source electrode 6 and the gate electrode 7 and between the gate electrode 7 and the drain electrode 8. Further, as shown in FIG. 3, it can be provided between the source electrode 6 and the drain electrode, and the gate electrode 7 can be provided on the insulating film 10.

The insulating film 10 is not particularly limited as long as it is an insulating film, but may be, for example, a film of SiN, SiO ₂ , or SiON. Moreover, the thickness of the insulating film 10 is not particularly limited, but may be, for example, 0.01 μm to 0.5 μm.
By providing the insulating film 10, the electric field between the source electrode 6 and the gate electrode 7 and the electric field between the gate electrode 7 and the drain electrode 8 can be relaxed, and electric field concentration in the channel layer 3 or the like can be reduced. It can be suppressed from occurring.
The insulating film 10 can be formed by, for example, a CVD method.

3-12. Insulator Layer The insulator layer 25 can be provided between the channel layer 3 and the gate electrode 7 as shown in FIG. The insulator layer 25 can also be provided between the barrier layer 4 and the gate electrode 7. Further, for example, as shown in FIG. 3, the insulating layer 25 may be the same as the insulating film 10.
The insulator layer 25 is not particularly limited as long as it is an insulator, but may be, for example, a film of SiN, SiO ₂ , or SiON. The insulator layer 25 may be an oxide film of the channel layer 3 or the barrier layer 4. Moreover, the thickness of the insulator layer 25 is not particularly limited, but may be, for example, 0.01 μm to 0.1 μm.

The insulator layer 25 may include a plurality of layers having different dielectric constants. For example, a two-layer structure having different dielectric constants may be formed by forming SiO ₂ after forming SiN _x .
By forming the insulator layer 25, good gate insulation characteristics can be obtained.
The insulator layer 25 can be formed by, for example, a CVD method.

4). Simulation for Conventional Field Effect Transistor For a conventional field effect transistor as shown in FIG. 8, a simulation was conducted to examine the electric field strength distribution inside the transistor.
As simulation conditions, the channel layer 103 was a GaN layer having a thickness of 3 μm, and the barrier layer 104 was an Al _1-x Ga _x N (x = 0.17) layer having a thickness of 0.025 μm. Further, the insulating film 110 made of SiN _x is provided between the source electrode 106 and the gate electrode 107 and between the gate electrode 107 and the drain electrode 108. The gate electrode 107 has a 1 μm field plate structure on the insulating film 110. The distance between the source electrode 106 and the gate electrode 107 was 1 μm, and the distance between the gate electrode 107 and the drain electrode 108 was 5 μm.

Further, the barrier layer 104 and the channel layer 103 immediately below the source electrode 106 are provided with the first n + diffusion region 112, and the barrier layer 104 and the channel layer 103 immediately below the drain electrode 108 are provided with the second n + diffusion region 113, and the first n + The sheet carrier concentration of the diffusion region 112 and the second n + diffusion region 113 was 1 × 10 ¹⁵ cm ⁻² . Further, the sheet carrier concentration of the two-dimensional electron gas 117 generated at the interface between the channel layer 103 and the barrier layer 104 was set to 2 × 10 ¹² cm ⁻² .
Further, the substrate 101 is a conductive substrate, and the substrate 101 and the source electrode 106 are electrically connected and grounded. In addition, a voltage of −10 V was applied to the gate electrode 107 and a voltage of +600 V was applied to the drain electrode 108.

  6A and 6B are simulation results of a conventional field effect transistor. FIG. 6A shows a potential distribution inside the transistor, and FIG. 6B shows a field strength distribution inside the transistor. . Note that the closer the potential distribution interval in FIG. 6A is, the greater the electric field strength in FIG. 6B. 6C is an enlarged view of a range A surrounded by a dotted line in FIG. 6B, and FIG. 6D is an enlarged view of a range B surrounded by a dotted line in FIG. 6B. is there.

  Referring to FIG. 6B, electric field concentration occurs in the vicinity of the corner portion of the gate electrode 107 in contact with the insulating film 110 of the field plate structure and in the vicinity of the corner portion of the drain electrode 108 in contact with the barrier layer 104 on the gate electrode 107 side. You can see that As shown in FIG. 6C in which the vicinity of the corner portion of the gate electrode 107 in contact with the insulating film 110 of the field plate structure is enlarged, an electric field concentration of 5.3 MV / cm occurs in the insulating film 110 below the corner portion. I understood. Since the dielectric breakdown electric field strength of SiNx which is the insulating film 110 is approximately 9 MV / cm, it was found that dielectric breakdown does not occur under this condition in the vicinity of this corner.

  Further, when FIG. 6D is an enlarged view of the vicinity of the corner portion of the drain electrode 108 in contact with the barrier layer 104 on the gate electrode 107 side, in the channel layer 103 and the barrier layer 104 near the corner portion, It was found that electric field concentration of 11.7 MV / cm occurred. The dielectric breakdown electric field strength of GaN as the channel layer 103 and AlGaN as the barrier layer 104 is about 5 MV / cm. Therefore, it was found that dielectric breakdown occurred in the vicinity of the corners, resulting in device breakdown. .

  This is because, particularly when the sheet electron concentration of the two-dimensional electron gas 117 is small, depletion of electrons as carriers under the gate electrode 107 to which a voltage of −10 V is applied is high when a high voltage is applied to the drain electrode 108. It is considered that the electron is depleted by reaching the lower portion of the drain electrode 108 by being pulled toward the drain electrode 108 by the electric field.

5). 1. Simulation for Field Effect Transistor of the Present Invention A simulation for examining the field strength distribution inside the transistor was performed for the field effect transistor of the present invention as shown in FIG.
As simulation conditions, the channel layer 3 was a 3 μm thick GaN layer, and the barrier layer 4 was a 0.025 μm thick Al _1-x Ga _x N (x = 0.17) layer. Further, the insulating film 10 made of SiN _x is provided between the source electrode 6 and the gate electrode 7 and between the gate electrode 7 and the drain electrode 8. The gate electrode 7 has a 1 μm field plate structure on the insulating film 10. The distance between the source electrode 6 and the gate electrode 7 was 1 μm, and the distance between the gate electrode 7 and the drain electrode 8 was 5 μm.

A first n-type impurity diffusion region 12 is provided in the barrier layer 4 and the channel layer 3 immediately below the source electrode 6, and a second n-type impurity diffusion is provided in the barrier layer 4 and the channel layer 3 immediately below the drain electrode 8. The region 13 is provided, and the sheet carrier concentration of the first n-type impurity diffusion region 12 and the second n-type impurity diffusion region 13 is 1 × 10 ¹⁵ cm ⁻² . Further, a third n-type impurity diffusion region 15 is provided so as to surround the second n-type impurity diffusion region 13, and the sheet carrier concentration of the third n-type impurity diffusion region 15 is 1 × 10 ¹² cm ^−2. It was. The third n-type impurity diffusion region 15 has a width of 1 μm from the corner of the lower surface of the drain electrode 8 on the gate electrode 7 side to the gate electrode 7 side. The sheet carrier concentration of the two-dimensional electron gas 17 generated at the interface between the channel layer 3 and the barrier layer 4 was set to 2 × 10 ¹² cm ⁻² .

  Further, the substrate 1 is a conductive substrate, and the substrate 1 and the source electrode 6 are electrically connected and grounded. Further, a voltage of −10 V was applied to the gate electrode 7 and a voltage of +600 V was applied to the drain electrode 8.

  FIG. 7 is a simulation result of the field effect transistor 20 according to the present invention. FIG. 7A shows a potential distribution inside the transistor, and FIG. 7B shows a field strength distribution inside the transistor. It is. Note that the closer the potential distribution interval in FIG. 7A is, the greater the electric field strength in FIG. 7B. FIG. 7C is an enlarged view of a range A surrounded by a dotted line in FIG. 7B, and FIG. 7D is an enlarged view of a range B surrounded by a dotted line in FIG. 7B. is there.

As shown in FIG. 7B, electric field concentration occurs in the vicinity of the corner of the gate electrode 7 in contact with the insulating film 10 of the field plate structure and in the vicinity of the channel layer 3 and the barrier layer 4 on the gate electrode 7 side of the drain electrode 8. I can see that Referring to FIG. 7C, in which the vicinity of the corner portion of the gate electrode 7 in contact with the insulating film 10 in the field plate structure is enlarged, an electric field concentration of 6.2 MV / cm occurs in the insulating film 10 below the corner portion. I understood. Since the dielectric breakdown electric field strength of SiN _x which is the insulating film 10 is approximately 9 MV / cm, it has been found that dielectric breakdown does not occur under this condition near this corner.

  Further, when FIG. 7D is an enlarged view of the vicinity of the channel layer 3 and the barrier layer 4 on the gate electrode 7 side of the drain electrode 8, the channel layer on the gate electrode 7 side of the third n-type impurity diffusion region 15. 3 and the barrier layer 4 were found to have an electric field concentration of 4.3 MV / cm. Since the dielectric breakdown field strength of GaN as the channel layer 3 and AlGaN as the barrier layer 4 is approximately 5 MV / cm, it has been found that dielectric breakdown does not occur in this vicinity under this condition. Therefore, by providing the third n-type impurity diffusion region 15, electric field concentration can be reduced in the channel layer 3 and the barrier layer 4 on the gate electrode 7 side of the drain electrode 8. It was found that it can be prevented from breaking.

  The reason why the electric field concentration can be alleviated by providing the third n-type impurity diffusion region 15 is not clear, but by providing the third n-type impurity diffusion region 15, This is probably because depletion of electrons, which are carriers, can be prevented from spreading to the drain electrode 8.

  From the above results, in the field effect transistor of the present invention, dielectric breakdown does not occur and breakdown of the element can be prevented under the condition that breakdown occurs in the conventional field effect transistor and causes breakdown of the element. all right.

1: substrate 3: channel layer 4: barrier layer 6: source electrode 7: gate electrode 8: drain electrode 10: insulating film 12: first n-type impurity diffusion region 13: second n-type impurity diffusion region 15: first 3 n-type impurity diffusion region 17: two-dimensional electron gas 20: field effect transistor 25: insulator layer 101: substrate 103: channel layer 104: barrier layer 106: source electrode 107: gate electrode 108: drain electrode 110: insulating film 112: First n + type diffusion region 113: Second n + diffusion region 117: Two-dimensional electron gas

Claims (11)

A channel layer and a barrier layer are provided in this order on the substrate,
On the barrier layer, a source electrode, a gate electrode and a drain electrode are provided separately in this order,
A first n-type impurity diffusion region is provided in the barrier layer and the channel layer immediately below the source electrode;
A second n-type impurity diffusion region is provided in the barrier layer and the channel layer immediately below the drain electrode;
A third n-type impurity diffusion region is provided in the channel layer below the second n-type impurity diffusion region and the channel layer on the gate electrode side of the second n-type impurity diffusion region and the barrier layer;
The first n-type impurity diffusion region and the third n-type impurity diffusion region are provided in a portion excluding the barrier layer and the channel layer immediately below the lower surface closest to the channel layer of the gate electrode,
The third n-type impurity diffusion region has an n-type impurity concentration lower than that of the second n-type impurity diffusion region,
The third n-type impurity diffusion region suppresses the occurrence of electric field concentration exceeding the dielectric breakdown strength in the barrier layer and the channel layer when a voltage is applied between the gate electrode and the drain electrode. A characteristic field effect transistor.   The third n-type impurity diffusion region has a gate electrode side of the second n-type impurity diffusion region when the distance between the lower surface closest to the channel layer of the gate electrode and the lower surface of the drain electrode is 100. 2. The transistor according to claim 1, wherein an interface between the channel layer provided with the third n-type impurity diffusion region and the barrier layer has a width of 10 or more and 50 or less.   The transistor according to claim 1, wherein the channel layer and the barrier layer are made of a group III nitride semiconductor. The first n-type impurity diffusion region and the second n-type impurity diffusion region have an n-type impurity concentration of 1.0 × 10 ¹⁴ cm ^{−2 to} 1.0 × 10 ¹⁶ cm ^−2. The transistor according to any one of the above. When the n-type impurity concentration of the second n-type impurity diffusion region is 1.0 × 10 ^x cm ⁻² , the third n-type impurity diffusion region is 1.0 × 10 ^x−4 cm ⁻² to 1. 5. The transistor according to claim 1, wherein the transistor has an n-type impurity concentration of 0 × 10 ^x−0.5 cm ⁻² . The channel layer is composed of an upper channel layer and a lower channel layer,
The transistor according to claim 1, wherein the upper channel layer has a smaller band gap than any of the barrier layer and the lower channel layer.   The transistor according to claim 1, wherein the substrate is a conductive substrate. The barrier layer or the channel layer has a recess structure,
The transistor according to claim 1, wherein the gate electrode is provided on a recess of the recess structure.   The transistor according to claim 1, further comprising an insulator layer between the gate electrode and the barrier layer or the channel layer.   The transistor according to claim 9, wherein the insulator layer includes a plurality of layers having different dielectric constants. Forming a channel layer and a barrier layer on the substrate in this order;
Forming a first n-type impurity diffusion region and a third n-type impurity diffusion region apart from each other in the channel layer and the barrier layer;
A second n-type impurity diffusion region is formed in a part of the third n-type impurity diffusion region and in a portion having the third n-type impurity diffusion region on the lower side and the first n-type impurity diffusion region side. Forming, and
Forming a source electrode immediately above the first n-type impurity diffusion region;
The first n-type impurity diffusion region and the first n-type impurity diffusion region between the step of forming the drain electrode immediately above the second n-type impurity diffusion region and the first n-type impurity diffusion region and the third n-type impurity diffusion region A step of forming a gate electrode directly above the channel layer and the barrier layer in which none of the n-type impurity diffusion regions is formed,
The third n-type impurity diffusion region is formed so as to have an n-type impurity concentration lower than that of the second n-type impurity diffusion region.

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