JPS61141220A - 同期パルス発生回路 - Google Patents
同期パルス発生回路Info
- Publication number
- JPS61141220A JPS61141220A JP59263852A JP26385284A JPS61141220A JP S61141220 A JPS61141220 A JP S61141220A JP 59263852 A JP59263852 A JP 59263852A JP 26385284 A JP26385284 A JP 26385284A JP S61141220 A JPS61141220 A JP S61141220A
- Authority
- JP
- Japan
- Prior art keywords
- input terminal
- output
- supplied
- gate
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Pulse Circuits (AREA)
- Manipulation Of Pulses (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59263852A JPS61141220A (ja) | 1984-12-14 | 1984-12-14 | 同期パルス発生回路 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59263852A JPS61141220A (ja) | 1984-12-14 | 1984-12-14 | 同期パルス発生回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS61141220A true JPS61141220A (ja) | 1986-06-28 |
JPH0219650B2 JPH0219650B2 (cs) | 1990-05-02 |
Family
ID=17395122
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP59263852A Granted JPS61141220A (ja) | 1984-12-14 | 1984-12-14 | 同期パルス発生回路 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61141220A (cs) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03122942U (cs) * | 1990-03-29 | 1991-12-13 |
-
1984
- 1984-12-14 JP JP59263852A patent/JPS61141220A/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
JPH0219650B2 (cs) | 1990-05-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4366394A (en) | Divide by three clock divider with symmetrical output | |
JPH0433056B2 (cs) | ||
US6535048B1 (en) | Secure asynchronous clock multiplexer | |
JPH0255970B2 (cs) | ||
US4988892A (en) | Method and circuit for generating dependent clock signals | |
JPH0373176B2 (cs) | ||
JPS61141220A (ja) | 同期パルス発生回路 | |
JPS63232615A (ja) | クロツク切替回路 | |
JPS62191910A (ja) | クロツク制御方式 | |
JPH0282812A (ja) | クロック切換方式 | |
JPH05327435A (ja) | 半導体集積回路装置 | |
JPH0293810A (ja) | 信号発生方式 | |
JPH0351331B2 (cs) | ||
JPH0137886B2 (cs) | ||
JP2543108B2 (ja) | 同期パルス発生装置 | |
KR930000452B1 (ko) | 비동기 펄스 파형의 동기화 회로 | |
JPH04186913A (ja) | エッジ検出回路 | |
JPS6128426Y2 (cs) | ||
KR940010436B1 (ko) | 주파수 분주회로 | |
KR900001444Y1 (ko) | 동기 자동 주파수 제어회로 | |
JPS63106029A (ja) | 同期制御回路 | |
JPS6260310A (ja) | 同期信号発生方式 | |
JPS58181330A (ja) | 計数回路 | |
JPH10163821A (ja) | 初期化回路 | |
JPS59191927A (ja) | 同期回路 |