JPS6112284B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a control method in a sequence control device.

Conventional sequence control technology has been carried out using a so-called hardwired logic method, in which switches, timers, relays, etc. are interconnected each time to control the desired equipment. However, the wire logic method described above lacks versatility as the sequence is fixed.

2. The intended operation often does not go as planned, and if changes are made frequently, it takes a long time to complete the actual operation.

3. Complex control is difficult and requires highly skilled circuit design.

4. The control device becomes large.

Many problems and inconveniences have been pointed out.
Fortunately, in recent years electronics, which has made remarkable progress, is beginning to replace it. In terms of hardware configuration, a pinboard type or diode matrix type is used, which is suitable for simple control, and a stored program type is used for those suitable for advanced control.

Furthermore, if we distinguish between control methods, cyclic control, which is called conditional control, is suitable for controlling complex random logic, as it performs detection and processing while scanning the input source each time for a set logic state, as shown in Figure 1. It is broadly divided into control method and sequential control method called step-by-step method, which requires relatively little processing time, such as proceeding to the next step after a predetermined process is completed, as shown in Figure 2. be done. Here, an example of the cyclic control method is shown in the third example.
It is shown in the figure and its operation will be explained. First, when the reset switch 21 is turned on, the contents of the counter 23 become "0", a signal is output to the head of the step counter 24 (the top output in the figure), and the setting element storage section 1
Step 0 of is selected. This setting element storage unit 1 contains a Γ control form; an instruction form that determines whether input source signals should be treated with logical product, logical sum, or other logic.

Γ Setting element format: For example, one or more input terminal numbers to be handled, timer time, and counter count.

Γ output form; output element to one or more terminals to be output.

etc. are stored in advance as binary numbers.

Among the above selected and derived form signals,
The control mode signal is applied to a command determination circuit 41, and a necessary circuit is selected from various determination circuits 42...44 via this.

At the same time, setting element form signals are sent to various judgment circuits 42.
......44B side, and as can be seen from FIG. 3, various switches 61 in the input source 6
The signals from ~64 are sent to the determination circuit 42...A of 44.
It is entered directly on the side. If the AND judgment circuit 42 is selected based on the control form signal, an output signal appears at the output terminal of the circuit 42 when A=B, and a storage command is sent to the register section 5 through the OR gate 45. Note that the above-mentioned output format signal is input to each input line of the register 5. Register section 5
As shown in detail in FIG. 4, it is composed of a first F.F. group (flip-flop group) 51, an OR gate group 52, and a second F.F. group 511. is first stored in the first F.F. group 51.

Further, if A≠B, no signal is output to the output terminal of the AND judgment circuit 42, so no output form signal is stored.

Returning to FIG. 3, next, the counter 23 is incremented by +1 by the clock of the clock generating circuit 3, and in response to this, the step counter 24 is also incremented by +1, and step 1 of the setting element storage section 1 is selected. Thereafter, similar operations are performed to store each output form signal from the storage section 1. step counter 2
4 advances to the final position, a signal via the output line E instructs the contents previously stored in the first F.F. group 51 to be stored in the second F.F. group 511 shown in FIG. Clear the contents of 1st F.F. group 51. In this way, the total output form of one scanning of all steps remains in the second F.F. group 511, and this is led out to the output section 7.

On the other hand, if one example of the order control method is excluded, a configuration as shown in FIG. 5 can be considered. However, the difference from the above-described cyclic control method is that the AND gate 22 in front of the counter 23 is controlled through the OR gate 45 based on the results of the various determination circuits 42-44. In other words, the AND gate 22 is gated and the counter 23 does not increment until the output signal appears at the OR gate 45 (that is, until the process of that part is completed).

Furthermore, in the sequential control method, it is sufficient to derive the output form signal of each process for each step, so the register section 5, unlike the cyclic control method, is not required.

The above sequential control method operates according to a time chart, so the movement is easy for the user to understand. The disadvantage is that it is not possible to detect a signal from an independent input source, for example, an input source of a constantly monitoring system.

The present invention eliminates the drawbacks of sequential control in the stored program method described above, and its feature is that both controls are combined so that cyclic control is included in the progress of sequential control. The point is that this is done by merging the two. In addition, in terms of time, the processing time for sequence control is short, so that the sequence control is apparently treated as part of cyclic control.

An embodiment of the present invention will be described below with reference to FIGS. 6 to 8. FIG. 6 and FIG. 7 are block diagrams for achieving the present invention, and FIG. 8 is a diagram showing the states of timing signals along the flow of time.

In FIG. 6, reference numeral 1 denotes a setting element storage section in which a sequence control program and a specific program for performing cyclic control are partitioned into blocks and stored as binary values in a format according to the purpose. Here, in the present invention, there is redundancy in the control form described in the conventional example (input source signals are treated with logical product, instruction form), that is, a code indicating "cyclic control" is added at the beginning of the control form. It is added. This is for determining the control method, and therefore may be a code that says "sequence control". In Figure 6, specific programs are marked with * to represent redundant codes (cyclic control).

8 is a circuit for determining the control method; 9
10 is a circuit for synthesizing the outputs of both methods (described later), 10 is a circuit for controlling the step counter 24, and register A102 contains the predetermined starting position of the specific program (cyclic control program). B10
3 stores in advance the starting position of the sequence control program.

Suppose that the cycle program contains a constant monitoring program. First, when the power is turned on, the signal line connected to the clock generation circuit 30
The control method determination circuit 8 is reset by the signal of CL ₁ , and the output lines S ₁ and S ₁ of this circuit 8 are at the "1" level (operable) at timing t ₁ in FIG. 8, respectively.
The register A102 is selected at the "1" level, and the specific program start position is input to the step register 101. This starting position is further set by step counter 2.
4, the start position step of the specific program in the setting element storage section 1 is selected, and the respective contents stored in that step are derived.

Next, among the derived signals, the signal of the control method added at the beginning is input to the control method determination circuit 8 and is determined. Further, the control form (instruction) and the setting element form are judged by the judgment unit 4 as in the conventional case, and the results are led out to the signal line _S3 . If logic is established between the signal from the input section 6 and the signal from the storage section 1, the AND gate 106 operates and outputs a storage command signal to the output synthesis circuit 9. An example of the output synthesis circuit 9 is shown in FIG. To explain the output synthesis circuit here, the output mode signal derived from the setting element storage section 1 passes through the OR gate 92 and is stored in the first F.F. group 91 by a storage command signal of the gate 106. Also, the 1st F.F. group 91 is Q
A terminal is connected to one input terminal of the OR gate 92, and is configured so that the logical sum is stored at the next storage command in a specific program.
Furthermore, it is connected to an OR gate 921, and is configured so that it can be stored in the second F.F. group 911 as a logical sum when executing a sequence control program to be described later.

On the other hand, the AND gate 107 is closed because it is prohibited by the signal line S2 when the signal line S1 is at a high level, and therefore nothing is stored in the second F.F. group 911.

Next, at timing _t2, the clock generation circuit 30
Output signal (high level) on signal line CL ₂ connected to
When , the +1 circuit 104 starts operating.

This +1 circuit 104 causes step register 1
01 is incremented by +1, this value is transmitted to the step counter 24, and the position of the specific program start position +1 step on the setting element storage section 1, that is, step 1 is selected. Thereafter, the operation is as described above, and only when a signal is output to the signal line _S3 , that is, only when the logic is satisfied between the signal from the input section 6 and the signal from the storage section 1, the signal is sent through the AND gate 106. A storage command is then issued to the output synthesis circuit 9.
In this case, the content of the first F.F. group 91 becomes the content obtained by adding the new output of the storage unit 1 to the previously stored content by using a logical sum while maintaining the previous output state.

On the other hand, when all the specific programs are completed after time _t1 has elapsed (timing _t3 in FIG. 8), the control method determination circuit 8 controls the output signal line S1 to be "0" and the output signal line S2 to be "1". . Therefore register A1
02 becomes unselected, the operation of the +1 circuit 104 and the AND gate 106 is prohibited, and instead, the AND gate 107 becomes operable and the register B 103 is selected.

By selecting the register B103, the start position of the sequential control program stored in this register is input to the step register 101, and the step counter 24 selects the starting position step of the sequential control program in the setting element storage section 1. do.

Next, the content derived from the setting element storage section 1 is determined by the control method determining circuit 8, and the signal line S1 holds "0" and the signal line S2 holds "1". Further, the control form is determined by the determination unit 4, and if the logic is established, the result is derived to the signal line S3. At this time, since the AND gate 107 is in the operable state as described above, the output signal of the AND gate 107 becomes a storage command, and the result of the 1st F.F. group 91 shown in FIG. The output derived from section 1 is logically summed and stored in the second F.F. group 911.

In addition, the +1 circuit 105 connected to the signal line S3
acts to advance register B103 by +1 step. Along with this, the step register 101 receives the value incremented by +1, the step counter 24 selects the next step of the sequence control program, and the same operation is performed thereafter. In the first loop of this program, the determination of YES and NO ends after time _t2 .

Then, as shown in the timing diagram of FIG. 8, when the second signal is output to the signal line CL1, the control method determination circuit 8 is reset and the signal line S1 is controlled to "1" and the signal line _S2 to "0" again. be done. At this time, the first F.F. group 91 is cleared by the signal on the signal line CL1. Therefore, the sequence control program is interrupted when its first loop is completed, the register A102 storing the starting position of the specific program is selected, and the above-described cyclic control operation is performed. After this cyclic control, the process returns to sequential control again and returns to the second loop that was interrupted earlier. In other words, one loop of all the specific programs and the sequential control program can be executed in the cycle T of CL1 generated by the clock generating circuit 30. Here above
The period T of CL1 may be equal to or greater than (time t ₁ required to execute a specific program)+(time t ₂ required to execute one loop of one sequential control program).
The flowchart of both of the above controls is shown in FIG. 9.

The output unit 7 has an output (logical sum) in which the total result of the specific program for each period T of CL1 and the result of the sequential control program each time are combined.
obtained as.

As mentioned above, specific programs, ie, cyclic control and sequential control, can be combined and controlled by adding a simple identification code indicating "which control method is used" to part of the control form. Both expressions can be performed in a unified format such as logical product (AND) of input signals or other instruction formats,
It is also possible to handle input signals that need to be constantly monitored and other input signals that cannot be handled by sequential control alone.
Moreover, since it can be applied to complex and advanced control, extremely effective effects can be obtained in practice.

[Brief explanation of the drawing]

Figures 1 and 2 are diagrams showing the operation flows of the basic control methods, cyclic control method and sequential control method, respectively. Figures 3 and 5 are diagrams showing the conventional sequencer that performs cyclic control and sequential control, respectively. 4 is a partial circuit diagram of FIG. 3, FIG. 6 is a block diagram of an embodiment of the present invention,
FIG. 7 is a partial circuit diagram thereof, FIG. 8 is a signal waveform diagram, and FIG. 9 is a diagram showing the operation flow. 1: Setting element storage section, 4: Determining section, 6: Input section, 7: Output section, 8: Control method determining section, 9: Output combining section, 10: Step counter control section, 24: Step counter.

Claims (1)

[Claims] 1. In order to derive output signals according to external input signals and internal setting elements, a setting element storage unit and a derivation unit store in advance a plurality of programs of sequential control method and cyclic control method with specific codes attached so as to be distinguishable from each other. A control method determination unit that determines the control method of the program that has been executed using a specific code and also specifies a cyclic control method program after the completion of a portion of the sequential control method program; and a control method determination section that receives the output of this circuit and controls a step counter. a step counter control section, a logic judgment section that judges the logic of the derived program;
A sequence control device comprising an output synthesis section that stores and synthesizes each output information obtained by executing the order control method and the cyclic control method using the output from the determination section.