JPS58222305A - Scanning type sequence controller - Google Patents

Abstract

PURPOSE:To progress simply the process, by revising a process number in a memory when a process number relating to a process advancing instruction is equal to a process number next to the present process number and input conditions are satisfied. CONSTITUTION:A CPU1, an ROM2 for system, a user's RAM3 for program storage, a working RAM4, and a 1-bit logical operation register LR are provided. Further, an area A1 represnets the preset process number storage area of the RAM4 and an area A3 represents a start flag area of an SPC instruction. When the SPC instruction executed at present is the basic instruction and the flag of the area A3 is set, whether the process number designated with the instruction is the present process number of not is checked, and when the number is the present number, the present process number of the area A1 is revised to the next process.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a scanning-type sequence controller that scans instructions stored in a program memory and sequentially executes instructions starting from the instructions that satisfy input conditions.

Conventional scanning-type sequence controllers can only use logical operation instructions such as OR and AND instructions, and general instructions such as kakunta and timer instructions. For this reason, when a sequence controller is intended to have a process step function, it is very difficult to interlock to the next step, and condition control becomes complicated, resulting in a very large number of command steps.

An object of the present invention is to provide a scanning type sequence controller that is capable of controlling process steps without interlocking between instructions.

To summarize the invention, a process step dedicated instruction can be used that updates a process step memory that currently stores a process number when a predetermined condition is met. , a process step memory, and a process number for determining whether the process number associated with the command is the next process number of the current process number stored in the memory when executing a process step dedicated command during scanning. a step determination means; and further, when the step number related to the instruction is equal to the next step number of the current step number in the above judgment result and the input condition is satisfied, the step number is changed from the step number in the memory to the next step number. A process number increment execution means is provided to update the process number increment, and process increment control is made possible by updating the stored contents of the process increment memory.

According to the present invention, since the process step memory essentially functions as an interlock means, there is no need for complicated interlock steps based on instructions. Therefore, it is necessary to prepare appropriate commands for the process steps in the program.
1. This allows process steps to be easily performed without any special efforts in hardware or software.

Embodiments of the present invention will be described below with reference to the drawings.

Process step dedicated command (Hereinafter, for convenience, this command will be referred to as SP'C)
' (referred to as a step controller command) has an input that is a step condition for that process on the ladder, and an output for that process.

FIG. 1 shows an example of a ladder diagram with SPC instructions. In the same figure, LODIO is a command to set the 10th manual force to the calculation register LR (described later), and 0UT100 is s
This is an instruction to output the pc instruction execution output to the 100th output terminal. In the SPC instruction, the code m represents an SPC number from 0 to 3. The code n represents the process number related to the m-th spc instruction. n=0゜n=1 spc instruction is n≧2 spc
Unlike commands, they have a special function.

FIG. 2 is an example of a ladder diagram having an SPC instruction with n=0, and FIG. 3 is an example of a ladder diagram having an SPC instruction with n=l. In FIG. 2, the condition connected to the input side of the SPC command is a reset condition for clearing a process step memory (not shown). That is, in this example, when the LOD20 instruction is executed and the 20th manual force is set in the calculation register LR, then when the SPCm instruction is executed, the current process becomes number 0. Furthermore, in FIG. 3, the conditions connected to the input side of the SPC command are start/stop conditions for process progression. This condition applies to subsequent SP
Decide whether to enable or disable the execution of C instructions, and
If there is power in number 0, that is, if 1 is set in the calculation register LR when the SPC instruction is executed, the program starts.
If not, stop. Once started,
Subsequent SPC commands are effectively executed until the next stop.

Note that in the 0UT110 instruction connected to the output side of the SPC instruction, the first process output is output to the 110th output terminal.

In addition to the above-mentioned special SPC command, the sequence controller of this embodiment has an spc command with a jump function.
Instructions are also available. FIG. 4 shows an example of a ladder program having the SPC instruction.

In this instruction, the condition connected to the input side becomes the jump condition, and when the number 40 is set in the arithmetic register LR and the SPC instruction is executed, the process immediately jumps to the n process. That is, when this command is effectively executed, the current process number stored in the process step memory is replaced with the jump destination process number (nth) related to the SPC command.

As mentioned above, in this sequence controller, the first
Process progress control is performed using the basic SPC command shown in the figure and the special SPC command shown in FIGS. 2 to 4. Incidentally, since process step control is possible as long as at least the basic SPC commands shown in FIG. 1 are provided, the special SPC commands shown in FIGS. 2 to 4 are not necessarily required.

Next, a specific configuration for carrying out the above process step control will be explained with reference to FIG. 5 and subsequent figures.

Fig. 5 is a system block diagram of a sequence controller which is an embodiment of the present invention, Fig. 6 is a partial configuration diagram of a work RAM, and Fig. 7 (2), CB) is a flowchart showing the execution procedure of the spc instruction. be.

In FIG. 5, 1 is a CPU, 2 is a system ROM,
3 is a user's RAM for storing programs, 4 is a work RAM, 5 is an internal data bus, 6 is an output port connected to an output terminal, 7 is an input port connected to an input terminal, 8
is a 1-bit logic operation register (LR), and 9.10 is an output port and an input port connected to the logic operation register 8.

The logic operation register 8 captures and stores input data when an LOD (load) instruction is executed, or stores the operation result when a logic operation instruction is executed. Furthermore, the output of the SPC command execution process is stored.

FIG. 6 shows the memory area required to execute the SPC instruction. As mentioned above, since there are four types of SPC numbers m, 0 to 3, an area is given for each SPC. Area A1 is 5pco current process number I) area, area A2 is 5P
The reset flag area of the CO, area #A3, is the start flag area of the 5PCO. @Area B1-B3. C1 to C3 and DI to D3 correspond to 5PCI, SP, C2, and 5PC3, respectively. In each SPC, if 1 is set in the reset flag area, that SPC instruction has been reset to 0 process, and if 1 is still set in the start flag area, the process step will not be executed in subsequent SPC instruction execution. will be carried out.

The SPC instruction is executed during a scan like any other instruction. During scanning, when the SPC command execution stage is reached, the process shown in FIG. 7 is executed.

In step nl (hereinafter step ni will be simply referred to as ni), m (SPC number)=00spc instructions are classified. SPC#et with other numbers is executed according to a flowchart (not shown) consisting of the same processing procedure as n2 and below. In n2, it is determined whether or not n (process number specified by the instruction)=0 for the SPC instruction where m=o. If n = 0, the 5PC6 instruction is a reset instruction.

Therefore, on the condition that the calculation register 8 is set to 1 in 03, the reset flag of the area A2 is set to ONL, and the current process number of the area A1 is set to zero in n5. Setting 1 to 1 is generally done by an LOD instruction.

L01) If the specified input is 00 when executing the instruction, set 0 to the calculation register 8, proceed as n3-+n6, and turn off the reset flag. Then set the reset flag to O
If it is N, proceed as n5-n7 and set 1 in calculation register 8, and if the reset flag is turned off, proceed as n6-n.
Step 8 and set 0 in the calculation register.

When an SPC instruction (n=0) is executed during instruction scanning, the reset flag is always turned on or off.

As long as the reset flag is ON, SPC from n to 0
Even if an instruction is to be executed, it proceeds in the order n2-n9→n8 and never exits n9. When there is no input during the execution of the SPC command for n = 0, that is, when the input turns OFF after a certain period of time, the SPCm command for n to 0 will proceed as n2-+n9-+nlO for the first time. .

In nlO, it is determined whether the SPC instruction is a jump instruction. If so, proceed to nll and check the start flag. Further, proceed to n12, check whether 1 is set in calculation register 8, and then proceed to n13.
Then, the jump process number n specified by the command is set as the current process number of area A1. On the other hand, if it is not a jump SPC command, the process proceeds from n10 to n14, and here it is checked whether it is a start/stop control SPC command with n=1. If it is an SPC command for start/stop control, the process proceeds from n14 to n15; otherwise, if it is a basic SPC command, the process proceeds from n14 to n20.

At n15, it is determined whether or not the arithmetic register 8 is set to 1. If it is set, the start flag for area A3 is set at n16. Furthermore n17. At n18, read the current process number of @ area Al, determine whether the number is 0 or 1, or other than 0.
If so, set the current process number to 17 at n19, if it is 1, do nothing and proceed to n7, and if it is other than 0 or 1, do nothing and n
Proceed to step 8. As a result of such processing, the current process number is O.
When the SPct instruction is executed with the input conditions satisfied, 1 is set in the arithmetic register 8 at n7, so the 0th process output can be output after the SPC instruction is executed.

If 1 is not set in the arithmetic register 8 at n15, the process advances to n15-+n25 and the start flag is turned off. Further, the process proceeds to n26, where the process number n specified by the command is compared with the current process number stored in the area Al, and if they match, the process proceeds to n7, and if they do not match, the process proceeds to n8.

SPC instruction or special instruction to be executed (n=0,1
If the instruction is not a basic instruction with n≧2 (and a jump instruction), the process proceeds to n14-+n20 on the condition that the reset flag is turned off.

At n20, it is determined whether or not the start flag of area A3 is ON. If it is OFF, execute n26→n8; if ON, proceed to [n2.1]. Area A below n21
This is a procedure for updating the current i-god number 1. Selection n21.
In step n22, it is checked whether the process number n specified by the command is the next number to the current process number, and only if so, steps n23 and n24 are executed. If 1 is set in the current calculation register 8 at n23, the process advances to n24 and the current process number in the ft area A1 is updated to the next process. n
If the process numbers do not match in step 21, the process goes to n7, only process output is enabled, and in step n22, the process number n specified by the command is
If it is not the next number to the current process number, the process advances to n8 and 0 is set in the calculation register 8.

According to the above-described procedure, each spc command shown in FIGS. 1 to 4 is executed to advance the process in the area AI. Note that the SPCI (m=1) instruction and 5PC2 (
The procedure for executing the 5PC3 (m=2) and 5PC3 (m=3) instructions is performed in the same manner as above.

As described above, by using SPC commands, process steps can be easily performed, and there is an advantage that there is no need to consider the interface between programmer and 1ri steps even at the flocram stage.

[Brief explanation of the drawing]

FIGS. 1 to 4 are examples of ladder diagrams having 14 types of sPc instructions that can be used in a sequence controller according to an embodiment of the present invention. Figure 5 (c) is a system block diagram of the sequence controller described in item 1, Figure 6 is a partial configuration diagram of the work RAM, Figure 7 ([F]) is a system block diagram of the sequence controller.
3 is a flowchart showing a procedure for executing a C instruction. Applicant Izumi Electric Co., Ltd. Agent Patent Attorney Hisao Komori Figure 1-2 Figure 3 □ Figure 4 Doki LOD T. PCmDn OUT 100 Instruction LOD 20 SPCmD. + Command□ Command LOD 40 SPCJmDn

Claims (1)

[Claims] (1) In a scanning type sequence controller that scans the instructions stored in the program memory and executes the instructions sequentially starting from the instructions that satisfy the input conditions,
In addition to providing a process step memory for storing the current process number, a process step only command determining means for determining whether or not there is a process step only command during the scanning, a step number step determination means for determining whether the step number is a step number next to the current step number stored in the memory; and input conditions for executing a step step dedicated instruction are satisfied; When the process number related to the instruction is the next process number of the current process number, the process number in the memory is changed to the next process number.