JPS6112283B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for arranging programs in a stored program type sequence control device and to speeding up processing time.

Traditionally, sequence control uses switches, relays,
Since dedicated hardware logic such as a timer was configured and interconnected, the control circuit was not versatile and could not be easily modified or changed, and it took a long time to design the circuit if it was a slightly complicated control circuit. A variety of problems were occurring.

However, in recent years, with the rapid advancement of electronics technology, the system has been replaced with a programmable control circuit that can handle each situation, and its effectiveness has been evaluated. Most of these systems employ a so-called stored program system in which control contents are stored in a memory element and processed. Further, as control methods, a cyclic control method in which processing is performed while scanning each input source within a predetermined period of time, and a sequential control method in which the next step is performed when a predetermined step is completed have been proposed.

On the other hand, in order to take advantage of the advantages of both of the above-mentioned control methods, a method of performing a combination and merging process may be considered. For example, the first
It is as shown in the figure, and to explain it,
Reference numeral 1 denotes a programmable memory element in which control contents are stored in a predetermined format in a setting element storage section. Here, the predetermined format refers to the part that distinguishes the control method (sequential control or cyclic control),
Control form (instructions on how to handle logic, such as logical product, logical sum, and other instructions, as well as setting element form, such as which number of input terminals to handle, and how long the timer should run) It consists of a part that distinguishes the output mode (or output terminal), and a part that distinguishes the output form (which output terminal the output is to be sent to), each of which is expressed as a binary value. As can be seen from Figure 1, the above control method is stored in two parts, with the program for the sequential control method at the front, and the program for the cyclic control method at the rear, with a code marked * attached to either one. has been done. Reference numeral 2 denotes a circuit for selecting a program position, that is, a step, in the setting element storage section 1 with a step counter.

Reference numeral 3 denotes a clock generation circuit, and 4 a logic determining section for determining the contents of the control form, setting element form, etc. set in the setting element storage section 1 and the contents of the input section 6. 7 is an output section, 8 is a control method determining circuit for determining the control method, and 9 is an output combining circuit for combining and storing the outputs of both control methods. 1
0 is a step control circuit for controlling the step counter based on the signals obtained from the clock generating section 3, logic determining section 4, and control method determining section 8; The starting positions of the programs for both control methods are stored at the fixed locations.

To describe the general operation of the circuit configured as described above, first, the start position of the cyclic control program stored in the step control circuit 10 is sent to the step counter 2, and the start position of the cyclic control program programmed in the setting element storage section is sent. The first part is selected, and the contents of the setting element storage section 1 are derived and processed by the control method judgment circuit 8, logic judgment section 4, and output synthesis circuit 9, respectively.
Cyclic control is performed one after another while zero is being controlled. When all of the above cyclic control programs are completed, a signal indicating the start position of the other sequential control program stored in the step control circuit 10 is generated, and the step counter 2 is activated by the sequential control program stored in the setting element storage section 1. The top is selected, its contents are derived, and each process is performed as described above. In this case, if the logic of that step (process) is established, the process moves to the next step. In this way, the sequential control program is interrupted when a predetermined fraction of operations is reached, and
Execute the cycle control program again.

From the above configuration and operation, (1) The memory locations of both programs are divided into two and fixed.

(2) When expanding a program for cyclic control, it must be done in the direction of a sequential control program, which is inconvenient.

(3) Furthermore, since the program cannot be placed in any arbitrary location in the setting element storage section, it is inconvenient that the program cannot be programmed in any order desired by the user.

Problems such as this arise.

In addition, as a means to solve the above (2) and (3), it is possible to search for the starting position each time the cyclic control program is executed, but in this case, the processing time is long because it is searched every time. This will become a problem again.

In the present invention, whereas conventionally the first step of a program that was divided into two and fixed in the setting element storage section was stored in a step control circuit, both programs can be arbitrarily placed and stored at any position in the setting element storage section. The advantage is that a position storage register is provided and a control circuit is provided to search for the first step of the cyclic control program prior to arithmetic processing.

Embodiments of the present invention will be described below with reference to FIGS. 2, 3, and 4.

FIG. 2 shows a block diagram, in which 1 is a setting element storage section in which a plurality of control programs with different control methods are arranged and stored at arbitrary locations;
The parts indicated by 4, 6 to 9 are the respective functional circuits described in the conventional example, and 11 is a search section according to the present invention, the details of which are shown in FIG.

Here, to explain the points of interest in the present invention,
There is some "leeway" just before the first control program is executed. Since this is a start command from the operator (for example, pressing a start switch), there are relatively no time constraints, and there is no problem even if the actual control operation is started after a delay of about 1 second.

That is, in the present invention, a search section is provided and the start step is stored in a position storage register built into the search section, thereby making use of the time before the start of arithmetic processing and determining the start positions of the plurality of cyclic control programs as described above in advance. This is to shorten the processing time by searching and storing the information.

FIG. 4 shows this situation in the form of a timing diagram.

Next, to explain the operation, first, the linked start switch 1 in Fig. 3
When 21 is pressed, step register 111, position storage register 112, shift register 113+
1 circuit 118 is cleared and the start switch 1
Each signal line connected to 21 is connected. However, the step register 111 and the position memory register 112
During this time, there will be an electrical disconnection.

Next, the contents of the +1 circuit 118 (in this case, the cleared value, ie, "0") are derived by the first pulse generated from the clock generation circuit 3, and become the input to the step register 111, and then the output of the step register 111. becomes an input signal to the step counter 2, and selects the first step 0 in the setting element storage section 1. Of the contents derived from the setting element storage section 1, the portion in which the control method is stored is input to the control method determination circuit 8 and is determined. In this case, as shown in Figure 2, since it is a sequential control program, "0" is derived from the signal line _l4 (when the sequential control program is "0" and the cyclic control program is "1" in logical expression). .

Here, monostable multivibrator 1
14 is an element that produces a constant width pulse at the output terminal Q when a "rising" signal is input to the A terminal. The above-mentioned constant width is determined by the capacitor 122 and the resistor 123, and an appropriate pulse width can be obtained by changing the values of each.

Now, since the signal line _l4 is "0", the pulse of the constant width cannot be obtained, and therefore the shift register 113 and the AND gate 115 do not function.

Next, the second pulse generated from the clock generation circuit appears on the signal line _L1 , and is input to the +1 circuit 118, and the value incremented by +1 is applied to the step register 11.
1, and the step 1 stored in the setting element storage section 1 is selected by the step counter 2. Further, the contents derived from the setting element storage section 1 are determined by the control method determination circuit 8 as described above, and the result is derived to the signal line _l4 . In this case as well, it is “0”, 114 monostable multivibrator, shift register 1
13. AND gate 115 does not function.

Such operations are performed sequentially.

Next, considering the case of step N1, the content derived from the setting element storage unit 1 is cyclic control marked with an asterisk, so it is determined by the control method determination circuit 8, and the result is "1" and the signal line is A “rising” signal is derived at l ₄ (the 4th
(see figure).

Therefore, the monostable multivibrator 11
A pulse of a constant width is obtained at the output terminal Q of 4.
This becomes an input signal to the shift register 113, and the output terminal _Q3 is selected. On the other hand, and gate 115
Then, the logical product of the pulse and the clock signal of the signal line _l1 is established, and an output signal is obtained on the signal line _l1 ,
The AND gate 116 functions by ANDing with the signal line _l6 , and the position storage register 112 is selected.
At this time, the signal image _l3 connected to the step counter 2 determines the current step, that is, step N1.
is stored in register 112 at location n ₁ .

Next, in the case of step N1+1, since no changing signal, that is, a "rising" signal is obtained on the signal line _l4 , the signal line _l5 becomes a low level and no output signal appears on the signal line _l7 . Therefore, the position storage register 11
2 is not selected.

Next, considering step N2, since the cyclic control is stored here, a "rising" signal is obtained on the signal line _l4 , which becomes an input signal to the shift register 113, selects the output end _Q2 , and the signal line _l6 A signal appears. In this case, the position storage register 112
n2 is selected and step _N2 is stored here.

As described above, each leading step of the arbitrarily arranged cyclic control program is stored in the position storage register 112. and,
When the above operation is completed, the start switch 121 is shut off. In this operation, since it is only necessary to determine the control method, the operation time is short and the signal line
The _l1 clock signal may be fast.

After the above-described search for the cyclic control program is completed, normal processing operation is started using a relatively long cycle signal (signal line _l3 ) necessary for processing generated from the clock generation circuit. For example, step N1 and the following block stored in n1 of position storage register 112, and when the above is completed,
When step N2 and the subsequent blocks stored in n2 and all the cyclic control programs are completed, the start address or destination address of the sequential control program is transferred to the position storage register 112 by the ±N circuit and stored. When the control program is executed, processing is performed sequentially in the order specified.

Here, the signal line _l9 is a signal line for inhibiting the output synthesis circuit 9 during the search, and the ±N circuit 119.
is a circuit for controlling the destination address when executing the sequence control program. In addition, the start switch 12
1 can be easily replaced with a semiconductor circuit or the like.

As described above, according to the present invention, the first step of each program is searched and stored in advance before execution of each program, so each program can be stored in any location, and programs can be expanded to any location. It is possible to improve the utilization rate of the storage unit. Furthermore, since it is not necessary to search the program position each time the program is executed, high-speed execution processing can be performed with no wasted time.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a sequence control device for merging multiple control methods, Fig. 2 is a block diagram of an embodiment of the present invention, Fig. 3 is a block diagram of its main part, and Fig. 4 is its block diagram. It is a signal waveform diagram. 1; Setting element storage unit, 2; Step counter,
4; logic judgment section, 6; input section, 7; output section, 8;
Control method determination unit, 9; Output synthesis unit, 11; Search unit, 111; Step register, 112; Position storage register.

Claims (1)

[Claims] 1. In order to derive an output signal according to an external input signal and an internal setting element, a program for cyclic control and a program for sequential control are attached with a specific code and placed at an arbitrary position so that they can be distinguished from each other. A stored setting element storage section, a step counter that specifies the step to be read from this storage section, a control method judgment section that judges the control method of the derived program using the above code, and a logical judgment of the derived program. and an output synthesis section that stores and synthesizes each output information obtained from the processing operations of the plurality of programs based on the output from the logic judgment section, and sequentially increments a step counter prior to the processing operation of the plurality of programs. receiving signals from a step register that searches the setting element storage section and a control method determination circuit that determines how to sequentially read each step in the setting element storage section;
A sequence control device comprising a search section including a position storage register for storing the first step of the cyclic control program.