JPS6231380B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a debug control function for an external control circuit in a data processing system having a dynamically operating microprocessor.

External control circuits in data processing systems with microprocessors include bus controllers,
The control circuit includes synchronous operation circuits such as a timing generation circuit, an address decoder, and a group of registers, but since the functions of this control circuit are important, it is necessary to check (debug) the functions from time to time. In a system using a microprocessor capable of static operation, debugging the external control circuit described above is easy. However, in a system using a dynamically operating microprocessor with a limited minimum frequency of the basic input clock, debugging the external control circuit is only possible through dynamic operation, making hardware debugging extremely difficult and requiring many It took time and effort.

The relationship between such a microprocessor and an external control circuit will be explained based on the control time relationship diagram shown in FIG. The microprocessor uses clock pulses
PCLK, and the external control circuit is clock pulse CLK.
1 and operate in synchronization with each other.

When the microprocessor requests operation of the external control circuit, it sends an access request signal PRQ to the external control circuit.

The external control circuit is activated by this PRQ,
Executes operations requested by the microprocessor.

When the external control circuit completes the operation requested by the microprocessor, that is, preparation for subsequent control, it sends a ready signal RDY to the microprocessor.

Time Ta in Figure 1 is the access request signal
This is the time from when PRQ is sent from the microprocessor to when ready signal RDY is sent from the external control circuit to the microprocessor. During this Ta, the microprocessor is in a standby state and maintains its current state.

When the microprocessor receives the RDY signal, the microprocessor outputs control signals, address signals, and data signals in time division fashion in synchronization with the clock pulse PCLK during the time indicated by Tb in FIG. The microprocessor will then perform post-processing during TA time and will then send out a new access request signal PRQ.

The present invention thus provides a data processing system using a microprocessor that is not capable of static operation, that is, a microprocessor for which the minimum frequency of the basic input clock is determined.
Access request signal from microprocessor
During the time Ta from sending PRQ to sending ready signal RDY from the external control circuit, continuous single-step operation of various synchronous operation circuits such as registers included in the external control circuit is performed to debug the external control circuit. This is intended to facilitate debugging of the hardware of the external control circuit.

The reason for choosing Ta in this way is that in the time Tb, as mentioned above, control signals, addresses, and data signals from the microprocessor are given to the external control circuit in a time-division manner in synchronization with clock pulses, and the corresponding This is because the operation is performed by an external control circuit, making single-step control impossible. According to the present invention, such debugging of the external control circuit during the time Ta is possible in a data processing system including a dynamically operating microprocessor, an input/output device, an external control circuit for controlling the input/output device, etc. A clock pulse control means is added in the clock pulse supply path to the external control circuit, and the means controls the external control circuit by an access request signal applied from the microprocessor to the external control circuit upon initiation of a single step function for debugging the external control circuit. In addition to cutting off the continuous supply of clock pulses to the external control circuit, only when performing a single step, a single pulse is extracted from the clock pulse and supplied to the external control circuit, and the ready signal given from the external control circuit to the microprocessor is Debugging is accomplished by a data processing system having a debug control function characterized by a function of terminating debugging in response to a signal.

That is, when the external control circuit is caused to perform a single step operation for debugging the circuit at time Ta, the addition of the clock pulse control means according to the present invention allows the access request signal to be sent from the microprocessor to the external control circuit. When a single step is to be performed, the clock pulses previously applied to the external control circuit are interrupted, and the pulse for single stepping is applied to the external control circuit only when a single step is to be performed. The functions of the circuits that perform various synchronous operations included in the system will be checked.

The invention will be further explained with reference to the drawings. Figure 2 shows the circuit of the embodiment, which consists of a dynamically operating microprocessor, an external control circuit, a bus, an input/output device, a pulse generation circuit, and a frequency divider circuit.The external control circuit also includes a bus controller and a timing generation circuit. , an address recorder, a group of registers, and other synchronous operation circuits. In the figure, clock pulse control means CCT according to the present invention is added to such a data processing system.

This clock pulse control means includes switches S ₁ ,
S ₂ , inverters I _ov1 , I _ov2 , flip-flop
FF ₁ ~ _{FF 4} , NAND circuit GT ₁ , GT ₂ , AND circuit
Consisting of GT ₃ , the clock pulse is CLK0,
PCLK and CLK1 are shown, and in the conventional external control circuit, the illustrated CLK1 matches CLK0. Third
The figure is a time chart explaining the operation of the embodiment circuit of FIG. 2. The symbols shown in this time chart indicate the clock pulses and the output signals of each component in the circuit of FIG.

When the microprocessor wishes to activate the external control circuit, it sends an access request signal PRQ to the external control circuit. At this time, the microprocessor is operating with the clock pulse PCLK shown in Figure 3, while the external control circuit receives the clock pulse CLK0.
It is supplied as CLK1 via AND circuit _GT3 . This means that the access request signal PRQ is simultaneously applied to flip-flop FF ₄ , and the NAND circuit GT ₂
This is because GT ₃ is open through . PRQ
The external control circuit activated by
Sends ready signal RDY to the microprocessor.

As already mentioned, the time up to this point is Ta.
When the present invention requires debugging of the external control circuit, the clock pulse CLK0, which has been continuously supplied to the external control circuit, is interrupted by the clock pulse control means CCT according to the present invention within this Ta time. and the external control circuit is
From clock pulse CLK0 to CLK1 shown in Figure 3
Only the pulses CL ₁ , CL ₂ , etc. are extracted and provided. This pulse causes the synchronized operation systems of various circuits included in the external control circuit to perform single-step operations, thereby detecting protection errors, variation errors, memory abnormalities, etc. in these circuits.

The operation in such a debugging case will be explained.

Switch _S2 is normally open or in the 0 state, but is activated when the single step function is to be activated and is held activated as long as it is desired to continue. Switch _S1 is normally open, ie, 0, and becomes active, ie, 1, only when single-step operation is desired within the valid time of the single-step function. This operation and restoration of switch _S1 is repeated as many times as necessary in a single step.

When the external control circuit is to be debugged, switch _S2 is operated. This causes FF ₃ to output state 1. Subsequently, when the access request signal PRQ is applied from the microprocessor to the external control circuit, FF ₄ also goes into state 1. As a result, the NAND circuit GT ₂ changes its operation as shown in Figure 3, and becomes an AND circuit.
The circuit _GT3 becomes blocked, and the clock pulse CLK0, which had been applied to the external control circuit up to that point, is also blocked.

When switch S ₁ is operated for the first time in this state, FF ₁ and FF ₂ are operated, and NAND circuits GT ₁ and GT ₂ are switched again as shown in FIG. ONLY AND gate GT ₃ is opened again and pulse CL1 is set as clock pulse CLK1.
(FIG. 3) is applied to the external control circuit, and with this pulse, various synchronous operation systems of the external control circuit perform single-step operations, and the pulse operation function of each circuit is checked. If an abnormality occurs, an error signal will be generated in a detection section (not shown).

Such a single step operation is performed by operating switch _S1 the necessary number of times,
In FIG. 3, only the case where switch _S1 is operated twice is shown. After the single step operation is performed the required number of times and the external control circuit completes the operation requested by the microprocessor, the ready signal RDY is activated.
is sent to the microprocessor. As a result, FF ₄ shifts to another state, and NAND circuit GT ₂ continuously outputs a signal in state 1, which causes AND gate GT ₃ to continuously supply clock pulse CLK0 as CLK1 to the external control circuit. become.

[Brief explanation of the drawing]

FIG. 1 is a control time relationship diagram between a microprocessor and an external control circuit, FIG. 2 is a block diagram illustrating an embodiment of the present invention, and FIG. 3 is a diagram illustrating an embodiment of the present invention. In the figure, CCT is the clock pulse control means according to the present invention, S ₁ and S ₂ are switches, FF ₁ to _{FF 4} are flip-flops, GT ₁ and GT ₂ are NAND circuits, and GT ₃ is a
AND circuit, CLK0, CLK1 are clock pulses,
A indicates an address signal, D indicates data, PRQ indicates an access request signal, and RDY indicates a ready signal.

Claims (1)

[Claims] 1. In a data processing system that includes an external control circuit for controlling a dynamically operating microprocessor, an input/output device, an input/output device, etc., a clock pulse control means is added to the clock pulse supply path to the external control circuit. The means cuts off the continuous supply of clock pulses to the external control circuit by an access request signal given from the microprocessor to the external control circuit when starting a single step function for debugging the external control circuit; Only when performing a single step,
A data processing system having a debug control function, characterized in that it has a function of extracting a single pulse from a clock pulse, supplying it to an external control circuit, and terminating debugging by a ready signal given from the external control circuit to a microprocessor. .