JPH10320080A - Reset circuit for information processor and resetting method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow an operator to freely change a generation place of a reset pulse according to a failure type and to improve efficiency by performing initialization that is suitable for the failure type. SOLUTION: This device is provided with a reset mask circuit 30 which individually set a mask to plural reset signals 11 to 14 which are allocated to plural expansion slots 21 to 23 and an LSI 24 respectively according to a reset command 31 from a CPU, issues a reset pulse only to a reset signal to which a mask is not set and omits and simplifies initialization and an initial diagnosis which are generated at the time of initialization of an information processor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a reset circuit and a reset method for an information processing device.

[0002]

2. Description of the Related Art In general, resetting means of an information processing apparatus includes a power reset circuit, a software reset circuit (hereinafter referred to as an S / W reset circuit), and a hardware reset circuit using a push switch (hereinafter referred to as an H / W reset circuit). There are three types of factors, all of which issue a reset pulse to the entire information processing apparatus for initialization, and execute from an initial setting and an initial diagnostic test.

[0003] The initial setting refers to setting each LSI (interrupt, timer controller, etc.) of the minimum functions required for the operation of the information processing apparatus, and the initial diagnostic test refers to the operation of the information processing apparatus. This is a simple function test of the minimum required functions, for example, a memory function test, L
It refers to tests such as SI.

FIG. 2 shows a block diagram of a power reset circuit in an information processing apparatus. Assuming that the drive voltage of the information processing apparatus 100 is 5 V in FIG. 2, when the drive voltage rises from 0 V to 5 V immediately after the power is turned on, the power reset circuit recognizes about 4.2 V to 4.6 V,
To transmit the information to the reset generation circuit 2. Based on the information, the reset generation circuit 2 generates a valid reset pulse for the reset signal 3 for a certain period of time throughout the information processing apparatus 100. Also, 4.
A reset pulse is also generated as the reset signal 3 when the voltage drops below 2V.

FIG. 2 is a block diagram of the S / W reset circuit in the information processing apparatus 100. In the S / W reset circuit, when an abnormality is detected by software (application software) operating in the information processing apparatus 100 in FIG. 2 and a reset generation request is made by a keystroke or the like from an operator, the CPU issues a reset command 4
Issue Upon receiving the reset command 4, the reset generation circuit 2 generates a reset pulse for the entire information processing apparatus 100 in response to the reset signal 3.

FIG. 2 is a block diagram of an H / W reset circuit in the information processing apparatus 100. When the software runs out of control and the S / W reset circuit cannot operate normally, the H / W reset circuit depresses (ON / OFF) the push S / W5 to thereby output the change information to the reset generation circuit 2. , A reset pulse is generated in the entire information processing apparatus 100 in response to the reset signal 3.

The information processing apparatus disclosed in Japanese Patent Application Laid-Open No. 5-197451 is an invention that performs initialization suitable for the type of reset. However, in terms of hardware, one reset signal is applied to the entire information processing apparatus. The program consists of:
Optimization has been performed.

[0008]

In the above-described three types of reset circuits of the conventional information processing apparatus, since a reset pulse is issued to the entire information processing apparatus, an initial diagnostic test and an initial setting are always executed. Even when an intermittent failure or accidental failure occurs, it is executed from the initial rarity test and initial setting, so the information processing device must be restarted each time, and it takes a long time to start up There is.

It is an object of the present invention to provide a reset circuit and a reset method of an information processing apparatus which can solve the above-mentioned disadvantages and can shorten and omit the restarting time.

[0010]

A reset circuit of an information processing apparatus according to the present invention includes a reset signal which is assigned to a specific LSI and a plurality of expansion slots.
A reset mask circuit for individually setting a mask according to a reset mask command from U is provided, and a reset pulse is issued only for a reset signal for which a mask is not set.

According to the information processing apparatus of the present invention, a reset mask circuit capable of individually masking reset pulses by setting a reset mask command from the CPU and a specific L
It is composed of SI and a plurality of reset signals assigned to a plurality of expansion slots, and can simplify initial setting and initial diagnosis by resetting the entire information processing apparatus. As a result, the speed of the information processing device can be increased, and a smooth use environment can be provided.

[0012]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a reset circuit according to the present invention. When FIG. 1 is compared with FIG. 2 referred to in the related art, the information processing apparatus 100 in FIG. 2 is configured by one reset signal common to the entire information processing apparatus 100. The device 101 is configured by a plurality of reset signals assigned to the expansion slot 21, the expansion slot 22, the expansion slot 23, and the LSI 24.

Further, in the reset circuit of FIG. 1, a reset mask circuit 30 is added,
1, the reset signal 11, the reset signal 12, and the reset signal 13 assigned to the expansion slot 22 and the expansion slot 23 can be freely masked so as not to generate a reset pulse by setting a reset mask command 31 from the CPU.

Next, the operation will be described. The description of the related art will be omitted, and points different from the related art will be described. The reset signal 11, the reset signal 12, and the reset signal 1 assigned to the expansion slot 21, the expansion slot 22, the expansion slot 23, and the LSI 24, respectively.
3. The CPU issues a reset mask command 31 to the reset mask circuit 30 that outputs a reset pulse to the reset signal 14, and sets a mask. The reset mask circuit 30 is configured not to output a reset pulse to a mask-set reset signal.

As an example, the specific option board 51 mounted in the expansion slot 21 is clearly
Alternatively, if an error is determined due to an intermittent failure, a reset signal (reset signal 12, reset signal 13, reset signal 14, reset signal 15) other than the reset signal 11 assigned to the expansion slot for mounting the specific option board 51 is received. Issue a reset mask command 31 from the CPU, apply a mask, and perform S / W reset and H
/ W reset is issued. By doing so, a reset pulse is generated only in the reset signal 11 of the specific option board 51, and the initial setting of only the specific option board 51 and the incorporation of software are performed without restarting the information processing apparatus 101. May return to normal operation.

When the LSI 24 of the main body control unit of the information processing apparatus 101 is clearly determined to be a random or intermittent failure, a reset mask command 3
1 is set so that the reset signal 11, the reset signal 12, and the reset signal 13 are masked, and the reset pulse is not output to the expansion slot side. After that, an S / W reset or a H / W reset is issued.

This makes it possible to simplify the initial setting of all the specific options mounted in the expansion slot, depending on the procedure by the software.

[0019]

As described above, the reset circuit of the information processing apparatus according to the present invention generates a reset pulse individually or generates a reset pulse individually when an accidental failure or an intermittent failure occurs. Since masking can be performed, restarting can be omitted and restarting time can be shortened, so that the speeding up of the information processing apparatus can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a reset circuit of the present invention.

FIG. 2 is a block diagram showing an embodiment of a conventional reset circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Voltage detection circuit 2 Reset generation circuit 3, 11, 12, 13, 14 Reset signal 4 Reset command 5 Push S / W 21, 22, 23 Expansion slot 24 LSI 30 Reset mask circuit 31 Reset mask command 51 Specific option board 100 101 Information processing device

Claims (4)

[Claims] 1. A reset circuit of an information processing apparatus, comprising: a reset mask circuit for individually setting a mask to a plurality of reset signals respectively assigned to a specific LSI and a plurality of expansion slots by a reset mask command from a CPU. A reset circuit for issuing a reset pulse only to a reset signal for which a mask is not set. 2. The reset circuit according to claim 1, wherein the reset pulse is issued by a power reset, a software reset, or a hardware reset. 3. A reset method for an information processing apparatus, wherein a reset signal is assigned to each of a specific LSI and a plurality of expansion slots, and a mask is individually set to the reset signal by a reset mask command from a CPU.
A reset method for an information processing apparatus, wherein a reset pulse is issued only for a reset signal for which a mask is not set. 4. The method according to claim 3, wherein the reset pulse is issued by a power reset, a software reset, or a hardware reset.