JPS60254268A - Selection system of microprogram data - Google Patents

Abstract

PURPOSE:To prevent difficulty at operation of a main program despite of a slow answer of an I/O device by controlling an I/O interface via various I/O interface control parts and performing other processes through a common control part. CONSTITUTION:A common program control part 1 decides the input/output conditions, etc. of a central controller and an I/O device and produces a head address of a microprogram stored in a common memory 3 to send it to a common program control sequencer 2. An I/O program selection part 7 decides the input/ output conditions of various I/O devices and produces the head addresses of the microprograms stored in the I/Oa and I/Oj control program memories 9 and 11, etc. An I/O control interruption signal generating part 12 outputs an interruption signal to a common control program and uses properly the program 3 and an I/O control program for execution of transfer of data to the I/O device.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is directed to the control of microprograms used to control various input/output devices in electronic exchanges, etc., which have the same control procedure but different timing. This relates to a data selection method.

[Conventional technology]

In general, in devices using microprograms, there are cases in which a response signal is immediately received when a control signal is issued to the I10 device, and cases in which a response is received after a period of time has elapsed since the control signal was issued.

[Problem that the invention seeks to solve]

FIG. 3 is a flowchart showing one control procedure when a response is received after the elapse of time after the control signal is issued, and FIG. 4 is a flowchart showing another control procedure.

In the flowchart of FIG. 3, after the interface with the I10 device is established, when the control signal A is output, the corresponding I10
Check whether there is a response signal from the device. If there is no response yet, this flow is repeated many times. The control procedure is such that time elapses by repeating that flow many times, and when a response is received, the flow moves to the next flow and a control signal B is issued to perform the same operation.

In the flowchart in Figure 4, after the interface with the I10 device is established, when control signal A is issued, the presence or absence of a response signal from the corresponding I10 device is checked in the same way, and if there is no response signal, a timer is set and monitored. Check whether the timing is over or not, and if the monitoring timing is not over, return to the original state and repeat this flow. If there is a response within the timer setting time, move on to the next flow, and if the monitoring timing is over, Moving on to the flow of monitoring timing over processing.

In the case of Fig. 3, other processing is impossible until there is a response, and in the case of Fig. 4, other processing is impossible within a certain period of time (this is a problem especially in the case of I10 devices with slow data transfer speeds). There was a drawback.

[Means for solving problems]

A means for solving the problem is that in a device that controls a plurality of input/output devices with the same communication or control procedure but different timings, a common program such as the communication or control procedure is stored in a common control program memory. The timing data that differs depending on the input/output device is stored in a control data memory for the input/output device, and the timing data corresponding to the input/output device is stored according to the address of the input/output device with which an interface is to be established. This is achieved by a microprogram data selection method that retrieves and controls.

[Effect]

The present invention includes a common control section and various I10 interface control sections, stores common programs such as communication or control procedures in a common control program memory in the common control section, and stores various I10 interface control sections.
I10 is stored in the control data memory in the 0 interface control unit.
Different timing data is stored for each device, and each fj
Each Tf110 interface control unit executes its own I10 ink face control, and the common control unit performs other processes such as CC interface l1il inventory and I10 interface startup control, so that the response of the I10 device is controlled. This has the advantage that even if the program is slow, it does not interfere with the operation of the main program.

〔Example〕

FIG. 1 is a diagram illustrating an embodiment of a microprogram data selection method according to the present invention.

FIG. 2 shows an embodiment of a flowchart explaining the operation of FIG.

In FIG. 1, I10a"-Iloj are input/output devices (I10 devices), respectively.

The common program control unit 1 determines the input/output conditions of the central control unit CC (not shown) and the I10 device, generates the start address of the microprogram stored in the common program memory 3, It has a function of sending data to the sequencer 2 for common program control.

The common program control sequencer 2 controls microprograms stored in the common program memory 3.

The common 1ffi program memory 3 stores common 1ff1 microprograms for CC interface control, data transfer between the I10 device and the central control bag Wc'c, etc.

Common control memory register 4 is common program memory 3
It is used to re-timing the microprogram timing read from the memory to match the internal logic.

The common im program control section 1, the common program control sequencer 2, and the common program memory 3 are collectively referred to as a common control section.

The common control memory register 4 is for resetting the timing of microprogram data to match the internal logic.

The CC interface unit 6 has a function of interfacing with the central control unit CC.

Various I10 program selection sections 7 determine the input/output conditions of various I10 devices, and generate starting addresses of microprograms stored in I10a control program memory 9, I10j control program memory 11, etc., which will be described later.

l10a City 1 ■ Wholesale program memory 9 stores tamming data and the like for l10a, and l10a program control sequencer 8 executes the l10a ink face control program.

I/Oj! '11 wholesale program memory 11 stores I/Oj tuning data, etc.
0j Program control sequencer 10 is I/Oj
Execute the interface control program.

In addition, l10a program control sequencer 8 and l10a
The control program memory 9 is connected to the l10a interface control unit, l10j program control sequencer 10 and l1.
The 0j control program memories 11 are respectively referred to as l10j interface control units.

Also, the OR circuit 18 is connected to the l10a control program memory 9 to l10a.
10j This circuit calculates the logical sum of each output of the control program memory 11.

Various l101ti! The J control interrupt signal generating section 12 issues an interrupt signal to the common control program to execute data transfer to the I10 device, and uses the common control program and the I10 control program.

The various I10 control memory registers 13 re-timing the microprogram data to match the timing of the I10 interface.

The various I10 tag line receiving sections 14 receive response signals from various I10 devices, determine the polling state, and send the results to the various I10 program selection sections 7.

The various I10 interrupt interrupt control units 15 detect the interrupts of the I10 devices a to j, and determine the numbers of a to j.

The logic section 16 other than the various I10 controls transmits and receives data between the central controller CC and the various I10 devices.

The signal sending circuit 5 is a circuit that sends signals to the I10 interface bus 19, and the signal receiving circuit 17 is a circuit that receives signals from the I10 interface bus 19.

The present invention will be described in detail below with reference to FIGS. 1 and 2.

As shown in Figure 2, the flowchart consists of (a) the main program (common control program) and the (bl subprogram (I10 control program). In Figure 2, only the I/Oj program is written. Although,
It is assumed that other programs such as l10a are also prepared.

First, when the interface with the T10j device is determined in the main program, it is checked whether the l10j interface control unit is activated.

If it has started, T10j sets the interface control program start address and moves to the next main program.

110j The subprogram starts by setting the interface control program start address, and l10j
The l10j program control sequencer 10 of the interface control unit is the l10j control program, and the program memo January 1
According to the I10j' interface control program stored in the I10j' interface control program, the control signal A is sent out to check whether there is a response signal or not, and if there is no response signal, this process is repeated as described above until a response is received.

In this case, it is also possible to use a timer as described in the prior art section.

If there is a response, control signal B is sent. As in the case of control signal A, it is checked whether there is a response signal or not. If not, this process is repeated until there is a response as described above, and if there is, the process moves to the next step.

Next, check whether there is data transfer to the T10j device or not, and if there is, check the various I10 control memory registers 1.
3 cents, the various I10 control interrupt signal generation units I2 operate and send interrupt signals to the common program control unit 1 to request execution of data transfer to l10j, etc., and the data from the common control unit Wait for the transfer end signal to arrive.

On the other hand, when an interrupt is made to the main program, the common control section executes operations such as data transfer according to the program stored in the common program memory 3, and when it is finished, the end is sent to the interface control section 110j via various I10 program selection sections 7. give a signal.

■When the 10j interface control unit receives the data transfer end signal from the common control unit, it
Check to see if there are any reports from 0j. If not, repeat this operation.

When a report is received from l10j, the various I10 interrupt side control units 15 detect this interrupt signal, detect the I10 number, and report it to the interface control unit 110j via the various I10 program selection units 7. The interface control section drives the various I10 control interrupt signal generation sections 12, sends interrupt signals to the common program control section 1 to interrupt, and transfers report result data to the CC.

As shown above, I1 is controlled by various I10 interface control units.
0 interface control, and the common control unit performs other processing, so the main program proceeds regardless of the slow response of a particular Ilo.

〔Effect of the invention〕

As described above in detail, the present invention has the great effect of realizing a microprogram data selection method that does not interfere with the operation of the main program even when the response of the 10 device is slow. Furthermore, even if a failure occurs during multiple processing of various I10 devices, the operating status of each of the various I10 devices can be easily grasped, which is very convenient for maintenance.

[Brief explanation of drawings]

FIG. 1 is a diagram illustrating an embodiment of a microprogram data selection method according to the present invention. FIG. 2 shows an embodiment of a flowchart explaining the operation of FIG. 1. FIG. 3 is a flowchart showing one control procedure when a response is received after a period of time has elapsed since the control signal was issued. FIG. 4 is a flowchart showing another control procedure when a response is received after a period of time has elapsed since the control signal was issued. In the figure, 110a to 10j are I10 devices, 1 is a common program control unit, 2 is a common program control sequencer, 3 is a common program memory, 4 is a register for common control memory, 5 is a signal sending circuit, and 6 is a CC Interface part 7 is various! 10 program selection unit, 8 a sequencer for l10a program control, 9 l10a control program memory, 10 a sequencer for l10j program control, 11 l10j control program memory, 12 various types; 10 control interrupt signal generation unit, 13 various types I10 control memory register, 14 is various I10 tag line receiving section, 15
16 is a logic unit other than various 110 control units, 17 is a signal receiving circuit, 18 is an OR1 circuit, and 19 is an I10 interface bus. 2 Hayabusa 2 figure JP-A-Sho GO-254268 (5) Rod 3 figure

Claims (1)

[Claims] In a device that controls multiple input/output devices with the same communication or control procedure but different timing, a common program such as the communication or control procedure is stored in a common control program memory, and the timing differs depending on the input/output device. Data is stored by providing a control data memory for the input/output device,
A microprogram data selection method characterized in that the timing data corresponding to the input/output device is extracted and controlled based on the address of the input/output device whose ink face is to be followed.