JPS61253546A - Interruption signal generator for multi-job executing device - Google Patents

Abstract

PURPOSE:To execute plural jobs in response to each processing speed by setting selectively the job executing time data stored in each buffer to a down-counter to count down them with clock signals and producing an interruption signal when said time data are equal to zero. CONSTITUTION:Plural buffers are provided in response to the number of jobs to be executed and store the job executing time data. This time data is set by each buffer and counted down by the clock signal. Then an interruption signal is delivered by a down-counter when the value of said time data is equal to zero. A means is added to designate the buffer storing the job executing time data to be set next in response to the interruption signal sent from the down-counter and then to set the job executing time data of the relevant buffer to the down-counter. Thus plural jobs can be executed satisfactorily in response to each requested processing speed without using any complicated program.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an interrupt signal generation device for a multi-job execution device.

[Prior Art] Conventionally, an interrupt signal generating device of a multi-job execution device converts a clock signal into a signal with a predetermined period using a frequency dividing circuit, and uses the signal as an interrupt signal. Therefore, the interrupt signal is always generated at regular time intervals as shown in FIG.
)) was also switched at regular intervals as shown in FIG. 3(b).

[Problems to be Solved by the Invention] However, if interrupt signals are always generated at regular time intervals like this, if there are jobs that need to be processed quickly and jobs that are not, this interrupt signal will cause the interrupt signals to be processed sequentially. This cannot be done by switching jobs, so software techniques are required, such as running a job that you want to process quickly twice in a row, or speeding up the repeat execution cycle of that job. There were some hassles that needed to be incorporated.

This invention was devised to solve such problems, and it is possible to generate interrupt signals that can efficiently execute multiple jobs according to the speed of processing without incorporating complicated programs. An object of the present invention is to provide an interrupt signal generation device for a multi-job execution device.

[Means for Solving the Problems] The present invention provides a multi-job execution device that sequentially executes a plurality of jobs in a predetermined order while switching in response to the generation of an interrupt signal. job execution time data is set from each buffer, the data is counted down by a clock signal, and an interrupt signal is output when the data value reaches zero. A down counter and a means for specifying a buffer storing job execution time data to be set next in response to an interrupt signal from the down counter and setting the job execution time data of the buffer in the down counter are provided. It's something.

[Operation] In the present invention having such a configuration, different job execution time data is stored in each buffer depending on the processing speed of each job, and the job execution time data is selectively set in a down counter. The job is counted down using a clock signal, and the corresponding job is executed until the data reaches zero, and when the data becomes zero, an interrupt signal is generated and execution of the next job is started.

[Embodiments of the invention] Embodiments of the present invention will be described below with reference to the drawings.

As shown in Figure 1, a microprocessor 1, a port (
1), (2), ~(n)21.22,...2ns control port (1) 3, control boat (2)
4. JOB counter boats 5 are provided, and these are connected by a pass line 6. Each of the ports 2s, 2
2,...2n have buffers (1), (2, ~(n)
71, 72, . . . , 74 are connected to each other, a control latch 8 is connected to the control port (1) 3, and a control buffer 9 is connected to the control port (2) 4. The microprocessor 1 connects each buffer 71 to 71 through each port 21 to 2n.
7n stores job execution time data corresponding to a plurality of jobs (JOBs). Each of the buffers 71 to 7n has an AND gate 1(h, 1
Job execution time data is supplied to the down counter 11 via 02, . . . 10rL. The gate opening of each of the AND gates 101 to 10n is controlled by a decoder 12.

Further, the microprocessor 1 stores control data in the control latch 8 via the control board (1) 3. This latch 8 controls the gate opening of the AND gate 13 that controls the input of the clock signal CLK, and also controls the opening of the gate of the AND gate 13 that controls the input of the clock signal CLK.
, resets and controls the down counter 11 and the JOB down counter 14. Further, the microprocessor 1 stores job control data in the control latch 9 via the control boat (2) 4. This latch 9 supplies job control data to the JOB down counter 14.

The zero state of the down counter 11 is detected by an AND gate 15 with an inverting input terminal, and its detection output is supplied to an AND gate 16 and an inverting input terminal of an AND gate 17. The AND gate 16 inputs the clock signal CLK from the AND gate 13. The AND gate 17 is also the AND gate 1
The clock signal CLK from 3 is input. The AND gate 16 outputs its output as an interrupt signal IN, and also inputs the interrupt signal IN to the down counter 11 as a load signal and to the JOB down counter 14 as a clock signal. The AND gate 17 supplies the input clock signal CLK to the down counter 11.

The zero state of the JOB down counter 14 is detected by an AND gate 18 with an inverting input terminal, and its detection output is supplied to an AND gate 19. The AND gate 19 also receives a signal obtained from the clock signal CLK via a delay circuit 20. And that and gate 1
9 is supplied to the JOB down counter 14 as a load signal. The JOB down counter 14 outputs its count data to the decoder 12 and also to the JOB counter board 5. The data of this JOB counter port 5 is read by the microprocessor 1 via a pass line 6.

In the embodiment of the present invention having such a configuration, Example Eva 3:
) (7) Show'7J 0B (1), JOB (2), J
When executing OB (3), three buffers 771
% 72.73 (not shown) is used. For example, select the job that requires the fastest processing as JOB (2).
, the next one is JOB (3), and if a job that does not require very fast processing is JOB (1), then the job execution time data stored in buffer (2) 72 is the largest, and the next one is in buffer (3) 7 a. Among the stored job execution time data, the job execution time data stored in buffer (1) 71 is the smallest data.

When executing JOB (1) in this state, a signal for opening the AND gate 101 is output from the decoder 12 based on the data from the JOB down counter 14. On the other hand, since the content of the down counter 11 is zero, the gate of the AND gate 17 is closed. Further, the microprocessor 1 can know which JOB to execute by reading the data of the JOB counter port 5. In this state, when the gate of the AND gate 13 is opened by the output from the control latch 8, the clock signal CLK is outputted via the AND gate 16, and at the falling edge of the signal CLK, the down counter 1
A load signal is input to the buffer (1), and the data in the buffer (1) is stored in the down counter 11. As a result, the output of the AND gate 15 is inverted from high level to low level, and the gate of the AND gate 17 is opened. In this way, the clock signal CLK is input to the down counter 11 via the AND gates 13 and 17, and the contents of the counter 11 are counted down. When the contents of the counter 11 eventually reach zero, the AND gate 15 detects this and its output becomes high level, and the clock signal CLK is outputted via the AND gate 16. Then, the clock signal CLK that is first output via the AND gate 16 is output as the interrupt signal IN. Further, the data of the JOB down counter 14 is counted down by this clock signal CLK, and the decoder 12 controls the opening of the next AND gate 102 based on the data. On the other hand, when the output of AND gate 15 becomes high level, AND gate 1
The job execution time data of the buffer (2) 72 is stored in the down counter 11 in response to the fall of the clock signal CLK from the AND gate 16.

In this way, the next JOB (2) is executed and the down counter 11 is counted down by the clock signal CLK. When the contents of the counter 11 eventually reach zero, the AND gate 15 detects this and its output becomes high level, and the clock signal CLK is outputted via the AND gate 16. Then, the clock signal CLK that is first output via the AND gate 16 is output as the interrupt signal IN. Further, the data of the JOB down counter 14 is counted down by this clock signal CLK, and the decoder 12 controls the opening of the next AND gate 103 based on the data. On the other hand, when the output of AND gate 15 becomes high level, AND gate 17
When the gate of the down counter 1 is closed and the clock signal CLK from the AND gate 16 falls, the down counter 1 is closed.
1 stores job execution time data of buffer (3) 73.

In this way, the next JOB (3) is executed and the down counter 11 is counted down by the clock signal CLK. Then, when the contents of the down counter 11 become zero again, the data of the JOB down counter 14 causes the decoder 12 to output a signal to open the gate of the AND gate 101 again. Thereafter, in this way, interrupt signals IN are generated at time intervals based on the job execution time data of buffers 1 (1), (2), and (3), and JOB<1)
, (2), and (3) are executed repeatedly in sequence.

Therefore, the interrupt signal IN is generated at different time intervals for each job as shown in (a) of FIG. 2, and the interrupt signal IN is generated at different time intervals for each job as shown in (b) of FIG. For (2), the longest time is allocated,
The next longest time is allocated to JOB (3), and the shortest time is allocated to JOB (1), which is not processed in a hurry. Therefore, JOB (2) can be repeatedly executed relatively quickly and for a long time, and the process can be ended immediately. In this way, JOB(2), JOB <3), JOB(
The processing can be completed in the order of 1).

In the above embodiment, the case where there are three jobs has been described, but this circuit can generate an interrupt signal to alternately execute up to n jobs. Furthermore, in this circuit, by setting various data to be stored in the control buffer 9 from the microprocessor 1 via the control board (2) 4, the contents of the data to be counted down by the JOB down counter 14 can be arbitrarily set. For example, it is possible to easily execute complex jobs such as repeatedly executing JOBs (1) to (n) several times in sequence and skipping over some of the best jobs. In addition, since the generation interval of the interrupt signal IN can be set according to the processing content of the JOB by simply changing the contents of the job execution time data stored in the buffers 771 to 7n, it is not necessary to incorporate a complicated program like the conventional It is not necessary and can be easily set up.

[Effects of the Invention] As detailed above, according to the present invention, it is possible to generate an interrupt signal that allows multiple jobs to be executed satisfactorily according to the requirements for processing speed without incorporating a complicated program. It is possible to provide an interrupt signal generation device for a multi-job execution device.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing the relationship between an interrupt signal and an execution JOB in the same embodiment, and FIG. 3 is a diagram showing the relationship between an interrupt signal and an execution JOB in the conventional method. It is a diagram. 1... Microprocessor, 71.72, ~7n...
・Buffer, 8... Control latch, 9... Control buffer, 11... Down counter, 12
...Decoder, 14...JOB down counter, 1
5...AND gate with inverting input terminal.

Claims (1)

[Claims] In a multi-job execution device that sequentially executes multiple jobs in a predetermined order while switching in response to the generation of an interrupt signal, a plurality of buffers are provided corresponding to the number of jobs to be executed and store job execution time data. , job execution time data is set from each buffer, and a down counter that counts down the data using a clock signal and outputs an interrupt signal when the data value reaches zero, and responds to the interrupt signal from this down counter. and means for specifying the buffer storing job execution time data to be set next, and setting the job execution time data of the buffer in the down counter. Signal generator.