JPS5826583B2 - Data collection - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data input device for inputting analog data to a control computer.

As is conventionally known, when analog data is input to a control computer, the analog data is converted to digital data, and this converted digital data is input to the control computer, and the analog data is converted to digital data. An analog to digital converter is generally used for this purpose.

This A-D converter starts an operation of converting analog data into digital data in response to a conversion command pulse (hereinafter referred to as a command pulse), completes the conversion for a certain period of time, and the digital data becomes valid.

Therefore, when the control computer reads analog data through the A-D converter, the control computer applies a command pulse to the A-D converter, waits for the time required for conversion from analog data to digital data, and then reads the A-D converter. - Read the data that has been converted to digital by the D converter, or read the data from the point where the data is needed.
A command pulse is applied to the A-D converter at a point in time that is back in time by the conversion time of the converter, and other commands are executed while this A-D converter is converting, and the conversion time of this human converter is After the lapse of time, a processing operation is executed to read the digital data converted by the A-D converter.

However, in the conventional well-known method described above, when a large amount of analog data is handled, time is wasted if the control computer waits during the conversion time. If a command pulse is retroactively applied to the AD converter and other commands are executed during the conversion operation, the software that defines the program for executing the arithmetic processing of the control computer becomes extremely complicated. There were drawbacks.

The present invention solves the above-mentioned drawbacks, and provides a status signal indicating the completion point of the conversion operation of an A-D conversion means for selectively converting a plurality of analog data into digital data at an address for specifying the address of an analog data selector. In addition to the counter, the address designation is changed, and the status signal is used to instruct an interrupt operation of a control computer that executes various arithmetic processing, so that the digital data generated by the A-D conversion means is transferred to the control computer. By reading the plurality of analog data to the control computer, the plurality of analog data can be efficiently read by the control computer,
Moreover, it is an object of the present invention to provide a data input device that can be easily configured with software for arithmetic processing of this control computer.

The present invention will be explained below with reference to FIG.

In Figure 1, 1 is an analog data selector, 1a
is a large number of analog data added to the analog data selector 1, and 1b is selected analog data obtained by selecting one data from the analog data 1a by the analog data selector 1.

Reference numeral 2 denotes a sample and hold circuit, which holds the selected analog data 1b generated by the analog data selector 1, and 2a represents the hold data held by the sample and hold circuit 2.

3 is an AD converter which converts the hold data 2a generated by the sample hold circuit 2 into digital data; 3c is the digital data converted by the AD converter 3;

4 is a digital data selector forming a reading circuit, 5 is a control computer, and 5a is a control signal for the digital data selector 4, which controls which data is selected.

Reference numeral 4a denotes the output of the digital data selector 4, from which data selected by the control signal 5a is output, and is applied to the input of the control computer 5.

3a is a status signal whose logic level becomes level while the A/D converter 3 converts analog data into digital data and is inverted at the time of completion of the conversion.

An inverter 7 inverts the status signal 3a to generate a control clock pulse 7a.

6 is an address counter, and the control clock pulse 7a
A selection signal 6a is generated for time-divisionally selecting a large number of analog data 1a to be applied to the analog data selector 1.

Further, the control clock pulse 7a generated by the inverter 7 is a hold signal of the sample hold circuit 2,
It serves as an interrupt signal for the control computer 5 and a clock input for the address counter 6.

3b is a command pulse for the A/D converter 3, which is generated from the control computer 5 at the time of starting the conversion operation.

Next, the operation of the present invention will be explained according to the timing diagram shown in FIG.

In Figure 2, (a) is the command pulse 3b, (b)
is status signal 3a, (c) is control clock pulse 7
a and (d) indicate the selection signal 6a.

First, at time t1, a command pulse 3b is applied from the control computer 5 to the A-D converter 3, and when the command pulse 3b is reversed from level to O level, that is, at time t2, the A-D converter 3 starts operating. Start status signal 3
Output a.

At this time, the control clock pulse 7a of the output of the inverter 7
is inverted and goes from Lebel to O level.

Further, the address counter 6 is triggered by a negative edge or an edge, and the selection signal 6a is counted up.

Therefore, the analog data selector 1 selects the next analog data and outputs the selected analog data 1b.

Thereafter, at time t3 when the conversion operation of the AD converter 3 is completed, the status signal 3a is inverted, and the control clock pulse 7a output from the inverter I changes from the 0 level to the level.

Since this control clock pulse serves as an interrupt signal for the control computer 5, the control computer 5 executes the interrupt service routine program.

At this time, the digital data selector 4 selects the output digital data 3c of the A-D converter 3 and the address counter 6.
The output selection signal 6a is inputted, and based on the selection signal 6a, it is determined whether the data is for the requested channel, and the data is stored in a predetermined memory corresponding to that channel.

When the operation of this interrupt service routine is completed, time t
At step 4, the control computer 5 outputs a command pulse 3b to the A-D converter 3.

Then, at time t5, command pulse 3b is output from Lebel to O.
When the level is inverted, the status signal 3a changes from the O level to the level, and the control clock pulse 7a output from the inverter 7 changes from the level to the 0 level.

This control clock pulse 1a is supplied to the sample and hold circuit 2.
Therefore, the analog data selected by the selection signal 6a output from the address counter 6 from time t3 to time t4 is held.

Further, the address counter 6 counts up at time t5.

Thereafter, this operation is repeated and analog data is manually input to the control computer 5 one after another.

At this time, the selection signal 6a is 1 from time t2 to t5.
Select the analog data of the channel, and from time t5 to t
Up to 8, analog data of 2 channels is selected, and thereafter analog data of the pot channel is selected.

Then, time t3 at which the interrupt service routine is executed.
to t5, and A-, which is a time other than between time t6 and t8.
During the conversion operation of the D converter 3, the main routine program of the control computer 5 is executed.

That is, the control computer 5 executes the main routine program from time t2 to t3, interrupts the main routine from time t3 to t5, executes the data reading operation of the interrupt service routine, and executes the data reading operation of the interrupt service routine from time t5 to time t5. The program after the interruption of the main routine is executed again until t6.

Further, the selection signal 5a is in a state in which the digital data read by the control computer 5 is incremented by one, but there is no problem if the selection signal 5a is counted up by one by software.

Note that in the embodiment described above, analog data is only input sequentially, but if it is desired to input two analog data at the same time, only the analog data can be input in parallel by inserting independent A-D converters for each. Bye.

In addition, although the A-D converter 3 used requires a conversion operation time of several m5ec, for example, a plurality of A-D converters whose conversion operation time is very short may be provided in parallel, and all of the conversion operations can be performed. The operation of intensively reading the digital data of all the AD converters using an interrupt service routine at the time of completion may be periodically repeated.

As described above, in the present invention, the status signal indicating the completion point of the conversion operation of the A-D conversion means for selectively converting a plurality of analog data into digital data is sent to the address counter that specifies the address of the analog data selector. In addition, the address designation is changed, and furthermore, the status signal is used to instruct an interrupt operation of a control computer that executes various arithmetic processing, and the digital data generated by the A/D conversion means is read into the control computer. Since the address designation of the address counter can be changed by the status signal, the burden on the control computer software for the address designation can be eliminated, and multiple analog data can be sequentially selected. After being A-D converted, it is input to the control computer using interrupt operation, so the control computer does not have to select multiple analog data and can read it efficiently. This has the advantage that the data can be referenced, and the software for the arithmetic processing of the control computer can be simplified.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a data input device according to the present invention, and FIG. 2 is a timing diagram illustrating the present invention in detail. 1...Analog data selector, 2...
- Sample hold circuit, 3...A-D converter, 4...Digital data selector forming a reading circuit, 5...Control computer, 6...
...Address counter, 7...Inverter.

Claims (1)

[Claims] 1. An analog data selector that sequentially selects one of a plurality of analog data; an address counter that specifies an address for the analog data selector; A/D conversion means for converting into digital data and changing the address designation of the address counter by a status signal indicating the completion point of the conversion operation; A data input device comprising reading means for reading digital data generated by the A/D converting means into the control computer in response to a command based on a status signal.