SU1580388A1 - Device for modeling activity of man-operator - Google Patents

Abstract

This invention relates to specialized computer hardware. The purpose of the invention is to expand the functionality of the device by determining the number of errors for each modeled operation. The device contains a memory block, a memory register, four OR elements, three delay elements, an adder, an error counter, an AND element, a correctly performed operations counter, a trigger, three comparison circuits, a completed implementation counter, a registration unit, a generator of uniformly distributed random numbers, pulse generator with a random duration, the differentiating element and the converter time interval - code. Introducing the fourth, fifth, and sixth delay elements, the fifth OR element, the AND block, the decoder, and the group of operational counters allows you to expand the functionality of the device by obtaining new simulation results, in particular, the number of errors made during each operation of the control algorithm. . 1 il.

Description

The invention relates to computing, in particular, to devices for simulating the human operator of man-machine systems (SMM).

The purpose of the invention is to expand the functionality of the device by determining the number of errors for each modeled operation.

The drawing shows a diagram of the device.

The device contains the first element OR 1, the memory block 2, the first delay element 3, the memory register 4, the fourth element OR 5, the trigger 6, the second delay element 7, z:

pulse generator 8 with random duration, uniformly distributed random number generator 9, third delay element 10, differentiating element 11, element 12, time interval converter 13 - code, first comparison circuit 14, fourth delay element 15, counter 16 errors, adder 17 , the sixth delay element 18, the fifth OR element 19, the fifth delay element 20, the registration unit 21, the third comparison circuit 22, the AND block 23, the counter 24 of correctly executed operations, the decoder 25, the second comparison circuit 26, the counter 27 group of poses split

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errors, the third element OR 28, the counter 29 of the implemented implementations, the second element OR 30 and the start input 31. The memory block 2 is intended for storage and input to the register 4 of the parameters of the control algorithm. It stores data on the control and operational components of the activity algorithm, the execution of which is simulated. These data are read by sending signals to its inputs, while generating a signal at its first input produces the output of the parameters of the first and all subsequent operations of the algorithm, and when a signal appears at its second input into the register, only data about it is output. the first operation of the algorithm, which corresponds to the beginning of the new implementation of the algorithm, provided that the previous implementation was unsuccessful, which means that the operator did not perform the control tasks this time.

Memory unit 2 is divided into two zones, with the mean of M (t) and the mean square deviation & (t) of the execution time of each type of elementary algorithm in its first zone. These values are placed in the order of the operations in the execution of the control algorithm. The second zone contains the likelihood values of the error-free execution of the corresponding type of elementary operations of the algorithm P, -.

These parameters characterize the operational component, and the order of their following in accordance with the sequence of elementary operations is the controlling component of the simulated algorithm of activity.

Register 4 stores and issues the first output PI values of the corresponding types of elementary operations, and the second output stores the value of the expectation and variance of the execution time of each type of elementary operations of the algorithm.

The delay elements 3, 7, 10 are designed to arrange reliable writing and reading of data from memory block 2 to register 4. Trigger 6 controls switching the device on and off.

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The generator 8 serves to output pulses with a random duration distributed according to the necessary law with parameters outputted by memory block 2. The generator 9 of randomly uniformly distributed numbers in the interval (0-1) produces values of these numbers.

The power to the generators 8, 9 is supplied by a signal that determines the beginning of the operation of the device, the power supply circuits are not shown in the circuit diagram.

Element 11 separates the pulse at the beginning and the pulse at the end of the pulses formed by the generator 8 to further convert the length of time into a code in the converter 13.

In the comparison circuit 14, when a pulse is received from the pulse end element 11, a random number x, previously generated by a command from the output of the delay element 10 by the generator 9, is compared with the probability of an error-free operation of this type P ;, rewritten into the comparison circuit 14 4. As a result of comparing these numbers, the accuracy of the current operation of the algorithm is determined. If x Ј P (, then the operation is considered completed correctly, otherwise an error is counted, the simulation of this implementation is stopped. The next implementation of the first operation of the algorithm is simulated by applying a signal to the input of memory block 2).

The delay element 15 is intended to organize reliable rewriting of information from the counter 24 into the decoder-25 and reliably read it to the corresponding counters 27 of operational errors.

Counter 16 counts the number of errors made during the execution of the algorithm, which corresponds to the number of unsuccessful implementations, i.e. attempts to execute the algorithm.

The adder 17 performs the summation of all values of the time intervals for performing the operations both for one and for all operations of the algorithm and for all successful implementations of it. In this case, if an operator makes an error when executing the algorithm, i.e. the algorithm is not executed, the values of all previous ones before this operation are erased and are not summed with error-free realizations.

Delay element 18 is designed to organize reliable rewriting of information from counter 24 to comparison circuit 26. The delay element 20 is designed to provide a reliable rewrite of the new information from the counter 24 v. decoder 25 and its zeroing.

Block 21, at the end of the simulation, records the number of unsuccessful attempts to execute the algorithm, i.e. the contents of counter 16, the value of the total simulation time of all successful implementations of the algorithm, i.e. the contents of the adder, as well as the number of errors for each operation, which lead to the failure of the control algorithm as a whole, i.e. the contents of the counters 27 operational errors.

Counter 24 counts the number of correctly executed operations for further comparison in comparison circuit 26 with the number of operations contained in the control algorithm, which allows determining the moment of completion of the operator control task and transition to its new implementation. In addition, when an incorrectly executed operation, the counter 24 together with the decoder 25 forms the address of the fixation counter 27 of the incorrectly executed operation. The number of operations of the simulated algorithm is set in comparison circuit 26 before the start of simulation.

Counters 27 count the number of errors for each operation of the simulated algorithm. The number of counters is determined by the number of operations in the algorithm.

Counter 29 counts the number of implementations carried out, both successful and erroneous for comparison in the circuit 22 compared with the required number of implementations. This number is recorded in the comparison circuit 22 also before the start of the simulation and the outcome is determined from the required accuracy of the simulation results.

The device operates as follows.

Before operation, the device is in its initial state: all counters, adder, trigger, registers are set to initial states.

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and, are nullified by a signal generated at power up.

After the signal has been applied1 the start-up to the device input 31 includes generators 8 and 9, the first of which is prepared to form a sequence of a random number of pulses, and the second - to generate random, uniformly distributed numbers. In addition, a start pulse through the element OR 1 arrives at the delay element 3, the delay time of which is set depending on the output to the specified operating mode of the generators 8 and 9.

After the signal arrives from the output of the delay element 3, the input of the memory block 2 reads data from its both zones into register 4 to simulate the execution of the first operation. In addition, the signal from element 3 through the element OR 30 is fed to the delay element 7, the delay time of which is chosen based on the duration of the rewriting of information from block 2 to the register 4. Register 4. According to this signal, the values of the parameters of the modeled operation are overwritten in generator 8 and comparison circuit 14, respectively. The generator 8 starts forming a sequence of pulses that arrive at the input of the element 11. The time delay of the element 10 ensures reliable reading of information from the register 4. When the signal from the output of the element 10 arrives at the setup input of the register 4 memory, the registers are reset.

The signal Starting from element 11 is fed to one input of the converter 13, the time interval is the code, and the End signal is sent to its other input, forming the code of the duration of the time interval. At the same time, the End Signal gives a command to compare in comparison circuit 14. It compares a random uniformly distributed number with the probability value of the error-free operation.

Tsi this type. In the event that the operation is performed without error, the pulse from the second output of the comparison circuit 14 is fed to the input of the And 12 element.

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When the input element is And 12, i.e., if not all the operations of the algorithm are performed, this signal is applied to the input of the element OR 1, and the whole cycle of the device operation, but already for the 4th model of the second operation of the algorithm, is repeated. In addition, the pulse from the second output of the comparison circuit 14 is fed to the first information input of the adder 17, to the first input of the element OR 19, to the input of the delay element 18. The adder consists of two blocks: in the first one, the simulation time of the current implementation is calculated, and in the second, the time of previous, successfully implemented implementations. If the implementation is completed successfully, then the simulation time is summed with the contents of the second block due to the occurrence of a signal at its second setup input, otherwise, i.e. in case of unsuccessful implementation, the signal at the first installation input of the adder embraces the contents of the first block.

From the output of the element OR 19, the signal goes to the information input of the counter 24. From the output of the delay element 18, the signal delayed by the response time of the element 19 and the counter 24 goes to the control input of the block 23 of the elements AND, allowing overwriting of information (the number of successful operations) from the counter 24 to the comparison circuit 26, from the first output of which a constant single signal is taken until all the operations of the control algorithm are performed. When all operations of the algorithm are completed successfully, a single impulse from the second output of the comparison circuit 26 is supplied through the elements OR 28 to the counter 29 for counting the total number of realizations. From the second output of the comparison circuit 22, a command is received through the first input of the element OR 5 to the second input of register 4 until the required number of implementations is carried out.

In that case, when comparing the values in the P-14 comparison circuit, the operation is considered unfulfilled. In this case, the signal from the first output of the comparison circuit 14 goes to the counter 16 for counting the number of unsuccessful realizations, to the input of the OR element 28 for counting the total number of realizations in the counter 29 and to the first setup input of sum5

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matator 17 for zeroing the contents of the first block of adder time, i.e. time spent on the current implementation. In addition, the signal from the first output of the comparison circuit 14 is fed to the input of the fifth element OR 19 to determine the incorrect operation of the algorithm in the counter 24. "

From the output of the counter 24, the number of the incorrectly executed operation goes to the input of the decoder 25 and to the information inputs of the block 23 elements I. Since there is no signal at the control input of the block 23 elements And there is no signal at its output. At the same time, the signal from the first output of the comparison circuit 14 arrives at a delay element 15, the signal from the output of which is delayed by the response time of the element OR 19, the counter 24 and the rewriting of information from the counter 24 to the decoder 25, enters the decryption enable input of the decoder 25, allowing the information to be written to the corresponding counter 27. At the same time, from the output of the delay element 15, the signal arrives at the delay element 20, the signal from the output of which is delayed by the rewriting time of the new information from the counter 24 to the decoder 25, enters and the installation input of the counter 24 to zero its contents, thereby preparing to count the number of successful events in the next implementation. The signal from the first output of the comparison circuit 14 is fed to the second input of the memory block 2 and provides the output to the register 4 of the first operation data for simulating the next implementation of the algorithm. I

When the number of implementations reaches the required number, from the first output of the comparison circuit 22, the installation inputs of counters 16, 27 are fed to the registration block 21, as well as to the read input of the adder 17, at the signal of which the total simulation time of all successful implementations is also rewritten block 21 registration. At the same time, the signal from the first output of the third comparison circuit 22 is supplied to the second input of the trigger 6, thus ending the operation of the device.

Claims (1)

Invention Formula A device for simulating human operator operations, comprising a memory block, the outputs of which are connected respectively to the bit inputs of the memory register, the first OR element and the first delay element, the second delay element and the third delay element, the adder, and the error counter , And element, the counter of correctly executed operations, the trigger, the single input of which is the device start input, three comparison circuits, the counter of completed implementations, the registration unit, uniformly distributed random number generator, second, third and fourth elements OR, pulse generator with random duration, differentiating element and time interval converter — code, first and second information inputs of the first comparison circuit are connected respectively to the first information register memory output and the generator output uniformly distributed random numbers, the start input of which and the setup input of the memory register are connected to the output of the third delay element, the output of the second The delay element is connected to the first read register memory enable input, the first and second inputs of the second OR element are respectively connected to the output of the More than the first comparison circuit and the output of the first delay element, the output of which is also connected to the first read permission input of the memory block, the second read enable input which is connected to the output More of the first comparison circuit, to the information input of the error counter, to the first input of the third OR element and to the first setup input of the adder, the first whose input is connected to the output. No more than the first comparison circuit and the first input of the AND element, the second input of which is connected to the output Less than the second comparison circuit, and the output of the AND element is connected to the first input of the first OR element, the second input of which is connected to the device start input, zero trigger input connected to setpoint five 0 five 0 five with the input of the error counter, with the read input of the adder and with the output Equal to the third comparison circuit, the output of which is less than connected to | the first input of the fourth OR element, the second input of the flip-flop connected to the direct output, and the output of the fourth OR element are connected to the second read enable input of the memory register, the output Equals the second comparison circuit connected to the second setting input of the adder and the second input of the third OR element, whose output connected to the counting input of the count of completed realizations; 7 the overflow output of which is connected to the information input of the third comparison circuit; the second information output of the memory register is connected with the input of the pulse generator with a random duration, the output of which is connected to the input of the differentiating element, the first output of which is connected to the trigger start input of the time interval — the code, and the second output — to the comparison enable input of the first comparison circuit and the time interval stop input of the converter, the code, the output of which is connected to the second information input of the adder, the output of which is connected to the first information input of the registration unit, the second information input of which is connected to the output dy error counter of T5 0 five To expand the functionality of the device by determining the number of errors for each modeled operation, it additionally contains the fourth, fifth and sixth delay elements, the fifth element OR, the block of AND elements, the decoder and the group of operation error counters, the first input of the fifth the OR element is connected to the output No more than the first comparison circuit, the Output More of which is connected to the second input of the fifth OR element and to the input of the fourth delay element whose output is connected to the work enable input encoder and to the input of the fifth delay element, the output of which is connected to the installation input of the counter of correctly performed operations, the information input of which is connected to the output of the fifth OR element, and the information outputs of the right counter 1580388 of properly executed operations are connected respectively to the information inputs of the decoder, the group of outputs of which is connected respectively to the information inputs of the operational error counters, the installation inputs of which are connected to the output of Equal to the third comparison circuit, and the information outputs of the operational error counters 12 the inputs of the registration block, the information outputs of the counter of correctly executed operations are connected to the information inputs of the I block, the control input of which is connected to the output of the sixth delay element, whose input is connected to the output of No more than the first comparison circuit, and the outputs of the And block of inputs are connected to the inputs of the second circuit Comparison, respectively. 7uv2