SU1388888A1 - Device for simulating man-machine system operator activity - Google Patents

Description

(21) 4145842 / 24-24

(22) 12.11.86

(46) 04/15/88. Bul Number 14

(72) V.I. Balabay, V.M. Machulsky

and B.A. Smirnov

(53) 681.3 (088.8)

(56) USSR Author's Certificate No. 1038948, cl. G 06 F 15/20, 1981.

USSR author's certificate number 1164726, cl. G 06 F 15/20, 1983.

I

(54) DEVICE FOR MODELING THE OPERATORS OF THE MAN-SYSTEM OPERATORS - MACHINE

(57) The invention relates to computing, in particular, to devices for modeling human-machine system operators. The purpose of the invention is to expand the functionality of the device by simulating the group activity of operators. To achieve the goal, the device contains memory registers, a block of delay elements, OR elements, comparison circuits, AND blocks, an inhibit element, triggers, a group of memory registers, a group of comparison circuits, groups, OR elements, an AND group, an accumulator, an element And, a clock generator, a pulse counter and a group of blocks for modeling operator actions, each of which contains a memory register, a random number generator, a generator of uniformly distributed numbers, a comparison circuit, a accumulating sum — g torus, an account uk operations performed. The device allows, as a result of modeling, to quantify the quality of activity of a group of operators. 3 W1.

(L

The invention relates to computer technology, in particular, to devices for modeling the activity of human-machine system generators.

The aim of the invention is to expand the functionality of the device by simulating the operator's gross activity.

Figure 1 shows a diagram of the proposed device; Fig. 2 is a block diagram of a simulation of operator actions; FIG. 3 is a diagram of comparison blocks.

The device contains the fourth delay element 1, the second trigger 2, the prohibition element 3, the first group of 4 AND elements, memory block 5, the first trigger 6, the tenth 7 and the ninth 8 delay elements, the pepper element OR 9, the third trigger 10 , third element OR 11, ninth element OR 12, sixth element 13 for holding, third delay element 14, second delay element 15, first delay element 16 second comparison circuit 17, operator action modeling blocks 18, sixth element OR 9, counter 20 errors, the fifth delay element 21, the second block 22 And elements, the first block 23 elements AND, the eighth element OR 24, the tenth element OR 25, the seventh element OR 26, the block 27 delay elements, the counter 28 pulses, the first group of 29 elements OR, the eleventh delay element 30, the fourth element OR 31, the second accumulating adder 32, the third block 33 of the AND elements, the first element of AND 34, the fifth element of the OR 35, a group of comparison circuits -36, a group of memory registers 37, the fourth comparison circuit 38, the registration block 39, the eleventh element OR 40, the third element AND 41, the tenth delay element 42, fourth element And 43, second element And 44, quarters th trigger 45 generator

46-stroke pulses, the second group

47 elements OR, the first accumulating adder 48, the seventh delay element 49, the second element OR 50, the counter 51 of completed implementations, the device start input 52.

FIG. 2 shows a variant of execution of an operator action modeling block containing a memory register 53, a random number generator 54, a uniformly distributed random number generator 55, a comparison circuit 56, an accumulator 57, an operation counter 58, a delay element 59, an OR element 60

FIG. 3 shows one embodiment of a comparison circuit 36, which comprises a comparison circuit 61, a delay element 62 and an AND element 63.

The device also contains the first 64 and third 65 comparison circuits, the first 66, the second 67, and the third 68 memory registers.

Trigger 2 controls the prohibition element. Block 5 of the gamut is intended for storing and delivering to the blocks 18 of the simulation of elementary actions the operators of parameters of the control algorithm. It stores information about the control and operational components of a group activity algorithm, the execution of which is simulated. These data are read by sending signals to its inputs, and when a signal appears at the second input to block 18, only the first operation of the algorithm performed by the first operator is reported, which corresponds to the beginning of the new implementation of the algorithm, provided that its previous implementation or by any other operator was unsuccessful, i.e. One of the operators made a mistake in the algorithm of activity, therefore the control goal is considered not achieved.

Memory block 5 is divided into zones according to the number of operators in the group. Each zone, in turn, has two memory subzones, and in the first subzone the values of the expectation and the standard deviation of the execution time of each type of elementary algorithm operations are stored. These values are arranged in order of the operations of the control algorithm. In its second subzone, the likelihood values of the error-free execution of the corresponding type of elementary operations of the algorithm P are located; .

These parameters characterize the operational component, and the order of their following in accordance with the sequence of elementary operations is the controlling component of the simulated activity algorithm.

Trigger 6 controls turn on and off of the device. Elements 7,

8, 13, and 21 delays are intended to provide reliable rewriting of information from the adder 57 of the block 18 to the adder 32.

The delay elements 14-16 are used for organizing reliable writing and reading data from memory block 5 into register 53 of block 18 for modeling elementary operator actions and then into comparison circuits 56, as well as for overwriting information from generators 55 of uniformly distributed random numbers into comparison circuits 56 and providing synchronization mode in comparison circuits 56.

Blocks 18 are designed to simulate the performance of elementary actions by automatic control system operators.

Counter 20 counts the total number of errors made during the execution of the algorithm, which corresponds to the number of unsuccessful implementations, i.e. attempts to execute the algorithm.

The delay element 30 is designed to organize reliable rewriting of information from the adder 57 of the block 18 / simulation of elementary operator actions into the comparison circuit 38.

 Register 66 is intended to store the value of the desired number of implementations. It is determined by the desired accuracy of the simulation results.

Register 67 is intended to store the value of the number of operations of the general algorithm, which are worked out by the first operator until the beginning of the division into particular algorithms that are executed by individual operators in parallel. This value is written to the register before the start of the simulation.

Register 68 is intended for storing the number of algorithm operations executed by the first operator until the operators complete the frequency of the algorithms, i.e. until they join into one branch. This value is recorded in the register also before the start of simulation.

Register 37 is designed to store the total number of operations of the algorithm performed by the first operator. The remaining registers 37 are designed to store the numbers of operations of private algorithms, worked out by the corresponding operators, with the exception of the first, after branching out the common

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control algorithm and its connection. Depending on the number of operations in each particular algorithm, these values are written into these registers before the start of the simulation.

Comparison circuit 38 is intended to select the largest time value for modeling elementary operations performed by operators in parallel branches of the algorithm, i.e., in a branched area.

Block 39, at the end of the simulation, records the number of unsuccessful attempts to execute the algorithm, i.e. the contents of counter 20, as well as the total simulation time of all successful implementations, algorithm a, i.e. the contents of the adder 48.

The adder 32 performs the summation of the values of the time intervals for performing the operations, both for all successfully performed operations of the algorithm before its branching, and for all successfully executed operations of the algorithm before its branching, and for all successfully executed operations of the algorithm after connecting the common algorithm. piiTMa controls in one branch.

The delay elements 42 and 49 are intended to ensure reliable rewriting of information from the adder 32 to the adder 48.

The trigger 45 is designed to control the start and stop of the clock pulse generator 46.

The counter 51 of the implemented implementations of the algorithm counts the number of implementations of the algorithm performed, both successful and erroneous to compare with the required number of implementations.

The device operates as follows.

Before operation, the device is in its initial state: all counters, adders, and triggers are transferred to the zero state.

After the start signal is applied to the device input 52, sensors 54 and generators 55 are turned on, the first of which are prepared for forming random numbers depending on the parameters of their distribution laws stored in memory block 5, and the second to generate random evenly distributed ones in the interval O - 1 numbers In addition, the impulse from the launch through the element OR 9 goes to

the input of the delay element 16, the delay time of which is set depending on the output to the specified mode of operation of the sensors and generators 54 and 55.

After the arrival of the signal from the output of element 1 6, the delay at the control input of the group of elements I 4 and at the first

the divided number X with the probability value of the error-free execution of operation P; this type. In that case, if the operation is considered completed without error, and the impulse from the output of the comparison circuit 56 is supplied through the output of block 18, and the element OR 31 enters the input of the element AND 34, When

the read input of the memory block 5 of the produced-) 0 signal at the second input of the element

All the data from the first zone of the memory block 5 is read through the group of its first outputs and the bit inputs of the block 18 (to the bit inputs of the memory register 53 for moderating the execution of the first operation. The register 53 stores and delivers to the first group outputs the values of the corresponding types of elementary operations, and the second outputs - the values of the expectation and variance of the execution time of each type of elementary operations of the algorithm. In addition, r, o, the signal from the output of the delay element 16 is fed to the input of the element OR 26, from the output of which it then goes to the input of the delay element 5, the signal from the output of the delay element 15 is fed to the input of the delay element 14 and through the first input of the block IB to the input of the read resolution of the register 53 and to the input of the generator 55 of uniformly distributed random numbers. performed a getts rewrite of the values of the parameters of the modeled operation into the sensor 54 of random numbers distributed according to the necessary law, and the comparison circuit 56, respectively. The time lag of the elements 14 ensures reliable reading of information from the memory register 53 and rewriting of information from the generator 55 of uniformly distributed random numbers into the comparison circuit 56. The sensor 54 of random numbers distributed according to the necessary law, depending on the incoming values of the operation parameters, generates a number corresponding to the simulation time of the current operation, which is fed to the second information input of the adder 57. The output signal of the delay element 14 through the third input of the block 18 (modular elementary actions of the operator produces the SI, resetting its registers and resolution of the comparison in the circuits; e 56. It compares the random evenly distributed

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And 34, i.e. if not all operations of the algorithm are executed, this signal is applied to the input of the 1 delay element. The signal delayed for the maximum simulation time of an elementary operation goes to the zero input of trigger 2 and to the information input of prohibition element 3, which passes the signal to the input of element OR 9, and the entire cycle of the device, but to simulate the second operation of the algorithm, is repeated. In addition, the pulse from the output of the comparison circuit 56 is fed to the resolution input of the summation of the adder 57 and to the information input of the counter 58, the number of correctly executed operations. The adder 57 calculates the simulation time of the current implementation. The counter 58 counts the number of correctly executed operations of the algorithm for further comparison on the circuit 61 of comparing groups 36 with the number of operations contained in the control algorithms, which makes it possible to determine the time when the task is completed by each operator. From the output of the counter 58, the number of correctly executed operations, the number of successfully executed operations goes through the output of block 18, and the input of the comparison circuit 65 to the input of the delay element 62 and to the first input of the comparison circuit 61, from the first output of which a constant single signal is removed until All operations of the algorithm will not be performed. In addition, the pulse from the output of the circuit 56 of the comparison unit 18 is fed to the information input of the counter 28 and records in it a unit (the number of the modeled operation).

In the case when the first operator successfully performed the number of elementary operations before the branching of the algorithm (this number is counted by counter 28 and compared in comparison circuit 17 after the enabling pulse arrives for comparison with element 27

delay), a single pulse appears at the output of the comparison circuit 17. Next, the signal is fed to the unit input of the trigger 10, to the input of the delay element 21 and to the first input of the OR element 24, the output signal from which through the fourth input of the block 18 enters the input of the delay element 59 and to the installation input of the adder 57, reading information from it through the fourth the output of block 18, to the information inputs of block 33 of elements And, to the information inputs of blocks 22 and 23 of elements I. A signal delayed by the time of reading information from adder 57, from the output of delay element 59 through an element OR 60 zeroed adder 57.

The signal delayed by the element 2, organizes the rewriting of information from the adder 57 through the block 23 elements AND and a group of 29 elements OR in the torus 32. The signal from the output of the element GZ

the delay delayed by the time is triggered; the information of the simulation time of the elements 23 and 29 through the element OR 12 is fed to the input of the recording resolution of the adder 32; Thus, in the adder 32 will be recorded

nor successfully performed operations of the algorithm by the second, third, and subsequent operators (i.e., the operations of the branched part of the general algorithm, the control of the simulation time for success). This information comes in.

operations by the first operator before branching of the control algorithm. At the same time, the signal from the unit output of the trigger 10 is supplied to the second input of the first group of 4 elements I.

If there are signals at both inputs of the first group of 4 elements, both it is triggered and the signal from its group of outputs is fed to the read enable inputs of memory block 5. All data is read from the available zones of block 5 to the bit inputs of memory registers 53 of blocks 18 to simulate the execution of the first branching operation of the control algorithm. The operation of the device for modeling a branched area is no different from that described.

In the event that the first statement successfully performed the number of elementary operations of the branched algorithm, and the completion time is determined by the comparison circuit 65, a single impulse appears at its first output. This pulse arrives at the input of the delay element 30 and at the input of the OR element 24, the output signal from which through the input of the block 18 is fed to the input of the delay element 59 and the input

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The adder 57, reading information from it to the inputs of blocks 33, 22 and 23 elements I. The signal delayed by the delay element 59 at the time of reading information from the adder 57, through the element OR 60 nulls the adder 57, and the output signal of the delay element 30 organizes overwriting the information from the adder 57 through the block of 33 elements And to one of the inputs to the comparison circuits 38. Due to the absence of signals at the second inputs of the blocks 23 and 22 elements, And the read information 5 Qi from the adder 57 of the block 18 to the adder 32 is not received.

In the case when other operators successfully complete the execution of their algorithms, at the first outputs of the corresponding circuits 36, the signals arriving at the inputs of the AND 41 element and through the inputs of blocks 18-18, the inputs of the delay elements 59, and the inputs of the sliders 57, from which counts20

nor successfully performed operations of the algorithm by the second, third, and subsequent operators (that is, the operations of the branched part of the general control algorithm

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to the remaining inputs of the comparison circuit 38. The signal from the output of the element And 41 enters the input of the element And 44 and to the second input of the element And 43, which is triggered, since there is a signal at its first input.

The output signal from the element 43 is fed to a single input of the trigger 45, the signal from the single output of which starts the generator 46, the clock pulses of which are fed to the second input of the comparison circuit 38, which selects the highest value of the number from all incoming to the second comparison circuit 38. From the outputs of the second comparison circuit 38, through the second group of elements OR 47, the maximum simulation time of the branched part of the algorithm goes to the first information inputs of the adder 48 and to the inputs of the OR element 40, the output signal from which goes to the zero input of the trigger 45 (thereby stopping the operation of the generator 46 ). and to the input of the element OR 25, from the output of which the signal is fed to the input of the resolution of the summation of the adder 48.

64 comparisons, from the second output through which the OR 11 element, the inputs of the blocks 18 for modeling the elementary actions of operators will receive a signal until the required number of implementations of the algorithm is performed.

In that case, when comparing the values in the comparison circuit 56 of any block, 18 X, p. , the operation is considered unfulfilled, and the signal from its first output goes to one of the inputs of the element OR 19, and the ac of its output goes to

When the first operator successfully completes the remaining operations in the algorithm, a single pulse appears at the output of the first comparison block 36, which is fed to the input of the element. AND 44, to the input, the delay element 8, and to the input of the OR 24 element, the output signal from which through the input of block 18 ,. enters the tO input of the delay element 59 and the input of the adder 57, from the output of which the simulation time information of the successfully performed remaining operations is read after connecting the branches j, the information input of the counter 20 for the algorithm. This information of the arrival of counting the number of unsuccessful implements the first inputs of blocks 33, 22, and 23 elements AND, however, only the block 22 elements AND works, because its control input receives a signal 20 50 to count the total number of re-output elements 8 delays. The signal of the algorithm in counter 51 and through the output of delay element 7 is fed to the input of an element OR 12, from the output of which the signal goes to the input

resolving the summation of the adder 32, 25 of the element OR 50. In addition, the signal which will summarize the time of the output of the element OR 19 will enter the deletion of successful operations performed by the first operator before branching and after connecting the branches of the control algorithm. thirty

From the output of the element K 44, the signal is fed to the inputs of the elements 42 and 49 of the delay and to the second input of the second element OR 50 ,. Signal delayed

. Simultaneously from the output of the element OR 19, the signal is fed to the input of zeroing the counter 28, to the input of the element

cutting the input of the blocks 18 to reset the counters 58, to prepare them for the new realization of signals from the output

The input element of block 18, the OR element 60, zeroes the contents of the adder 57. The signal from the output of the OR element 19 also goes to the second read enable input of memory block 5 and provides the block 18 with data from the first simulation operation of the next implementation, and the signal arriving from the output of the element OR 19 to the input of the element OR 26, is fed to the input of the element 15 delay, providing the data to the register 53, their reading and starting the generator 55 of uniformly distributed numbers. One time from the output of the element OR 19, the signal goes to the single input of trigger 2 and to the zero input of the trigger 10. The first of them closes the prohibition element 3 by the output signal from the single output, and the second cancels the control signal at the readings of the memory 5 ti. When simulating elementary operators' actions, when the number of re, algorithm alarms reaches the required number, the signal from the first output of the comparison circuit 64 arrives at the installation input of the counter 20 for reading information into the registration unit 39, and the signal from the first output of the comparison circuit 64 is fed to the reading input adder 48, at a signal from which the total simulation time of all successors by delay element 42 for the duration of the summation of information in the matrix 32, arrives at its input and performs reading and zeroing adder 32. The simulation time for successful operations performed by the first operator before branching and after connecting the control algorithm from the output of adder 32 through the OR 47 elements arrives at the information inputs of the adder 48 From the output of delay element 49, the signal delayed by the time of rewriting information from the adder 32 adder 48, is fed to the input of the element OR 25, from the output of which the signal supplies to the input of the resolution of the summation of the adder 48, in which the simulation time is completed successfully implementations of the control algorithm; From the output of the element OR 50, the signal is applied to counter 51 to count the total number of implementations of the algorithm. This number from the output of the counter 51 is fed to the input of the circuits

64 comparisons, from the second output through which the OR 11 element, the inputs of the blocks 18 for modeling the elementary actions of operators will receive a signal until the required number of implementations of the algorithm is performed.

In that case, when comparing the values in the comparison circuit 56 of any block, 18 X, p. , the operation is considered unfulfilled, and the signal from its first output goes to one of the inputs of the element OR 19, and the ac of its output goes to

information input counter 20 for counting the number of unsuccessful implementations - 50 for counting the total number of implementations of the algorithm in counter 51 and

information input counter 20 for counting the number of unsuccessful implementations - 50 for counting the total number of implementations of the algorithm in counter 51 and

. Simultaneously from the output of the element OR 19, the signal is fed to the input of zeroing the counter 28, to the input of the element

information input counter 20 for counting the number of unsuccessful implementations - 50 for counting the total number of implementations of the algorithm in the counter 51 and h

cutting the input of the blocks 18 to reset the counters 58, to prepare them for the new realization of signals from the output

5 of the element OR 50. In addition, the signal from the output of the element OR 19 arrives - 0

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The input element of block 18, the OR element 60, zeroes the contents of the adder 57. The signal from the output of the OR element 19 also goes to the second read enable input of memory block 5 and provides the block 18 with data from the first simulation operation of the next implementation, and the signal arriving from the output of the element OR 19 to the input of the element OR 26, is fed to the input of the element 15 delay, providing the data to the register 53, their reading and starting the generator 55 of uniformly distributed numbers. One time from the output of the element OR 19, the signal goes to the single input of trigger 2 and to the zero input of the trigger 10. The first of them closes the prohibition element 3 by the output signal from the single output, and the second cancels the control signal at the readings of the memory 5 ti. When simulating elementary operators' actions, when the number of re, algorithm alarms reaches the required number, the signal from the first output of the comparison circuit 64 arrives at the installation input of the counter 20 for reading information into the registration unit 39, and the signal from the first output of the comparison circuit 64 is fed to the reading input adder 48, the signal from which the total simulation time all successful5

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realizations will be rewritten in block 39 registration. At the same time, the signal from the output of block 64 is fed to the second input of trigger 6, terminated; this is the simulation process.

Claims (1)

Invention Formula A device for simulating the activities of human-system operators: a machine containing a memory block, the first OR element and the first delay element, the second delay element and the third delay element, the first accumulating adder, the error counter, the first AND element, and the implementation counter , the first trigger, the first input of which is input to the launch of the device and is connected to the first input of the first element OR, the second and third elements OR, the first and second comparison circuits to the registration, the output of the first delay element is connected to the first read input of the memory block, the output of the second element IL1-1 is connected to the counting input of the counter of completed implementations, the bit outputs of which are connected respectively to the information inputs of the first group of the first comparison circuit, output Equals which is connected to the read input of the first accumulating sum Pa, the bit outputs of which are connected respectively to the first group of inputs of the registration unit, the second groups of inputs of which are connected respectively to the bit inputs of the error counter, the setup input of which is connected to the output Equal to the first comparison circuit and the zero input of the first trigger, the first output of the first trigger is connected to the first input of the third element OR, the second input of which is connected to the output Less than the first comparison circuit, which is characterized by the fact that, in order to expand the functionality of the device account for modeling the group activity of operators; it additionally contains the first, second and third memory registers, a block of delay elements, from the eleventh delay elements, from the fourth to the eleventh OR elements, the third and fourth comparison schemes, first, second and three - ten 15 20, 25 to 8888812 ti blocks of elements i, prohibit element, second, third and fourth triggers, group of memory registers, group of comparison circuits, first and second groups of elements or, group of elements i, second accumulating adder, second 5 third and quarter-hr elements i, clock generator , a pulse counter and a group of blocks for modeling operator actions, each of which contains a memory register, a random number sensor, a generator of uniformly distributed numbers, a comparison circuit, an accumulator, an operation counter, an element nt delay and the OR element, and in each modeling block, operator actions, the bit outputs of the first and second groups of the memory register are connected respectively to the setup inputs of the random number sensor and the information inputs of the first group of the comparison circuit, the information inputs of the second group of which are connected respectively to the generator outputs evenly distributed numbers, and the output Less than or equal to the comparison circuit is connected to the input of the summation of the accumulating adder and the information input of the counter in completed operations, the outputs of the random number sensor are connected respectively to the information inputs of the accumulating adder, the zero input of which is connected to the output of the OR element, the first input of which is connected to the output of the delay element, the output of the second delay element of the device connected to the inputs of the memory register registers and uniformly distributed numbers of all blocks of modeling operator actions, outputs Less than or equal to the comparison circuits of which are connected respectively to the inputs of the fourth element the OR input, the output of which is combined with the first input of the first element AND, the second input of which is connected to the output of the fifth OR element, whose inputs are connected respectively to the outputs. the inputs of the second group of comparison circuits of the group are connected to the bit outputs of the counter of executed operations with 40 45 50 55 the corresponding operator action simulation block, memory register reset inputs and comparison enable inputs of which are connected to the third delay element, the second OR output is connected to the counter inputs of executed operations of all operator action modeling blocks, setting memory register inputs which are connected to the output of the third element OR, the outputs of the memory block are connected respectively to the bit inputs of the memory registers of the action modeling blocks operator , outputs. More comparison circuits of which are connected respectively to the inputs of the sixth OR element, the output of which is connected to the first input of the second OR element, which connects the pulse counter input, the counter input of the error counter, the second read input of the memory block, the single input of the second trigger, zero the input of the third trigger, the second inputs of the elements of the IPD of all the simulation blocks of the operator’s actions and the first input of the seventh OR element, the second input of which is connected to the output of the first delay element and the first the inputs of elements AND groups whose second inputs are connected to the direct output of the third trigger, and the outputs of elements AND of the group are connected respectively to the read inputs of the memory block group, the output of the first AND element is connected to the input of the fourth delay element whose output is connected to the zero input of the second trigger and information entry of the prohibition element, the control input of which is connected to the direct output of the second trigger, and the output of the prohibition element is connected to the second input of the first one. the OR element, the output: the seventh IPD element is connected to the input of the second element, the bit outputs of the pulse counter are connected respectively to the inputs of the block of delay elements and the information inputs of the first group of the second and third comparison circuits, the information inputs of the second group of the first, second and third comparison circuits connected to the bit outputs of the first, second, and third memory registers, respectively; the output of the block of delay elements is connected to the comparison enable input five , 0 d 0 five five 0 five The second comparison circuit, the Output Equal to which is connected to the single input of the third trigger, the first input of the eighth OR element, and the input of the fifth delay element, the output of which is connected to the control input of the first block of AND elements and the sixth input of the delay element whose output is connected to the first input of the 9th OR element whose output is connected to the summing resolution input of the second accumulating adder, whose information inputs are connected respectively to the outputs of the OR elements of the first group, and the second outputs The accumulating adder is respectively connected to the first inputs of the OR elements of the second group, the second inputs of the OR elements of the second group are connected respectively to the outputs of the fourth comparison circuit, and the outputs of the OR elements of the second group are respectively connected to the information inputs of the first accumulating adder, the resolution input of which connected to the output of the tenth element OR, the first input of which is connected to the zero input 4eTBepkToro of the trigger and the output of the eleventh element OR, whose inputs are connected respectively, to the outputs of the fourth comparison circuit, the second input of the tenth OR element is connected to the output of the seventh delay element, whose input, the second input of the second OR element and the seventh delay element input are connected to the output of the second And element, the output of the eighth delay element is connected to the second input input accumulating adder, the first input of the second element And is connected to the output of the third element And, the first input of the fourth element And, the output of which is connected to the single input of the fourth trigger; the direct and inverse outputs of which are connected respectively to the start input and the stop input of the clock generator, the output of which is connected to the comparison enable input of the fourth comparison circuit, the output is Equal to the first group comparison circuit connected to the second input of the second AND element, the second input of the eighth OR element and the input the ninth delay element, the output of which is connected to the control input of the second block of elements And and the input of the tenth element (paf.i From l. 15 .f KffA.31 REV.CR ID iS a Fie.2 Fig.Z