SU1432553A1 - Device for simulating the activity of human operator - Google Patents

Abstract

This invention relates to specialized computer hardware. The aim of the invention is to expand the functionality of the device by simulating the performance of sensory and sensory operations. The device contains a memory block, a memory register, a random pulse generator, a random number generator, a random number generator, a differentiating element, a time interval converter — a code, a time adder, five comparison circuits, a counter of timely implementations, a counter of incomplete implementations, a counter of executed operations. , the counter performed implementations, the registration block, three triggers, seven OR elements, nine delay elements, four AND elements, the standard time register, two error counters, a counter in a timely manner and faultlessly executed implementations, the register of the admissible number of repetitions of the operation, § the register of the established number of realizations, the register of the number of operations in the algorithm. 1 il. (L

Description

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The invention relates to computing, in particular, to devices for simulating the activity of a human operator of a system

trap machine, and can be used for statistical studies of the quality indicators of operator activity.

The purpose of the invention is to expand the functional capabilities of the device by simulating the performance of sensory and sensorimotor operations. : The drawing shows a diagram of the device.

The device contains a block of 1 memory: register 2 memory, the first element OR 3, the first element 4 delay, the third element OR 5, the second element 6 delay, the first element And 7, the seventh element § delay, a quarter .ELE 9 , second element 10, third delay element 11, generator 2 random pulses, differential | 13) element 13, J4 transducer time interval — code, sum jrop 15 time, generator 16 random numbers, five RShI element 17 , the third 1 trigger 18, the first circuit 19 is com-, the second trigger 20, the third element I 21, the first counter 22 errors, (Seventh el ment OR 23, second counter - Chik 24 errors, fourth delay element 25, register 26 number of repetitions of operations, fifth circuit 27 compared and (and sixth element OR 28, counter 2J9 incomplete: algorithm implementations, block 30 registration, the first trigger 31, the register 32 of the set number of implementations of the algorithm, the fourth ilyro comparison circuit 33, the eighth delay element 34, the counter 35 of completed implementations, the fifth delay element 36, the second element. III, the second comparison circuit 38, register 39 the number of operations of the algorithm, the sixth element 40 delay, counter 41 operations performed, standard time register 42, ninth delay element 43, third comparison circuit 44, fourth element 45, counter 46 timely implementations implemented And counter 47 timely and error-free implementations of the algorithm.

Memory unit 1 is designed to store the characteristics of the elementary operations of the algorithm. The block is divided into three zones. In the first zone is stored

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mathematical expectation m. and the standard deviation of the execution time of each operation, and these values are placed in the order of the operations of the simulated algorithm. The second zone contains the likelihood values of the error-free execution of the corresponding elementary operation of the PJ algorithm. These parameters allow the operator to model the accuracy and duration of the algorithm, taking into account the conditions of its operation, and characterize the operational component of this algorithm. The third zone contains the attribute of an elementary operation; is it sensory, i.e. simulates the operator's actions on the controls, or sensory, i.e. simulates control-by-display control actions on the control panel. This feature is entered as O for a sensomotor operation and 1 for a sensory operation. The order of the operations of the algorithm, together with the sign of the operation, characterizes the control component of the simulated algorithm.

The memory register 2 stores the characteristics of the next operation and the output of the mean and standard deviation of time, the next time sequence generator 12, pulses, the probability values of the correct execution of this operation in the comparison circuit and the sign of this operation to control the trigger 20 i.e. to allow and prevent repetition of operations when an error occurs.

The random pulse generator 12 produces pulses of random duration, depending on the parameters of the necessary law of the distribution of the execution time of a given operation of the algorithm, received from memory register 2.

The differentiating element 13 generates pulses corresponding to the beginning and end of the pulses of the generator 12.

Transducer 14 time interval — the code is intended to form a binary number corresponding to a time interval equal to the time sequence 31A32553

impulses generated by the generator 12.

Adder 15 records the time value of the last operation performed t

-1, summarizes the time intervals of all the modeled operations of the current pei-t

as well as sum5

LIZATIONS (4t + 2 It), a. yults up- „

Peaces the times of all currently completed implementations of the simulated algorithm.

An operation is considered completed if, when modeling a sensory one- 15 complex of the implementation of a simulated

We repeat the operation Pa. When the comparison condition is fulfilled, a potential signal is generated that permits the repetition of the operation; when equality is achieved, the circuit generates a pulse signal prohibiting the continuation of the current implementation.

Counter 29 counts the number of interrupted, incomplete implementations of the algorithm.

Block 30 of the register is intended to be recorded after the completion of the entire

complex implementation of the simulated

We repeat the operation Pa. When the condition is met, the comparison circuit generates a potential signal that permits the repetition of the operation. When equality p n is reached, the circuit generates a pulse signal prohibiting the continuation of the current implementation.

Counter 29 counts the number of interrupted, incomplete implementations of the algorithm.

Block 30 of the register is intended to be recorded after the completion of the entire

There was no error in the radio, and during a sensorimotor operation when an error occurred, the number of repetitions of this operation to correct the error did not exceed the permissible number. Otherwise, the operation is considered unfulfilled, the current implementation of the algorithm is terminated and is considered incomplete.

The generator 16 apuchaynyh numbers team generates uniformly distributed random numbers.

The comparison circuit 19 compares the probability that an error of execution of operation P received from register 2, and a random number generated in the generator 16, and gives a pulse signal about the result of comparison. The operation is considered completed without error if, as a result of the comparison,

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i-P, it is considered that an error has been made.

Error counter 22 counts the number of errors when repeating the same operation to correct an error, i.e. the number of incorrectly executed repetitions n within the permissible number of repetitions of the operation.

The 24 error counter counts the total number of errors made during the execution of all planned implementations of the simulated algorithm.

Register 26 is intended to be stored and stored after each unsuccessful attempt to perform an operation for comparing the value of the permissible number of repetitions of the operation n. This number is entered in the register before starting the simulation of the algorithm.

The comparison circuit 27 compares ko. the number of errors committed during the execution of this operation and with

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the algorithm of statistical simulation results: the number of timely implementations, the number of timely and error-free implementations, the total execution time of all completed operations, the number of incomplete implementations, the total number of errors.

Register 32 of a set number of implementations is intended to store the value needed to model the algorithm for the number of its implementations.

Comparison circuit 33 is intended to compare the number of all implementations (both completed and incomplete) 1 that are currently running and the established number of implementations 1st. The simulation of the algorithm is terminated when equality 1 1u is reached.

Counter 35 counts the number of runs performed by the algorithm.

Comparison circuit 38 compares the number of current implementation operations k that have been executed to a given time with the total number of operations in the algorithm k .. As long as condition k is satisfied, the comparison circuit generates a potential signal allowing the parity to the next operation of the current implementation. When k k 1 the circuit generates a pulse signal, signaling the completion of the current implementation.

The number of operations register 39 is intended to store and store the total number of operations, k, in the simulated algorithm, which is entered before the start of the simulation.

The counter 41 counts the number of completed operations k of the current implementation.

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The standard time register 42 is designed to store and store the standard time t, the execution of the simulated algorithm.

The comparison circuit 44 compares the duration value of the last closed-2 4t. (k number1 (

Shenna implementation t.

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Lo operations in the algorithm) with the value of the standard time of execution

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If it is done, pd, td, it is considered that it implements;

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: The test was performed in a timely manner, and the scheme generates a pulse control signal.

I Counter 46 counts the number of timely implementations;

The counter 47 counts the number of timely and accurately executed implementations. The device operates as follows;

; After the start-up device has been fed to the input: the impulse signal of the Start signal, which is fed to the input of the element OR 3; And to the single input of the trigger 31, the latter is transferred to the single state; Toe. The signal from the direct output of the trigger: generator 31 is fed to the input of register 2, | allowing writing information from memory 1 to its cells, and to the start inputs of the generators 12 and 6. From the output of the OR 3 element, a pulse arrives to the input of the counter 41 of the performed operations and the input of the trigger 18, to bring them back to the initial state. The same pulse from the output of the element OR 3 is fed to the input of the delay element 4, the delay time of which is established, based on the time required before executing the first implementation to switch the trigger 31 to a single state and ensure that register 2 is ready to record information from memory block 1 , as well as to run the generators 12 and 16, and before performing subsequent implementations to trigger the comparison circuit 33, to determine the outcome: whether to proceed to the next implementation or the algorithm modeling is fully completed, and L shift in the latter case, the trigger 31 to the initial (zero) state Yanie. From the code of the delay element 4, the signal is fed to the read input of the memory block 1. In this case, register 2 is read from block 1 memory 10

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characteristics of the first operation. The same signal from the output of the delay element 4 is fed to the input of the element OR 5, from the output of which a pulse arrives at the input of the trigger 20 and the input of the first, counter 22 errors, and before starting the next operation, they return to the initial state. The same pulse from the output of the element OR 5 arrives at the input of the delay element 6, the delay time of which is determined by the time of reliable input of information into the register 2, as well as the resetting time of the flip-flop 20. From the output of the delay element 6, the signal goes to the input of the element OR 9 and from its input to the input of register 2, permitting the issuance of information from its cells, and to the input of the generator 16 random numbers, permitting the issuance to the inputs of the circuit 19 comparing the random number.

From the outputs of register 2, the values of the mathematical expectation of the operation time and the value of the standard deviation of this time come to the inputs of the generator 12, the value of the probability of an error-free execution of this operation arrives from the outputs of the second group, to the inputs of the trigger 20 the form of a potential signal, corresponding-. O for sensorimotor operation and 1 for sensory operation. Thus, when simulating a sensorimotor operation, the second trigger 20 is in the zero state, at. From the direct output of the trigger 20, the signal to the input of the And 21 element is not reset to TjmaeT, and this element, which is 1 stitched, is closed, and the presence of the signal from the inverse output of the trigger 20 at the input of the And 10 element allows its opening under other necessary conditions . When simulating a sender, trash operation, the trigger 20 is in a single state, the element AND 21, to the input of which the signal from the direct output of the trigger 20 arrives, is open, and the element 10 is closed.

Upon receipt at the inputs of the generator 12 characteristics of the time of the operation, the generator generates and outputs a pulse to the differentiating element 13, the duration of which corresponds to the time of the operation. Differential element 13 forms and issues from its

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the first output of the converter 14 time interval is the pulse code Start, corresponding to the beginning of the time sequence, and from the second output to the second input of converter 14, the pulse End, corresponding to the end of the sequence. In the time interval converter 14, a binary number is generated corresponding to the value of the operation execution time, which is entered into the execution time register of the last operation of the adder 15.

The End signal from the second output of the differentiating element 13 also enters the input of the comparison circuit 19, permitting the comparison of the probability values entered into the circuit in advance from register 2 to correctly execute operation PJ with a random number x. from generator 16. If the operation is performed correctly, a pulse appears at the first output of the comparison circuit 19. It is fed to the input of the element OR 17 and from its output to the control input of the time adder 15. At the same time, the execution time of this operation recorded in the adder and t is summed with the total execution time of previous operations of the current implementation.

tr (/ Itj + 2 ut-). The same impulse of passing / -1 gives to the input of the element OR 23 with its

the output it enters the input of register 2, zipped the information cells of all three zones. The same pulse from the output of the comparison circuit 19 is fed to the counting input of the counter 41 of the performed operations, the contents of which k is directly fed to the inputs of the comparison circuit 38. 1 The same pulse arrives at the read input of the register 39 of the number of operation of the algorithm.

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the progress of the comparison circuit 38, the potential signal is removed, arriving at the input element I 7, opening it. output of the delay element 40, the signal is fed to the input of the delay element 8, the delay time of which is set based on the time required for the operation of the comparison circuit 3 and the subsequent opening of the closure of the element 7. From the output of the delay element 8, the signal enters the input of the open element And 7 from the output of which it enters the input of the memory block, allowing the output of the characteristics of the next operation to the register, and the input of the element OR 5. Next, the modeling of the next operation occurs as if the input signal OR 5 of the Start signal In the comparison circuit 38, it turned out that k k then the potential signal coming from its output to the input of the element And 7 is removed, the element And 7 is closed and the formation of the next operation does not start, i.e. The current implementation of the algorithm is complete. At the first output of the comparison circuit 38, a pulse appears that goes to the control input of the adder 15. The value of the total time to complete the completed implementation tj comes from the outputs of the first group of the adder 15 to the corresponding inputs of the comparison circuit 44, and in the adder itself 15 it is summed with the total time taken to complete all previous implementations of the algorithm. The impulse from the first output of the timed circuit 38 is also applied to the control input of the register 42 of the standard time, in addition, the value of the standard time of the algorithm t. is written to the comparison circuit 44. This impulse goes to the input element.

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which gives to the inputs of the circuit 38 of the comparison 43 delays, the delay time of which the value of the total quantity of go is determined by the recording time and the operation in the kj algorithm. The same information from the adder 15 and the pulse register from the output of the comparison circuit 19 is fed to the input of the delay element 40, the delay time of which is determined by the time required for the operation of the counter 41 and reliable recording in the numeric value comparison circuit 38 of the counter 41 and the register 39 From the output of the delay element 40, the signal is fed to the input of the comparison circuit 38,

42 of the standard time in the comparison circuit 44. From the output of the delay element 43, the impulse arrives at the input of the comparison circuit 44, where the comparison of the time of execution of the last realization t c with the standard time occurs.

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performed in a timely manner, from the output of the comparison circuit 44 to the input of the counter 46 an impulse comes in to count the next timely executed pea-

allow comparison of numbers written in it. If k k .., then from the second you

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the progress of the comparison circuit 38, a potential signal is taken, arriving at the input of the element AND 7, opening it. From the output of the element 40 delay signal., Is fed to the input element 8 delay. ki, the delay time of which is established, based on the time required for the operation of the comparison circuit 38 and the subsequent opening or closing of the element 7. From the output of the delay element 8, the signal goes to the input of the open element AND 7, from the output of which it goes to the input of memory block 1 ti, permitting the output to the register 2 of the characteristics of the next operation, and the input of the element OR 5. Next, the next operation is simulated as if the input of the ment OR 5 of the Start signal, If in the comparison circuit 38 it turned out to be kk, then the potential signal al coming from its output to the input of AND gate 7 is removed, AND gate 7 is closed and the formation of the next operation is not started, i.e., The current implementation of the algorithm is complete. At the first output of the comparison circuit 38, an impulse appears that goes to the control input of the adder 15. With this, the value of the total execution time of the completed implementation tj from the outputs of the first group of the adder 15 goes to the corresponding inputs of the comparison circuit 44, and in the adder 15 it is summed with the total execution time of all previous implementations of the algorithm. The impulse from the first output of the comparison circuit 38 is fed to the control input of the register 42 of the standard time, and the value of the standard time of the algorithm t is executed. is written to the comparison circuit 44. The same impulse goes to the input element

 43 delays, the delay time of which is determined by the recording time of information from the adder 15 and the register

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  43 delays, the delay time of which is determined by the recording time of information from the adder 15 and the register

42 of the standard time in the comparison circuit 44. From the output of the delay element 43, a pulse arrives at the input of the comparison circuit 44, where a comparison is made between the implementation time of the last implementation t с and the standard time

3 delays, the delay time of which is determined by the recording time and information from the adder 15 and register

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43 delays, the delay time of which is determined by the recording time of information from the adder 15 and the register

performed in a timely manner, from the output of the comparison circuit 44 to the input of the counter 46 an impulse arrives to count the next pea- executed in time.

algorithmization. The same impulse arrives at the input of the element I 45, which is the key. Element I 45 Is open, because a potential signal from the inertial output of trigger 18 arrives at its other input, it is 1 in its initial zero state starting after the pulse start, the pulse that came to the input of the element

45, passes to the input of the counter 47 1I am counting the next timely

error-free implementation

tgoritm. Thus, if in the Jiecce implementation of the current implementation, the first trigger 18 remains in the initial state, its timely detection is also recorded by the counter 46,

counter 47. The signal from the first output of the comparison circuit 38 enters the course of the element OR 37. From its output, the signal comes to the counter input of the implementations, from the output ioB of which is the number of all implementations of the simulated algorithm up to this moment (and Completed and incomplete) is fed to the inputs of the comparison circuit 33.CHI from the output of the element OR 37 also receives the 1st input of the register 32 of the set number of implementations to the control, allowing the output of the number recorded in it to the inputs of the comparison circuit 33. A signal from the output of the OR element 37 is also fed to the input of the delay element 34, the delay time of which is established, based on the response time of the counter 35 and the subsequent input of information from it into the comparison circuit 33. From the output of the delay element 34, the signal arrives at the input of the comparison circuit 33, allowing the comparison of numbers written to its registers.

1 and 1 ,. When the equality 1 1y is reached, a pulse appears at the output of the comparison circuit 33, which, arriving at the input of the trigger 31, zeroes it. The potential signal from the trigger output, which is fed to the input of register 2 and the inputs of generators 12 and 16, is removed, thereby prohibiting the recording of information from memory block 1 to the register

2 and operation of generators 12 and 16 The simulation of the algorithm is terminated.

The signal from the output of the delay element 34 is also fed to the input of the element OR 3 and further until the comparison condition is satisfied in the comparison circuit 33. Modeling 1432553 °

The realization of the next implementation of the algorithm is the same as when an element of an OR 3 impulse is received at the input. As noted earlier, the timing of the resolution of the cf ablation of the comparison and switching circuit 33 after it of the flip-flop 31 with the start time of the next implementation is provided by the presence of the delay element 4.

In the derivation in diagram 33, compare 10

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Equality 1 1y, the signal from its output also goes to the input of delay element 36, the delay time of which is determined by the time required to prevent the signal from the output of the comparison circuit 33 from arriving at the inputs of counters 46 and 47 with respect to the time of operation of the counters to count the last implementation simulated algorithm. From the output of the element 36 of the delay signal is supplied to the second inputs of the counters 46 and 47 and to the input of the adder 15 time. The value of the number of timely implementations made from the outputs of the counter 46 is fed to the inputs of the fourth group of the registration block 30, the number of implementations from the outputs of the counter 47 that are completed in a timely and error-free way goes to the inputs of the fifth group of the block 30, and from the outputs of the time accumulator 15 to the inputs of the third group of block 30, then the total value of the execution time of all completed implementations of the algorithm is taken.

If the result of the comparison in the comparison scheme 19 is the result of Xp; R., i.e. a mistake was made, a pulse appears not at the first, but at the second output of the comparison circuit 19. In the simulation of a sensorimotor operation, the characteristic of the operation. The type of operand in the form O from the third output of register 2 is applied to the single input of the trigger 20. The trigger remains in the initial zero state, which it leads after interacting to its second input, as noted, Start through the element OR 3, the element 4 delay and the element OR 5, and before carrying out the next operation - the pulse from the first output of the comparison circuit 19, the elements 40 and 48 of the delay, the element 7 and the element OR-5. From the inverse of the trigger 20 to the input element 35

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Equality 1 1y, the signal from its output also goes to the input of delay element 36, the delay time of which is determined by the time required to prevent the signal from the output of the comparison circuit 33 from arriving at the inputs of counters 46 and 47 with respect to the time of operation of the counters to count the last implementation simulated algorithm. From the output of the element 36 of the delay signal is supplied to the second inputs of the counters 46 and 47 and to the input of the adder 15 time. The value of the number of timely implementations made from the outputs of counter 46 is fed to the inputs of the fourth group of registration block 30, the number of implementations made from timely outputs of the counter 47 arrives at the inputs of the fifth group of block 30, and from the outputs of time adder 15 to the inputs of the third group of block 30, then the total value of the execution time of all completed implementations of the algorithm is taken.

If the result of the comparison in the comparison scheme 19 is the result of Xp; R., i.e. a mistake was made, a pulse appears not at the first, but at the second output of the comparison circuit 19. In the simulation of a sensorimotor operation, the characteristic of the operation. The type of operand in the form O from the third output of register 2 is applied to the single input of the trigger 20. The trigger remains in the initial zero state, which it leads after interacting to its second input, as noted, Start through the element OR 3, the element 4 delay and the element OR 5, and before carrying out the next operation - the pulse from the first output of the comparison circuit 19, the elements 40 and 48 of the delay, the element 7 and the element OR-5. From the inverse of the trigger 20 to the input element5

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That AND 10 receives the potential signal, allowing its opening, and from the direct output of the trigger, the signal to the input of the And 21 element is not applied, and the And 21 element is closed. The signal from the second output of the comparison circuit 19 does not pass through the AND 21 element, but arriving at the input of the OR element 17, passes through it to the input of the adder 15, allowing the addition of the time recorded in it for this operation (although an error has been made) with the mean time execution of all previous operations i of the current implementation. The same pulse from the second output of the comparison circuit 19 is applied to the single input of the trigger 18, which switches and stops the supply of the potential signal from its inverse output to the input of the And 45 element. The latter closes, and with any result of this implementation it will not be taken into account in the slit 47 as performed in a timely and error-free manner. The signal from the second output of the comparison circuit 19 is also fed to the input of the error counter 22, from the outputs of which the resulting value of the number is transmitted directly to the inputs of the comparison circuit 27

The same signal from the second output of the comparison circuit 19 is fed to the input of the error counter 24, to the input of the register 26 dp of resolution for the number of the number written in it. This signal is also fed to the input of the delay element 25, the delay of which is determined by the time required for the error counter 22 to operate and for inputting the number obtained in the counter 22 into the comparison circuit 27. From the output of the delay element 25, the signal arrives at the input of the comparison circuit 27, permitting the comparison of the number of errors introduced in the execution of this operation n previously entered from the counter 22 and the number of repetitions of the operation n „from register 26. When executed in diagram 27

comparing the condition nn "from the first output of the input element I 10, a potential signal arrives, which, if there is a potential signal on its other input, from the trigger 20 in the course of a sensorimotor operation, opens this element I. The signal from the output of the delay element 25 also arrives to the input element 11 of the delay, the delay time of which ope, 0

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makes the time necessary for the operation of the comparison circuit 27 and the subsequent closing or opening of the AND 10 element. From the output of the delay element 11, the signal goes to the first input of the pre-opened AND 10 element, from its output to the input of the OR element 9. Next, the re-modeling of the operad is performed , as when the Start signal arrives, through the HJIIi element 3, the delay element 6 to the first input of the element OR 9 to allow the simulation of the first one to 5 radio sets, but without first zeroing the register 2 and then entering it into its cell cristis

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 next operation.

When reaching in the comparison circuit 27, the equality n from the first output of the potential signal to the input of the element And 10 stops, the latter closes and the repetition of the simulation of this operation is prohibited. At the second output of the comparison circuit 27, a pulse arrives at the input of the element OR 28. From its terminal, the signal arrives at the first counting input of the counter 29 incomplete implementations, at the first input of the element OR 23, from the output of which, as with the correct execution of the operation, the signal arrives at the third one by zeroing the input of register 2, allowing the zeroing of its cells. The signal from the output of the sixth element OR 28 is also fed to the fifth time dryer input 15, while the value of the total

execution time of the current implementation

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JLt is erased.

When modeling a sensory operation from the third output of register 2, with the characteristics of the operation, the first unit input of the second trigger 20 is removed 1, the trigger is transferred to the unit state. In this case, the supply of a potential signal from the inverted output of the trigger 20 to the input of the element And 10 is stopped and the repetition of an unimplemented operation is prohibited. From the direct output of the trigger 20, a potential signal arrives at the input of the And 21 element, opening the latter. If, in the comparison scheme 19, the result is obtained x h P, - i.e. An error was made; the signal from the second output of the comparison circuit 19, as well as when an error occurred during the simulation of a sensorimotor operation, goes to the input of the OR element 17 and then to the input of the adder 15, allowing to sum up the execution time of this operation to the total execution time of previous implementation operations to the trigger input 18, switching it to a single state, to the counter input of the counter 24, to the counter input of the counter 22, to the read input of the register 26, to the input of the delay element 25 and. Then, at the input of the comparison circuit 27, where the values of n and pa of the signal are equalized, the delay element 25 is also removed from the output, and through the delay element 11 it enters the input of the element 10. And, despite the presence of the second input element And 10 of the potential signal from the first output of the comparison circuit Z7 (valid for Pi 1, 3 otherwise with para 1 immediately; condition nn is satisfied), the element And to is closed due to the absence of a signal at its third input from - jepcHoro trigger output 20. Therefore; simulating the simulation of the operator: it does not occur, the signal from the second code of the comparison circuit 19 through this open element I 21 arrives at the input of the element OR 28, and then the circuit works, as during the arrival. At the other input of the element 28, the signal 28 from the second output of the circuit 27 The ir, e is interrupted by the current implementation, the 1N scheme proceeds to the simulation of the next implementation, as described earlier.

Claims (1)

Invention Formula A device for simulating human operator operations, containing a memory block: the first read input of which the first delay element is connected to the output of the first OR element, the first input of which is the Start input of the device, the second read input of the memory block connected to the output of the first element I, and the outputs of the memory block are connected respectively to the bit inputs of the memory register, the bit outputs of the first group of which are connected respectively to the setup inputs of the random pulse generator, the bit outputs of the second are connected respectively to information n 5 0 0 0 five the inputs of the first group of the first comparison circuit, the recording register recording resolution input is connected to the direct output of the first trigger, the unit input of which is connected to the device Start input, the second and third delay elements, the differentiating element whose input is connected to the output of the random pulse generator, The first and second outputs of the differentiating element are connected respectively to the start input and the stop input of the time interval converter - a code, and the second output of the differential element is also connected to the enable input No comparison of the first comparison circuit connected by the information inputs of the first group to the corresponding outputs of the random number generator, the output Less than the first comparison circuit connected to the counting input of the overhead counter, the output outputs of which are connected to the information inputs of the first group of the second comparison circuit, the adder, information inputs of the first group of which are connected respectively to the outputs of the time interval converter — the code, the first read input of the time adder is connected to More progress second comparing circuit, a first group of information outputs of the adder time respectively connected to data inputs of the first group to the third comparing circuit and the second group of information outputs of the adder vre-. The menus are connected to the information inputs of the first group of the registration unit, the information inputs of the second group of which are connected to the bit outputs of the counter of incomplete implementations of the algorithm, the read input of which is connected to the output of Equal to the fourth comparison circuit and the zero input of the first comparison circuit are connected with the bit outputs of the counter vshih- from the implementations of the algorithm, the counting input of which is connected, n to the output of the second element 1SHI, the first input of which is under is connected to the output of More than the second comparison circuit, the Output of which is less connected to the first input of the first element, the output of the More second comparison circuit is also connected to the register matching input standard time, the bit outputs of which are connected to the corresponding information inputs of the second group of the third comparison circuit, the Output Less than which is connected to the counter input of the counter. timely implementations, the bit outputs of which are connected to the information inputs of the third group of the Q block of registration, the third element OR, t is characterized by the fact that, in order to expand the functionality by simulating the performance of sensory and sensorimotor 15 operations, it additionally contains a quarter, the sixth, OR, fourth, fifth, fifth, sixth, seventh, eighth, ninth delay elements, the first and second error counters are on the other side, the counter is timely and error-free implementations, the fifth comparison circuit, the register of the established number of implementations of the simulated 25 algorithm, the register of the number of operations in the algorithm, the second and third triggers, the second, third and fourth elements AND, the first input of the third element OR connected to the output of the first delay element, and the second input of the third element nta OR is connected to the output of the first element AND, and the output of the third element OR through the second delay element is connected to the first input of the fourth element SH, the output of which is connected to the input of the output register of the characteristics of the operation with the read input of the random number generator, the single input of the second trigger is connected with the output of the last bit of the memory register, the zero input of the second trigger is connected to the output of the third SHS element by the read input of the first error counter, the inverse output of the second trigger is connected to the first The second input of the second element is AND, and the direct output of the second trigger is connected to the first input of the third element AND, the second input of the terminal is connected to the output of the More First comparison circuit, with the counting run of the first error counter, the third input of the third trigger OR the reading of the register of the number of turns of the operation, the bit outputs are connected, respectively, with the information inputs of the first group 35 40 the first time ops per pen pt to sra 45 50 55 go matz blo ring key rubs the key of the key and you are on the screen with the key of the key of the second key of the key of the second key element of the key of the second key of the key. under that The fifth comparison circuit, the information inputs of the second group of which are connected respectively to the bit outputs of the first error counter, the comparison resolution resolution of the fifth comparison circuit and the input of the third delay element are connected to the output of the fourth delay element, whose input and the second error counter input are connected to output More than the first comparison circuit, the read input of the second counter opshbok and. the input of the fifth delay element connected to the output Equal to the fourth circuit that comparisons, and the bit outputs are second Q 15 2 of that 25 thirty 35 40 45 0 five The second error counter is connected to the information inputs of the fourth group of the registration unit, the output is Less than n, the comparison circuit is connected to the second input of the second element AND, the third input of which is connected to the output of the third delay element, the output of the More than five comparison circuit is connected to the first input of the sixth OR element, the second the input of which is connected to the output of the third element I, and the output to the counting input of the counter of incomplete implementations of the algorithm, with the second input of the second element OR, with the input of zeroing the time adder and the first input The second of the seventh OR element, the output of which is connected to the zeroing input of the memory register, the second input of the seventh element OR is connected to the output Smaller than the first comparison circuit, the second input of the fifth OR element, the input of the sixth delay element and the input of the register of the number of algorithm operations, the output n the OR element is connected to the enable input of the summation of the time adder, the output of the sixth delay element is connected to the enable input of the comparison of the second comparison circuit and the input of the seventh delay element whose output is Connected to the second input of the first element AND, the output of the second element AND is connected to the second input of the fourth element OR, and the output of the second element OR is connected to the input of the eighth delay element and the register read input of a set number of implementations of the algorithm, the bit outputs of which are connected respectively to the second information inputs group of the fourth comparison circuit, the input of the resolution of which is connected to the output of the eighth element