SU1320830A1 - Device for defining teaching program - Google Patents

Abstract

The invention relates to a simulator and can be used to set up a training program. The purpose of the invention is to expand the didactic capabilities of the device. This goal is achieved in that a known device containing two groups of AND elements, an address register, a first memory block, a first microinstructions register, a decoder, two OR elements, a first recorder, a first comparison block, a random code generator, the first and second groups of elements OR, first and second pulse generators, third, fourth and fifth elements OR, third and fourth groups of elements AND, trigger, counter, two delay elements, second and third comparison blocks, second number register, group PPA counters, a group of triggers, a second memory block and a second register of microinstructions with circuit connections specified in the formula. The invention allows operators to indicate the desired implementation of its algorithm in case of errors a specified number of times. 1 il. (ABOUT 00 co

Description

The invention relates to the technical means of training the operators of the ACS and can be used to create control devices for simulators for teaching the tasks of controlling a complex logical structure.

The purpose of the invention is to expand the capabilities of the device.

The drawing shows schematically a device for setting a training program.

The device contains the address register 1, the memory block 2, the micro-command register 3, the OR element 4, the random code generator 5, the comparison block 6, the AND elements 8 and 8, the decoder 9, the OR element 10, the register 11, the device 12-14 , outputs 15 of register 3, inputs 16 of device, elements 17 OR, generators 18 and 19 of pulses, elements 20-22 OR, elements 23 and 24 AND, trigger 25, counter 26, elements 27 and 28 delays, blocks 29 and 30 of comparison, a register of 31 numbers, counters 32, triggers 33, a memory block 34, a register of 35 micro-instructions, elements 36 OR, and outputs 37-39 of the device.

Register 1 is used to specify the control component of the control algorithm. It contains two parallel sections of the same capacity, in the first of which the codes of operator sequence numbers are written in the cells. They are used to determine the starting times of the generator 5 (first outputs of register 1), the opening moments of elements 7 and 8 for influencing the information inputs of blocks 2 and 34, and also for issuing control actions (fourth information outputs of register 1) through elements 24 and the inputs of the first unit 2. In the second section of register 1, control codes are recorded, which, according to the operator number, affect the human operator on the control panel panel of the simulator. E, the capacity of sections of register 1 is determined by the number of operations of the control algorithm, the number of bits, the cell of the first section is also determined by the number of operations of the algorithm.

The bit width of the second section of register 1 is determined depending on the number of controls of the corresponding panel of the operator’s console.

The shift by one cell of register 1 is performed by the receipt of a signal at its input by element 22, when a signal is received from the second input of which the shift is made by the number of operators between the arrows indicating the transition (up and down arrows).

Block 2 is designed to store the parameters of the algorithm. In this case, microcommands are stored in this block, and in block 34 there are operators corresponding to opposite outcomes when the logical operators are triggered.

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A call to block 35 is made only if the human operator has made a mistake in choosing the desired implementation of the control algorithm.

Register 3 contains four, and register 35 contains three micro-operations. At the same time, in the first microoperations, the codes of the control panel bodies of the simulator operator console are stored, which the operator should influence in this operation of the algorithm. In the second microoperations of registers 3 and 35, the values of the codes of the organs of the indication panels of the simulator operator console are stored, which change their state in this operation of the control algorithm 5. In the third microoperations of these registers, a code is stored for the value of the delay time of the corresponding indication bodies to take into account the peculiarities of the operation of the control objects. In the fourth micro-operation, register 3 0 stores the value of the probability of occurrence of one of the outcomes of the logical operator. At the same time, the fourth micro-operation contains micro-instructions that precede the played logical operators.

The generator 5 is designed to specify a random number that is uniformly distributed in the interval up to 1.

Block 6 is designed to determine the occurrence of one outcome or other of the logical condition of the algorithm by comparing the probability value corresponding to one of the outcomes of the logical condition with a random number generated by the generator 5.

Elements 7 and 8 function as switching devices, allowing C to determine the address of the next microcommand in the first 2 and in the second 34 memory blocks, depending on what outcome the logical condition of the algorithm took. The number of elements 7 and 8 is equal to the number of logical conditions of the control algorithm.

The decryptor 9 is designed to unambiguously compare the cell number of the register 1, which corresponds to the position number of the operator, i.e., the operation number of the algorithm — the required elements 7 and 8.

Register 11 is intended to store the probability value of one of the outcomes of a logical condition. This value is written to register 11 at its inputs from the fourth micro-operation of the block 2 micro-instructions preceding the logic operators.

One input of register 11 is designed to control the reading of information in block 6, and the other input to reset register 1 1.

The outputs 12 are connected to the control authorities that should be involved in this implementation of the algorithm, the outputs 39 of the device are connected directly to the controls that must be

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us to be involved by operators. In this case, in the case of an incorrect choice by the operator of the required implementation of the control algorithm after logical operations, these organs are illuminated by a flashing light. In this case, the control code recorded in the Perzoy micro-operation of register 35 enters via outputs 39 to the required control panel of the operator’s console and illuminates it with a flashing light. Output 13) Heister 3 and output 37 of register 35 are intended; You can control the display elements of the operator’s console. In this case, in the event of an erroneous selection of the required implementation, the necessary display elements will also be illuminated by a flashing light. The output 14 of the register 3 and the output 38 of the register 35 are designed to control the delay of some of the display elements of the operator console panel in accordance with the operation features of the control panel. Exit 15 is intended to overwrite the probability value of one of the outcomes of the subsequent logical condition in register 11.

The input 16 is intended for inputting into the device the code of the control body involved by the human operator when performing the current operation of the control algorithm.

The generator 18 is designed to control the shift of reading information from register 1. For example, if the first logic condition is triggered, the operator after the second operation has to go to the seventh operation, the code corresponding to the seventh cell of the second section of the register will appear at the outputs of register 1. 1. This shift is made by the generator 18.

The generator 19 is designed for flashing illumination to a human operator of a desired control, assuming it is an error in selecting the necessary implementation, after working out the logical condition of the control algorithm.

Elements 23 and 24 perform key functions.

The trigger 25 controls the length of the / p-guest operation of the generator 18.

Counter 26 is designed to count the number of errors made by the operator when performing operations of the control algorithm.

Block 29 is intended to compare the number of errors committed to the number of s.vI.

The unit 30 is designed to compare the codes of the involved and the required control panels of the operator’s console, which makes it possible to record the fact that an error has occurred.

Hegister 31 is intended to store the number corresponding to the allowable number of errors, when exceeded, the operator will be prompted

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by issuing. 1 lsov generator 19 .v: "Sub: Etcn TUcoveNiorc control panel organ; - :.

The group of subtractive counters 32 of the pre ;; - is the number of assignments for the number of shift tags (jump) of the cells oei HCTpa 1, after the logical operators have triggered. So. .l paccMHTpHBacN oro; In the first match of the algorithm 32, the number 3 will be written (the difference between σ; Inik: operators), and in the second - 4 (the difference between the other ikp; operators). These are 1 census records. counters 32 before pack hp; - ycTpoiiCTBa 1ra-llenc tro.

, cp o and c t o f u n c c i o n and p} with t barely d u w - di m way.

When “1 :: ni” of the simulator is turned on, select the first operation of the algorithm. Dunn :: signal produced to overwrite content) of the first microcommand from block 2 to reg: page 3, which leads to the appearance of signals at the outputs 12-14 of the device. Etc;; This is the organization that should be in charge. Operated by the operator IO .hi- Regisgra 1 moves, rewritten from}: the second section of register I to block 30. After issuing. Human. m-slterator corresponding to 1 control; about the effects at the inputs 6 of the construction code according to the opraiip code. Pezl; un. on which impact .: c.orpek-opeuutor. Dsl, l .ol enters the inputs of block 30, in KOTOpojii, a comparison is made of the correspondent action of cneprrroi; oM of the governing body. required: - body. In the case of coincidence of the received KO.:ICR signal appears at the output of the block - 30, which is sent to the input | of the elements 24 and i-; a return of the element 22, the signal on. one csg | ku in register 1 next in both sec. the next Alli Ori operation is set by the “unscrupulous operator, then the signals GET ON the outputs of the register 1 and through the open elements 24 arrive; and the inputs of the block 2 where the selection of the appropriate command is performed; the micro-command and its recruits into regist 3. Other than In addition, the signal is on Rtv- ho. Gamgics p l I from the second second ceKiu-i; . ;; census1 in Gl.i ..; M) and the cycle of work -., Repetition devices; - in the order described.

In the case, onepai contour: ;; : Is logical. Slanp i.; iropHTN.i. i.e., denoted by some operator, then i; the preceding oiioptMUin, and the 1st decade of the microscope micros, ce; Oder. Part ncpcinioi-i- is registered in the register 1 1 from the inputs 15 of the register 3. With the mode. Ira: None11. p. A condition of the algorithm appears:: from the output and output outputs per iCTj) a 1, nep; -bio whose halls are connected to those HCiMcp: -; vi hss ;; og; 1Stra 1. which correspond to the sequence number of the operator, and through s. ieMcn -1 enters pa 5, input

register 1, to overwrite the value: the likelihood of triggering one of the outcomes of the logical condition in block 6, and gaizhe-iii trigger input 25. The resulting random number, distributed evenly in the i-uiTcp-shaft O-1, goes to block 6 for matching It does not come with the number 1 received from register 1 at the inputs of block 6. If, as a result of the comparison, it turns out that random CC1,: io is less than the probability of an increase, and the outcome of the operator’s response, those signals appear at the outputs of block 6 and The address of the next micro-command is selected in the way that the human operator py need:; o move on to the fulfillment of the next onerapin. Otherwise, i.e., if the random number is greater than the operator's probability of tripping, s | -flc-s at the output of block 6 and the operator must perform certain operations.

The choice of one or another micro-command is made by the appearance of signals on Br, 1-strokes of elements 7 and 8. Signals at the outputs of elements 7 appear when signals arrive at one of their inputs from the output of block 6, and at other inputs of elements 7 - from the output of the decoder 9. Element 10 is intended to reset the register 1 1 after working out the operation corresponding to the logical operator. At the input of the dexfractor 9, a code is received that corresponds to | T) - tions to the numbers of the cells of the first section of register 1., intended for the storage of serial numbers of operators. In case of c, 1e1 {and the signal at the output of b, b, the corresponding elements 8 and / homer of the next operation of the algorithm are triggered, information about the need for execution of which must be presented to the human operator will be presented due to the appearance of the signal from the second micro-operation of the register - 35 through the device outputs 37 to the corresponding display indication memory of the simulator console. In addition, the signal; at the output of the decoder 9, the triggering switch 3-3 E is a single state, which ensures that the signal from its output reaches the input of the corresponding element 23 and prepares it for opening. The output from the output of the element 8 through the element 21 is fed to the start input of the generator 18 and the input of the element 28. The pulses from the output of the generator 18 are received through the open element 23 to the corresponding subtractive counter 32, the pulses from the output of which through the element 20 and the input of the element 22 arrive to the input of register 1 and make a shift to the CMC cells, how many pulses are recorded from the C - slider 32. At the same time, in block 30, the code of the control is copied from the second register 1, which corresponds to the required control of the correct implementation algorithm. The delay delay of the element 28 is selected and

taking into account m; -1Ks - it is possible to count the number of i.pulses, write X in the counter; -; kakh 32. After expiration of h ;; th time, the signal / output of element 28 enters the trigger exit 25, and the signal from its -Only installed, all three merits are set: 33 the state (n} le-vo5) stops the generator at the end;

This is how the device operates (operating the device with error-free operator actions. In the event of a supplementary error, the operator acts as follows. Assume that the operator must perform the action, s; are valid for one operator, and oi-; another operation. In this case, the signals appear on the inputs of the device 12. In block 30, the code: - .: the required and affected controls do not match, and the signal is GUYABLE to its output and :. Next, Oii goes to the counter 26, from the output of which - to e, / 1st 27 and register 31. In this data, the reg. stre

0 recorded a valid O1nibok number of the operator. If the operator has exceeded this number, the signal from the output of block 29 is fed to the input of the generator 19 and starts it. I. pulse from its output nocTyiiaKjT-through the inputs of the elements 17 and 26 d „| I am flashed5

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The new backlight is of-o-FiepaTor and the required opi-anvans for control of the operator's zero panel. After being eliminated by the human o; op. ibki gyu c. Young: usa pa; 1a lia output of block 30, prolzduDGgs ob1: best of the counter 26 and the axis of the new generator 19.

The proposed condition: the pos1O1 – C t i) ac-shear didactic property; : e capabilities of the simulator due to blocking the One Action of the developer and by providing noj, - a fairy tale when allowing errors in the operations of acceptance to select the necessary further implementation of the algorithm y: i - distribution.

Forms at l and from lies

A device for specifying the training program frame 01, containing the g-ergist ;: adg esch, the output of the rpyruHj KOTOpoi O is the first with the corresponding inputs. first element

OR, the KOTOpoi O output is connected to the generator with: a pair of codes and to the input of the first register of the number register; the set input is connected to the output of the second OR element. Information inputs with

the corresponding outputs of the first are grouped by the first registrar) and microinstructions, and the outputs are with the corresponding (steps of the first group of the first comparison unit, the inputs of the second soil of which are connected to the corresponding

the outputs of the random code generator, the first output to the first inputs of the second element OR and the elements of the nerve group, and the second output to the second input of the second element OR and the first inputs of the elements AND of the second group, the second inputs of the elements AND of the first and second groups are connected to the corresponding outputs of the decoder, the inputs of which are connected to the corresponding outputs of the second group of the address register, the outputs of the elements AND of the first group are connected to the corresponding information inputs of the first memory block, the outputs of which connected to the corresponding inputs of the first register of microinstructions, the outputs of the second and third groups of which are the corresponding information outputs of the first and second groups of the device, characterized in that, in order to expand the didactic capabilities of the device, the first and second groups of elements OR, first and second pulse generators, the third, fourth and fifth elements OR, the third and fourth groups of elements AND, the trigger, the counter, the first and second delay elements, the second and third blocks of comparison, the second register numbers, a group of counters, a group of flip-flops, a second memory block and a second register of micro-instructions, whose inputs are connected to the corresponding outputs of the second memory block, the outputs of the first group to the first inputs of the corresponding OR elements of the second group, and the outputs of the second and third groups are corresponding information outputs of the third and fourth groups of the device, the first inputs of the elements OR of the first group are connected to the corresponding outputs of the fourth group of the first register of micro-commands, the second inputs of the elements OR of the first and The second groups are connected to the output of the second pulse generator, and the outputs are the corresponding information outputs of the fifth and sixth groups of the device, respectively, the inputs of the first group of the third comparison unit are connected to the corresponding outputs of the third group of the address register.

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the first output is to the first inputs of the fifth OR element and elements of the fourth group and the installation inputs of the counter and the second pulse generator, the inputs of the second group of the third comparison unit are the corresponding inputs of the device, and the second output is connected to the information input of the counter, the output of which is connected to the inputs The second register of the number and the first delay element, the output of which is connected to the first input of the second comparison unit, the second input of which is connected to the output of the second number register, and the output to the start input is second pulse generator, the second inputs of the elements of the fourth group are connected to the corresponding outputs of the fourth group of the address register, and the outputs to the corresponding address inputs of the first memory block, the inputs of the second memory block are connected to the outputs of the corresponding elements of the second group connected to the corresponding inputs of the fourth element OR, the output of which is connected to the start input of the first pulse generator and the input of the second delay element, the output of which is connected to the S-input of the trigger, the / -input of which is connected En to the output of the first element OR, and the output to the / -inputs of group triggers and the stop input of the first generator, the output of which is connected to the first inputs of elements AND of the third group, the second inputs of which are connected to the outputs of the corresponding group triggers, S-inputs of which are connected to the corresponding outputs of the decoder, the outputs of the elements of the third group are connected to the information inputs of the corresponding group counters, the outputs of which are connected to the corresponding inputs of the third OR element, the output of which is connected to the second input One of the first OR element, the output of which is connected to the information input of the address register.

Claims (1)

A device for setting a training program containing an address register, the outputs of the first group of which are connected to the corresponding inputs of the first element ⁴⁵ OR, the output of which is connected to the input of the random code generator and to the write enable input of the first register of the number, the installation input of which is connected to the output of the second element OR. information inputs ...... with the corresponding outputs of the first group of the first register of microcommands, and the outputs with the corresponding inputs of the first group of the first comparison unit, the inputs of the second group of which are connected to the corresponding 55 outputs of the random code generator, the first output to the first the inputs of the second OR element and the AND elements of the first group, and the second output to the second input of the second OR element and the first inputs of the AND elements of the second group, the second inputs of the AND elements of the first and second groups are connected to the corresponding the outputs of the decoder, whose inputs are connected to the corresponding outputs of the second group of the address register, the outputs of the And elements of the first group are connected to the corresponding information inputs of the first memory block, the outputs of which are connected to the corresponding inputs of the first register of microcommands, the outputs of the second and third groups of which are the corresponding information outputs of the first and the second group of the device, characterized in that, in order to expand the didactic capabilities of the device, the first and second g groups of OR elements, first and second pulse generators, third, fourth and fifth OR elements, third and fourth groups of AND elements, trigger, counter, first and second delay elements, second and third comparison blocks, second number register, group of counters, group flip-flops, the second memory block and the second register of microcommands, the inputs of which are connected to the corresponding outputs of the second memory block, the outputs of the first group - with the first inputs of the corresponding elements of the second group, and the outputs of the second and third groups are corresponding the information outputs of the third and fourth groups of the device, the first inputs of the OR elements of the first group are connected to the corresponding outputs of the fourth group of the first register of microcommands, the second inputs of the OR elements of the first and second groups are connected to the output of the second pulse generator, and the outputs are the corresponding information outputs of the fifth and sixth groups devices, respectively, the inputs of the first group of the third comparison unit are connected to the corresponding outputs of the third group of the address register, the first output to to the inputs of the fifth OR element and the And elements of the fourth group and the installation inputs of the counter and the second pulse generator, the inputs of the second group of the third comparison unit are the corresponding inputs of the device, and the second output is connected to the information input of the counter, the output of which is connected to the inputs of the second register of the number and the first element delays, the output of which is connected to the first input of the second comparison unit, the second input of which is connected to the output of the second register of the number, and the output to the start input of the second pulse generator s, the second inputs of the AND elements of the fourth group are connected to the corresponding outputs of the fourth group of the address register, and the outputs are connected to the corresponding address inputs of the first memory block, the inputs of the second memory block are connected to the outputs of the corresponding AND elements of the second group connected to the corresponding inputs of the fourth OR element, output which is connected to the start input of the first pulse generator and the input of the second delay element, the output of which is connected to the S-input of the trigger, /? - the input of which is connected to the output of the first ele OR, and the output - to / ^ - the inputs of the triggers of the group and the stop input of the first generator, the output of which is connected to the first inputs of the AND elements of the third group, the second inputs of which are connected to the outputs of the corresponding triggers of the group, The S-inputs of which are connected to the corresponding outputs of the decoder, the outputs of the AND elements of the third group are connected to the information inputs of the corresponding counters of the group, the outputs of which are connected to the corresponding inputs of the third OR element, the output of which is connected to the second input of the first OR element, the output of which is connected to the register information input addresses.