JPS6110974B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a method for forming alignment marks used in electron beam direct exposure.

For example, when forming extremely fine wiring patterns and electrode patterns in integrated circuits, etc., a forming method using direct exposure using an electron beam is generally used.

However, the conventional method for forming alignment marks used in direct electron beam exposure involves photoprocessing at two or more locations on the surface of a silicon wafer on which integrated circuit elements are to be formed by wafer processing. The method was to form uneven marks by etching or vapor deposition.

However, since this alignment mark forming method forms alignment marks directly on the silicon wafer surface, it is not possible to form elements at or near the mark position, which reduces the degree of integration of elements per wafer. Since the marks are formed as steps in the resist, there have been problems such as low mark detection sensitivity due to differences in the amount of reflected electrons and poor positioning accuracy.

In view of the above-mentioned problems, the present invention provides a method for forming alignment marks with good detection sensitivity without reducing the degree of integration of elements during direct electron beam exposure.

That is, the present invention is characterized in that alignment marks for semiconductor wafers used in direct electron beam exposure are formed on a resist for electron beam exposure applied to the wafer using a material having a different electron reflectance from that of the resist. shall be.

The present invention will be explained in detail below with reference to Examples.

1 to 4 are process explanatory diagrams of the present invention.

First, as shown in FIG. 1, on the surface of a silicon wafer 1 on which elements have been formed through a series of wafer processes such as element isolation diffusion, base resistance diffusion, and emitter diffusion in the manufacture of semiconductor integrated circuits,
For example, a polyisoprene-based electron beam exposure resist layer (hereinafter referred to as EB resist layer) 2 has a thickness of 1 μm.
After applying the EB resist 2 to a certain thickness,
A photoresist layer 3 of a novolac type such as AZ-1350, for example, is formed to a thickness of about 0.5 .mu.m.

However, as shown in FIG. 2, after forming a mark pattern 4 on the photoresist layer 3 by photolithography, as shown in FIG. A resist for electron beam exposure with a thickness of about 0.1 μm and mark forming material thin film layers 5a and 5b made of gold, chromium, etc. having different electron reflectances are then formed by a lift-off method. The mark forming material thin film layer 5b on the resist layer 3 is removed, and the EB resist is coated on the silicon wafer 1 as shown in FIG. 4, and fine wiring patterns and electrode patterns are to be directly exposed to an electron beam. A mark pattern 4 is formed on the layer 2 by a mark forming material thin film layer 5a.

Although the above embodiments have been described with respect to processes in the manufacture of semiconductor integrated circuits, it goes without saying that the method of the present invention can be applied to the manufacture of other semiconductor devices.

As explained above, since the present invention is a method of forming alignment marks on a resist for electron beam exposure, the alignment marks do not reduce the degree of integration of elements, and can be placed in large numbers at convenient locations for alignment. This makes it possible to form individual alignment marks. Furthermore, since alignment marks can be formed using a material whose electron reflectance is significantly different from that of a resist film for electron beam exposure, the detection sensitivity of marks is increased and alignment accuracy is improved, which facilitates the production of semiconductor devices such as semiconductor integrated circuits. It is extremely effective in improving the degree of integration, manufacturing yield, and reliability.

[Brief explanation of the drawing]

1 to 4 are process explanatory diagrams of an embodiment of the present invention. In the figure 1...silicon wafer, 2...
EB resist layer, 3...Photoresist layer, 4...
... Mark pattern, 5a, 5b... Thin film layer of mark forming material.

Claims (1)

[Claims] 1. A position characterized in that alignment marks for a semiconductor wafer used in electron beam direct exposure are formed on a resist for electron beam exposure applied to the wafer using a material having a different electron reflectance from that of the resist. How to form alignment marks.