JPS61103228A - クロツク制御回路 - Google Patents

クロツク制御回路

Info

Publication number
JPS61103228A
JPS61103228A JP59225561A JP22556184A JPS61103228A JP S61103228 A JPS61103228 A JP S61103228A JP 59225561 A JP59225561 A JP 59225561A JP 22556184 A JP22556184 A JP 22556184A JP S61103228 A JPS61103228 A JP S61103228A
Authority
JP
Japan
Prior art keywords
clock
output
flop
flip
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59225561A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0332086B2 (enrdf_load_stackoverflow
Inventor
Osamu Toyama
修 遠山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP59225561A priority Critical patent/JPS61103228A/ja
Publication of JPS61103228A publication Critical patent/JPS61103228A/ja
Publication of JPH0332086B2 publication Critical patent/JPH0332086B2/ja
Granted legal-status Critical Current

Links

JP59225561A 1984-10-26 1984-10-26 クロツク制御回路 Granted JPS61103228A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59225561A JPS61103228A (ja) 1984-10-26 1984-10-26 クロツク制御回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59225561A JPS61103228A (ja) 1984-10-26 1984-10-26 クロツク制御回路

Publications (2)

Publication Number Publication Date
JPS61103228A true JPS61103228A (ja) 1986-05-21
JPH0332086B2 JPH0332086B2 (enrdf_load_stackoverflow) 1991-05-09

Family

ID=16831225

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59225561A Granted JPS61103228A (ja) 1984-10-26 1984-10-26 クロツク制御回路

Country Status (1)

Country Link
JP (1) JPS61103228A (enrdf_load_stackoverflow)

Also Published As

Publication number Publication date
JPH0332086B2 (enrdf_load_stackoverflow) 1991-05-09

Similar Documents

Publication Publication Date Title
US7079441B1 (en) Methods and apparatus for implementing a power down in a memory device
US6338127B1 (en) Method and apparatus for resynchronizing a plurality of clock signals used to latch respective digital signals, and memory device using same
US6134182A (en) Cycle independent data to echo clock tracking circuit
JP3180317B2 (ja) 半導体記憶装置
US6493829B1 (en) Semiconductor device enable to output a counter value of an internal clock generation in a test mode
US7408394B2 (en) Measure control delay and method having latching circuit integral with delay circuit
US7050352B2 (en) Data input apparatus of DDR SDRAM and method thereof
JPH0817182A (ja) 論理データ入力ラッチ回路
USRE41441E1 (en) Output buffer having inherently precise data masking
US6028448A (en) Circuitry architecture and method for improving output tri-state time
JPH01285088A (ja) 半導体記憶装置
JPS61103228A (ja) クロツク制御回路
JP3686265B2 (ja) 内部クロック発生回路
US6301188B1 (en) Method and apparatus for registering free flow information
JP2001035155A (ja) パイプレジスタ及びそれを備えた半導体メモリ素子
JP2981870B2 (ja) ライト制御回路
JPS6221196B2 (enrdf_load_stackoverflow)
KR20020037525A (ko) 지연 락 루프 회로를 구비한 동기형 반도체 메모리 장치
JP2682502B2 (ja) 不揮発性メモリの出力データのローディングタイミング方法及び回路
KR100653972B1 (ko) 반도체메모리장치의 데이터 출력 제어 방법 및 장치
JP3740312B2 (ja) Ｃａｍセル回路
KR100633334B1 (ko) 디디알 에스디램의 데이터 입력 제어 방법 및 장치
JPH11238382A (ja) 半導体メモリ装置
JPH05166376A (ja) 半導体集積回路装置
JPH03237688A (ja) 半導体出力回路

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees